SAM4SD32-SAM4S-EK2-IMT-Docs/html/instance__adc_8h_source.html

/*

 * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>

 */


#ifndef _SAM4S_ADC_INSTANCE_

#define _SAM4S_ADC_INSTANCE_


/* ========== Register definition for ADC peripheral ========== */

#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

  #define REG_ADC_CR                    (0x40038000U)

  #define REG_ADC_MR                    (0x40038004U)

  #define REG_ADC_SEQR1                  (0x40038008U)

  #define REG_ADC_SEQR2                  (0x4003800CU)

  #define REG_ADC_CHER                  (0x40038010U)

  #define REG_ADC_CHDR                  (0x40038014U)

  #define REG_ADC_CHSR                  (0x40038018U)

  #define REG_ADC_LCDR                  (0x40038020U)

  #define REG_ADC_IER                   (0x40038024U)

  #define REG_ADC_IDR                   (0x40038028U)

  #define REG_ADC_IMR                   (0x4003802CU)

  #define REG_ADC_ISR                   (0x40038030U)

  #define REG_ADC_OVER                  (0x4003803CU)

  #define REG_ADC_EMR                   (0x40038040U)

  #define REG_ADC_CWR                   (0x40038044U)

  #define REG_ADC_CGR                   (0x40038048U)

  #define REG_ADC_COR                   (0x4003804CU)

  #define REG_ADC_CDR                   (0x40038050U)

  #define REG_ADC_ACR                   (0x40038094U)

  #define REG_ADC_WPMR                  (0x400380E4U)

  #define REG_ADC_WPSR                  (0x400380E8U)

  #define REG_ADC_RPR                   (0x40038100U)

  #define REG_ADC_RCR                   (0x40038104U)

  #define REG_ADC_RNPR                  (0x40038110U)

  #define REG_ADC_RNCR                  (0x40038114U)

  #define REG_ADC_PTCR                  (0x40038120U)

  #define REG_ADC_PTSR                  (0x40038124U)

#else

  #define REG_ADC_CR   (*(__O  uint32_t*)0x40038000U)

  #define REG_ADC_MR   (*(__IO uint32_t*)0x40038004U)

  #define REG_ADC_SEQR1 (*(__IO uint32_t*)0x40038008U)

  #define REG_ADC_SEQR2 (*(__IO uint32_t*)0x4003800CU)

  #define REG_ADC_CHER (*(__O  uint32_t*)0x40038010U)

  #define REG_ADC_CHDR (*(__O  uint32_t*)0x40038014U)

  #define REG_ADC_CHSR (*(__I  uint32_t*)0x40038018U)

  #define REG_ADC_LCDR (*(__I  uint32_t*)0x40038020U)

  #define REG_ADC_IER  (*(__O  uint32_t*)0x40038024U)

  #define REG_ADC_IDR  (*(__O  uint32_t*)0x40038028U)

  #define REG_ADC_IMR  (*(__I  uint32_t*)0x4003802CU)

  #define REG_ADC_ISR  (*(__I  uint32_t*)0x40038030U)

  #define REG_ADC_OVER (*(__I  uint32_t*)0x4003803CU)

  #define REG_ADC_EMR  (*(__IO uint32_t*)0x40038040U)

  #define REG_ADC_CWR  (*(__IO uint32_t*)0x40038044U)

  #define REG_ADC_CGR  (*(__IO uint32_t*)0x40038048U)

  #define REG_ADC_COR  (*(__IO uint32_t*)0x4003804CU)

  #define REG_ADC_CDR  (*(__I  uint32_t*)0x40038050U)

  #define REG_ADC_ACR  (*(__IO uint32_t*)0x40038094U)

  #define REG_ADC_WPMR (*(__IO uint32_t*)0x400380E4U)

  #define REG_ADC_WPSR (*(__I  uint32_t*)0x400380E8U)

  #define REG_ADC_RPR  (*(__IO uint32_t*)0x40038100U)

  #define REG_ADC_RCR  (*(__IO uint32_t*)0x40038104U)

  #define REG_ADC_RNPR (*(__IO uint32_t*)0x40038110U)

  #define REG_ADC_RNCR (*(__IO uint32_t*)0x40038114U)

  #define REG_ADC_PTCR (*(__O  uint32_t*)0x40038120U)

  #define REG_ADC_PTSR (*(__I  uint32_t*)0x40038124U)

#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


#endif /* _SAM4S_ADC_INSTANCE_ */