SAM4SD32 (SAM4S-EK2)
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instance_adc.h File Reference

Copyright (c) 2012-2018 Microchip Technology Inc. More...

Go to the source code of this file.

Macros

#define REG_ADC_ACR   (*(__IO uint32_t*)0x40038094U)
 (ADC) Analog Control Register
#define REG_ADC_CDR   (*(__I uint32_t*)0x40038050U)
 (ADC) Channel Data Register
#define REG_ADC_CGR   (*(__IO uint32_t*)0x40038048U)
 (ADC) Channel Gain Register
#define REG_ADC_CHDR   (*(__O uint32_t*)0x40038014U)
 (ADC) Channel Disable Register
#define REG_ADC_CHER   (*(__O uint32_t*)0x40038010U)
 (ADC) Channel Enable Register
#define REG_ADC_CHSR   (*(__I uint32_t*)0x40038018U)
 (ADC) Channel Status Register
#define REG_ADC_COR   (*(__IO uint32_t*)0x4003804CU)
 (ADC) Channel Offset Register
#define REG_ADC_CR   (*(__O uint32_t*)0x40038000U)
 (ADC) Control Register
#define REG_ADC_CWR   (*(__IO uint32_t*)0x40038044U)
 (ADC) Compare Window Register
#define REG_ADC_EMR   (*(__IO uint32_t*)0x40038040U)
 (ADC) Extended Mode Register
#define REG_ADC_IDR   (*(__O uint32_t*)0x40038028U)
 (ADC) Interrupt Disable Register
#define REG_ADC_IER   (*(__O uint32_t*)0x40038024U)
 (ADC) Interrupt Enable Register
#define REG_ADC_IMR   (*(__I uint32_t*)0x4003802CU)
 (ADC) Interrupt Mask Register
#define REG_ADC_ISR   (*(__I uint32_t*)0x40038030U)
 (ADC) Interrupt Status Register
#define REG_ADC_LCDR   (*(__I uint32_t*)0x40038020U)
 (ADC) Last Converted Data Register
#define REG_ADC_MR   (*(__IO uint32_t*)0x40038004U)
 (ADC) Mode Register
#define REG_ADC_OVER   (*(__I uint32_t*)0x4003803CU)
 (ADC) Overrun Status Register
#define REG_ADC_PTCR   (*(__O uint32_t*)0x40038120U)
 (ADC) Transfer Control Register
#define REG_ADC_PTSR   (*(__I uint32_t*)0x40038124U)
 (ADC) Transfer Status Register
#define REG_ADC_RCR   (*(__IO uint32_t*)0x40038104U)
 (ADC) Receive Counter Register
#define REG_ADC_RNCR   (*(__IO uint32_t*)0x40038114U)
 (ADC) Receive Next Counter Register
#define REG_ADC_RNPR   (*(__IO uint32_t*)0x40038110U)
 (ADC) Receive Next Pointer Register
#define REG_ADC_RPR   (*(__IO uint32_t*)0x40038100U)
 (ADC) Receive Pointer Register
#define REG_ADC_SEQR1   (*(__IO uint32_t*)0x40038008U)
 (ADC) Channel Sequence Register 1
#define REG_ADC_SEQR2   (*(__IO uint32_t*)0x4003800CU)
 (ADC) Channel Sequence Register 2
#define REG_ADC_WPMR   (*(__IO uint32_t*)0x400380E4U)
 (ADC) Write Protect Mode Register
#define REG_ADC_WPSR   (*(__I uint32_t*)0x400380E8U)
 (ADC) Write Protect Status Register

Detailed Description

Copyright (c) 2012-2018 Microchip Technology Inc.

and its subsidiaries.

\cond ASF_LICENSE

Definition in file instance_adc.h.

Macro Definition Documentation

◆ REG_ADC_ACR

#define REG_ADC_ACR   (*(__IO uint32_t*)0x40038094U)

(ADC) Analog Control Register

Definition at line 86 of file instance_adc.h.

◆ REG_ADC_CDR

#define REG_ADC_CDR   (*(__I uint32_t*)0x40038050U)

(ADC) Channel Data Register

Definition at line 85 of file instance_adc.h.

◆ REG_ADC_CGR

#define REG_ADC_CGR   (*(__IO uint32_t*)0x40038048U)

(ADC) Channel Gain Register

Definition at line 83 of file instance_adc.h.

◆ REG_ADC_CHDR

#define REG_ADC_CHDR   (*(__O uint32_t*)0x40038014U)

(ADC) Channel Disable Register

Definition at line 73 of file instance_adc.h.

◆ REG_ADC_CHER

#define REG_ADC_CHER   (*(__O uint32_t*)0x40038010U)

(ADC) Channel Enable Register

Definition at line 72 of file instance_adc.h.

◆ REG_ADC_CHSR

#define REG_ADC_CHSR   (*(__I uint32_t*)0x40038018U)

(ADC) Channel Status Register

Definition at line 74 of file instance_adc.h.

◆ REG_ADC_COR

#define REG_ADC_COR   (*(__IO uint32_t*)0x4003804CU)

(ADC) Channel Offset Register

Definition at line 84 of file instance_adc.h.

◆ REG_ADC_CR

#define REG_ADC_CR   (*(__O uint32_t*)0x40038000U)

(ADC) Control Register

Definition at line 68 of file instance_adc.h.

◆ REG_ADC_CWR

#define REG_ADC_CWR   (*(__IO uint32_t*)0x40038044U)

(ADC) Compare Window Register

Definition at line 82 of file instance_adc.h.

◆ REG_ADC_EMR

#define REG_ADC_EMR   (*(__IO uint32_t*)0x40038040U)

(ADC) Extended Mode Register

Definition at line 81 of file instance_adc.h.

◆ REG_ADC_IDR

#define REG_ADC_IDR   (*(__O uint32_t*)0x40038028U)

(ADC) Interrupt Disable Register

Definition at line 77 of file instance_adc.h.

◆ REG_ADC_IER

#define REG_ADC_IER   (*(__O uint32_t*)0x40038024U)

(ADC) Interrupt Enable Register

Definition at line 76 of file instance_adc.h.

◆ REG_ADC_IMR

#define REG_ADC_IMR   (*(__I uint32_t*)0x4003802CU)

(ADC) Interrupt Mask Register

Definition at line 78 of file instance_adc.h.

◆ REG_ADC_ISR

#define REG_ADC_ISR   (*(__I uint32_t*)0x40038030U)

(ADC) Interrupt Status Register

Definition at line 79 of file instance_adc.h.

◆ REG_ADC_LCDR

#define REG_ADC_LCDR   (*(__I uint32_t*)0x40038020U)

(ADC) Last Converted Data Register

Definition at line 75 of file instance_adc.h.

◆ REG_ADC_MR

#define REG_ADC_MR   (*(__IO uint32_t*)0x40038004U)

(ADC) Mode Register

Definition at line 69 of file instance_adc.h.

◆ REG_ADC_OVER

#define REG_ADC_OVER   (*(__I uint32_t*)0x4003803CU)

(ADC) Overrun Status Register

Definition at line 80 of file instance_adc.h.

◆ REG_ADC_PTCR

#define REG_ADC_PTCR   (*(__O uint32_t*)0x40038120U)

(ADC) Transfer Control Register

Definition at line 93 of file instance_adc.h.

◆ REG_ADC_PTSR

#define REG_ADC_PTSR   (*(__I uint32_t*)0x40038124U)

(ADC) Transfer Status Register

Definition at line 94 of file instance_adc.h.

◆ REG_ADC_RCR

#define REG_ADC_RCR   (*(__IO uint32_t*)0x40038104U)

(ADC) Receive Counter Register

Definition at line 90 of file instance_adc.h.

◆ REG_ADC_RNCR

#define REG_ADC_RNCR   (*(__IO uint32_t*)0x40038114U)

(ADC) Receive Next Counter Register

Definition at line 92 of file instance_adc.h.

◆ REG_ADC_RNPR

#define REG_ADC_RNPR   (*(__IO uint32_t*)0x40038110U)

(ADC) Receive Next Pointer Register

Definition at line 91 of file instance_adc.h.

◆ REG_ADC_RPR

#define REG_ADC_RPR   (*(__IO uint32_t*)0x40038100U)

(ADC) Receive Pointer Register

Definition at line 89 of file instance_adc.h.

◆ REG_ADC_SEQR1

#define REG_ADC_SEQR1   (*(__IO uint32_t*)0x40038008U)

(ADC) Channel Sequence Register 1

Definition at line 70 of file instance_adc.h.

◆ REG_ADC_SEQR2

#define REG_ADC_SEQR2   (*(__IO uint32_t*)0x4003800CU)

(ADC) Channel Sequence Register 2

Definition at line 71 of file instance_adc.h.

◆ REG_ADC_WPMR

#define REG_ADC_WPMR   (*(__IO uint32_t*)0x400380E4U)

(ADC) Write Protect Mode Register

Definition at line 87 of file instance_adc.h.

◆ REG_ADC_WPSR

#define REG_ADC_WPSR   (*(__I uint32_t*)0x400380E8U)

(ADC) Write Protect Status Register

Definition at line 88 of file instance_adc.h.