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SAM4SD32 (SAM4S-EK2)
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Copyright (c) 2012-2018 Microchip Technology Inc. More...
Go to the source code of this file.
Macros | |
| #define | REG_PIOB_ABCDSR (*(__IO uint32_t*)0x400E1070U) |
| (PIOB) Peripheral Select Register | |
| #define | REG_PIOB_AIMDR (*(__O uint32_t*)0x400E10B4U) |
| (PIOB) Additional Interrupt Modes Disables Register | |
| #define | REG_PIOB_AIMER (*(__O uint32_t*)0x400E10B0U) |
| (PIOB) Additional Interrupt Modes Enable Register | |
| #define | REG_PIOB_AIMMR (*(__I uint32_t*)0x400E10B8U) |
| (PIOB) Additional Interrupt Modes Mask Register | |
| #define | REG_PIOB_CODR (*(__O uint32_t*)0x400E1034U) |
| (PIOB) Clear Output Data Register | |
| #define | REG_PIOB_ELSR (*(__I uint32_t*)0x400E10C8U) |
| (PIOB) Edge/Level Status Register | |
| #define | REG_PIOB_ESR (*(__O uint32_t*)0x400E10C0U) |
| (PIOB) Edge Select Register | |
| #define | REG_PIOB_FELLSR (*(__O uint32_t*)0x400E10D0U) |
| (PIOB) Falling Edge/Low Level Select Register | |
| #define | REG_PIOB_FRLHSR (*(__I uint32_t*)0x400E10D8U) |
| (PIOB) Fall/Rise - Low/High Status Register | |
| #define | REG_PIOB_IDR (*(__O uint32_t*)0x400E1044U) |
| (PIOB) Interrupt Disable Register | |
| #define | REG_PIOB_IER (*(__O uint32_t*)0x400E1040U) |
| (PIOB) Interrupt Enable Register | |
| #define | REG_PIOB_IFDR (*(__O uint32_t*)0x400E1024U) |
| (PIOB) Glitch Input Filter Disable Register | |
| #define | REG_PIOB_IFER (*(__O uint32_t*)0x400E1020U) |
| (PIOB) Glitch Input Filter Enable Register | |
| #define | REG_PIOB_IFSCDR (*(__O uint32_t*)0x400E1080U) |
| (PIOB) Input Filter Slow Clock Disable Register | |
| #define | REG_PIOB_IFSCER (*(__O uint32_t*)0x400E1084U) |
| (PIOB) Input Filter Slow Clock Enable Register | |
| #define | REG_PIOB_IFSCSR (*(__I uint32_t*)0x400E1088U) |
| (PIOB) Input Filter Slow Clock Status Register | |
| #define | REG_PIOB_IFSR (*(__I uint32_t*)0x400E1028U) |
| (PIOB) Glitch Input Filter Status Register | |
| #define | REG_PIOB_IMR (*(__I uint32_t*)0x400E1048U) |
| (PIOB) Interrupt Mask Register | |
| #define | REG_PIOB_ISR (*(__I uint32_t*)0x400E104CU) |
| (PIOB) Interrupt Status Register | |
| #define | REG_PIOB_LOCKSR (*(__I uint32_t*)0x400E10E0U) |
| (PIOB) Lock Status | |
| #define | REG_PIOB_LSR (*(__O uint32_t*)0x400E10C4U) |
| (PIOB) Level Select Register | |
| #define | REG_PIOB_MDDR (*(__O uint32_t*)0x400E1054U) |
| (PIOB) Multi-driver Disable Register | |
| #define | REG_PIOB_MDER (*(__O uint32_t*)0x400E1050U) |
| (PIOB) Multi-driver Enable Register | |
| #define | REG_PIOB_MDSR (*(__I uint32_t*)0x400E1058U) |
| (PIOB) Multi-driver Status Register | |
| #define | REG_PIOB_ODR (*(__O uint32_t*)0x400E1014U) |
| (PIOB) Output Disable Register | |
| #define | REG_PIOB_ODSR (*(__IO uint32_t*)0x400E1038U) |
| (PIOB) Output Data Status Register | |
| #define | REG_PIOB_OER (*(__O uint32_t*)0x400E1010U) |
| (PIOB) Output Enable Register | |
| #define | REG_PIOB_OSR (*(__I uint32_t*)0x400E1018U) |
| (PIOB) Output Status Register | |
| #define | REG_PIOB_OWDR (*(__O uint32_t*)0x400E10A4U) |
| (PIOB) Output Write Disable | |
| #define | REG_PIOB_OWER (*(__O uint32_t*)0x400E10A0U) |
| (PIOB) Output Write Enable | |
| #define | REG_PIOB_OWSR (*(__I uint32_t*)0x400E10A8U) |
| (PIOB) Output Write Status Register | |
| #define | REG_PIOB_PCIDR (*(__O uint32_t*)0x400E1158U) |
| (PIOB) Parallel Capture Interrupt Disable Register | |
| #define | REG_PIOB_PCIER (*(__O uint32_t*)0x400E1154U) |
| (PIOB) Parallel Capture Interrupt Enable Register | |
| #define | REG_PIOB_PCIMR (*(__I uint32_t*)0x400E115CU) |
| (PIOB) Parallel Capture Interrupt Mask Register | |
| #define | REG_PIOB_PCISR (*(__I uint32_t*)0x400E1160U) |
| (PIOB) Parallel Capture Interrupt Status Register | |
| #define | REG_PIOB_PCMR (*(__IO uint32_t*)0x400E1150U) |
| (PIOB) Parallel Capture Mode Register | |
| #define | REG_PIOB_PCRHR (*(__I uint32_t*)0x400E1164U) |
| (PIOB) Parallel Capture Reception Holding Register | |
| #define | REG_PIOB_PDR (*(__O uint32_t*)0x400E1004U) |
| (PIOB) PIO Disable Register | |
| #define | REG_PIOB_PDSR (*(__I uint32_t*)0x400E103CU) |
| (PIOB) Pin Data Status Register | |
| #define | REG_PIOB_PER (*(__O uint32_t*)0x400E1000U) |
| (PIOB) PIO Enable Register | |
| #define | REG_PIOB_PPDDR (*(__O uint32_t*)0x400E1090U) |
| (PIOB) Pad Pull-down Disable Register | |
| #define | REG_PIOB_PPDER (*(__O uint32_t*)0x400E1094U) |
| (PIOB) Pad Pull-down Enable Register | |
| #define | REG_PIOB_PPDSR (*(__I uint32_t*)0x400E1098U) |
| (PIOB) Pad Pull-down Status Register | |
| #define | REG_PIOB_PSR (*(__I uint32_t*)0x400E1008U) |
| (PIOB) PIO Status Register | |
| #define | REG_PIOB_PUDR (*(__O uint32_t*)0x400E1060U) |
| (PIOB) Pull-up Disable Register | |
| #define | REG_PIOB_PUER (*(__O uint32_t*)0x400E1064U) |
| (PIOB) Pull-up Enable Register | |
| #define | REG_PIOB_PUSR (*(__I uint32_t*)0x400E1068U) |
| (PIOB) Pad Pull-up Status Register | |
| #define | REG_PIOB_REHLSR (*(__O uint32_t*)0x400E10D4U) |
| (PIOB) Rising Edge/ High Level Select Register | |
| #define | REG_PIOB_SCDR (*(__IO uint32_t*)0x400E108CU) |
| (PIOB) Slow Clock Divider Debouncing Register | |
| #define | REG_PIOB_SCHMITT (*(__IO uint32_t*)0x400E1100U) |
| (PIOB) Schmitt Trigger Register | |
| #define | REG_PIOB_SODR (*(__O uint32_t*)0x400E1030U) |
| (PIOB) Set Output Data Register | |
| #define | REG_PIOB_WPMR (*(__IO uint32_t*)0x400E10E4U) |
| (PIOB) Write Protect Mode Register | |
| #define | REG_PIOB_WPSR (*(__I uint32_t*)0x400E10E8U) |
| (PIOB) Write Protect Status Register | |
Copyright (c) 2012-2018 Microchip Technology Inc.
and its subsidiaries.
\cond ASF_LICENSE
Definition in file instance_piob.h.
| #define REG_PIOB_ABCDSR (*(__IO uint32_t*)0x400E1070U) |
(PIOB) Peripheral Select Register
Definition at line 117 of file instance_piob.h.
| #define REG_PIOB_AIMDR (*(__O uint32_t*)0x400E10B4U) |
(PIOB) Additional Interrupt Modes Disables Register
Definition at line 129 of file instance_piob.h.
| #define REG_PIOB_AIMER (*(__O uint32_t*)0x400E10B0U) |
(PIOB) Additional Interrupt Modes Enable Register
Definition at line 128 of file instance_piob.h.
| #define REG_PIOB_AIMMR (*(__I uint32_t*)0x400E10B8U) |
(PIOB) Additional Interrupt Modes Mask Register
Definition at line 130 of file instance_piob.h.
| #define REG_PIOB_CODR (*(__O uint32_t*)0x400E1034U) |
(PIOB) Clear Output Data Register
Definition at line 104 of file instance_piob.h.
| #define REG_PIOB_ELSR (*(__I uint32_t*)0x400E10C8U) |
(PIOB) Edge/Level Status Register
Definition at line 133 of file instance_piob.h.
| #define REG_PIOB_ESR (*(__O uint32_t*)0x400E10C0U) |
(PIOB) Edge Select Register
Definition at line 131 of file instance_piob.h.
| #define REG_PIOB_FELLSR (*(__O uint32_t*)0x400E10D0U) |
(PIOB) Falling Edge/Low Level Select Register
Definition at line 134 of file instance_piob.h.
| #define REG_PIOB_FRLHSR (*(__I uint32_t*)0x400E10D8U) |
(PIOB) Fall/Rise - Low/High Status Register
Definition at line 136 of file instance_piob.h.
| #define REG_PIOB_IDR (*(__O uint32_t*)0x400E1044U) |
(PIOB) Interrupt Disable Register
Definition at line 108 of file instance_piob.h.
| #define REG_PIOB_IER (*(__O uint32_t*)0x400E1040U) |
(PIOB) Interrupt Enable Register
Definition at line 107 of file instance_piob.h.
| #define REG_PIOB_IFDR (*(__O uint32_t*)0x400E1024U) |
(PIOB) Glitch Input Filter Disable Register
Definition at line 101 of file instance_piob.h.
| #define REG_PIOB_IFER (*(__O uint32_t*)0x400E1020U) |
(PIOB) Glitch Input Filter Enable Register
Definition at line 100 of file instance_piob.h.
| #define REG_PIOB_IFSCDR (*(__O uint32_t*)0x400E1080U) |
(PIOB) Input Filter Slow Clock Disable Register
Definition at line 118 of file instance_piob.h.
| #define REG_PIOB_IFSCER (*(__O uint32_t*)0x400E1084U) |
(PIOB) Input Filter Slow Clock Enable Register
Definition at line 119 of file instance_piob.h.
| #define REG_PIOB_IFSCSR (*(__I uint32_t*)0x400E1088U) |
(PIOB) Input Filter Slow Clock Status Register
Definition at line 120 of file instance_piob.h.
| #define REG_PIOB_IFSR (*(__I uint32_t*)0x400E1028U) |
(PIOB) Glitch Input Filter Status Register
Definition at line 102 of file instance_piob.h.
| #define REG_PIOB_IMR (*(__I uint32_t*)0x400E1048U) |
(PIOB) Interrupt Mask Register
Definition at line 109 of file instance_piob.h.
| #define REG_PIOB_ISR (*(__I uint32_t*)0x400E104CU) |
(PIOB) Interrupt Status Register
Definition at line 110 of file instance_piob.h.
| #define REG_PIOB_LOCKSR (*(__I uint32_t*)0x400E10E0U) |
(PIOB) Lock Status
Definition at line 137 of file instance_piob.h.
| #define REG_PIOB_LSR (*(__O uint32_t*)0x400E10C4U) |
(PIOB) Level Select Register
Definition at line 132 of file instance_piob.h.
| #define REG_PIOB_MDDR (*(__O uint32_t*)0x400E1054U) |
(PIOB) Multi-driver Disable Register
Definition at line 112 of file instance_piob.h.
| #define REG_PIOB_MDER (*(__O uint32_t*)0x400E1050U) |
(PIOB) Multi-driver Enable Register
Definition at line 111 of file instance_piob.h.
| #define REG_PIOB_MDSR (*(__I uint32_t*)0x400E1058U) |
(PIOB) Multi-driver Status Register
Definition at line 113 of file instance_piob.h.
| #define REG_PIOB_ODR (*(__O uint32_t*)0x400E1014U) |
(PIOB) Output Disable Register
Definition at line 98 of file instance_piob.h.
| #define REG_PIOB_ODSR (*(__IO uint32_t*)0x400E1038U) |
(PIOB) Output Data Status Register
Definition at line 105 of file instance_piob.h.
| #define REG_PIOB_OER (*(__O uint32_t*)0x400E1010U) |
(PIOB) Output Enable Register
Definition at line 97 of file instance_piob.h.
| #define REG_PIOB_OSR (*(__I uint32_t*)0x400E1018U) |
(PIOB) Output Status Register
Definition at line 99 of file instance_piob.h.
| #define REG_PIOB_OWDR (*(__O uint32_t*)0x400E10A4U) |
(PIOB) Output Write Disable
Definition at line 126 of file instance_piob.h.
| #define REG_PIOB_OWER (*(__O uint32_t*)0x400E10A0U) |
(PIOB) Output Write Enable
Definition at line 125 of file instance_piob.h.
| #define REG_PIOB_OWSR (*(__I uint32_t*)0x400E10A8U) |
(PIOB) Output Write Status Register
Definition at line 127 of file instance_piob.h.
| #define REG_PIOB_PCIDR (*(__O uint32_t*)0x400E1158U) |
(PIOB) Parallel Capture Interrupt Disable Register
Definition at line 143 of file instance_piob.h.
| #define REG_PIOB_PCIER (*(__O uint32_t*)0x400E1154U) |
(PIOB) Parallel Capture Interrupt Enable Register
Definition at line 142 of file instance_piob.h.
| #define REG_PIOB_PCIMR (*(__I uint32_t*)0x400E115CU) |
(PIOB) Parallel Capture Interrupt Mask Register
Definition at line 144 of file instance_piob.h.
| #define REG_PIOB_PCISR (*(__I uint32_t*)0x400E1160U) |
(PIOB) Parallel Capture Interrupt Status Register
Definition at line 145 of file instance_piob.h.
| #define REG_PIOB_PCMR (*(__IO uint32_t*)0x400E1150U) |
(PIOB) Parallel Capture Mode Register
Definition at line 141 of file instance_piob.h.
| #define REG_PIOB_PCRHR (*(__I uint32_t*)0x400E1164U) |
(PIOB) Parallel Capture Reception Holding Register
Definition at line 146 of file instance_piob.h.
| #define REG_PIOB_PDR (*(__O uint32_t*)0x400E1004U) |
(PIOB) PIO Disable Register
Definition at line 95 of file instance_piob.h.
| #define REG_PIOB_PDSR (*(__I uint32_t*)0x400E103CU) |
(PIOB) Pin Data Status Register
Definition at line 106 of file instance_piob.h.
| #define REG_PIOB_PER (*(__O uint32_t*)0x400E1000U) |
(PIOB) PIO Enable Register
Definition at line 94 of file instance_piob.h.
| #define REG_PIOB_PPDDR (*(__O uint32_t*)0x400E1090U) |
(PIOB) Pad Pull-down Disable Register
Definition at line 122 of file instance_piob.h.
| #define REG_PIOB_PPDER (*(__O uint32_t*)0x400E1094U) |
(PIOB) Pad Pull-down Enable Register
Definition at line 123 of file instance_piob.h.
| #define REG_PIOB_PPDSR (*(__I uint32_t*)0x400E1098U) |
(PIOB) Pad Pull-down Status Register
Definition at line 124 of file instance_piob.h.
| #define REG_PIOB_PSR (*(__I uint32_t*)0x400E1008U) |
(PIOB) PIO Status Register
Definition at line 96 of file instance_piob.h.
| #define REG_PIOB_PUDR (*(__O uint32_t*)0x400E1060U) |
(PIOB) Pull-up Disable Register
Definition at line 114 of file instance_piob.h.
| #define REG_PIOB_PUER (*(__O uint32_t*)0x400E1064U) |
(PIOB) Pull-up Enable Register
Definition at line 115 of file instance_piob.h.
| #define REG_PIOB_PUSR (*(__I uint32_t*)0x400E1068U) |
(PIOB) Pad Pull-up Status Register
Definition at line 116 of file instance_piob.h.
| #define REG_PIOB_REHLSR (*(__O uint32_t*)0x400E10D4U) |
(PIOB) Rising Edge/ High Level Select Register
Definition at line 135 of file instance_piob.h.
| #define REG_PIOB_SCDR (*(__IO uint32_t*)0x400E108CU) |
(PIOB) Slow Clock Divider Debouncing Register
Definition at line 121 of file instance_piob.h.
| #define REG_PIOB_SCHMITT (*(__IO uint32_t*)0x400E1100U) |
(PIOB) Schmitt Trigger Register
Definition at line 140 of file instance_piob.h.
| #define REG_PIOB_SODR (*(__O uint32_t*)0x400E1030U) |
(PIOB) Set Output Data Register
Definition at line 103 of file instance_piob.h.
| #define REG_PIOB_WPMR (*(__IO uint32_t*)0x400E10E4U) |
(PIOB) Write Protect Mode Register
Definition at line 138 of file instance_piob.h.
| #define REG_PIOB_WPSR (*(__I uint32_t*)0x400E10E8U) |
(PIOB) Write Protect Status Register
Definition at line 139 of file instance_piob.h.