SAM4SD32 (SAM4S-EK2)
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instance_pwm.h
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1
31/*
32 * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
33 */
34
35#ifndef _SAM4S_PWM_INSTANCE_
36#define _SAM4S_PWM_INSTANCE_
37
38/* ========== Register definition for PWM peripheral ========== */
39#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
40 #define REG_PWM_CLK (0x40020000U)
41 #define REG_PWM_ENA (0x40020004U)
42 #define REG_PWM_DIS (0x40020008U)
43 #define REG_PWM_SR (0x4002000CU)
44 #define REG_PWM_IER1 (0x40020010U)
45 #define REG_PWM_IDR1 (0x40020014U)
46 #define REG_PWM_IMR1 (0x40020018U)
47 #define REG_PWM_ISR1 (0x4002001CU)
48 #define REG_PWM_SCM (0x40020020U)
49 #define REG_PWM_SCUC (0x40020028U)
50 #define REG_PWM_SCUP (0x4002002CU)
51 #define REG_PWM_SCUPUPD (0x40020030U)
52 #define REG_PWM_IER2 (0x40020034U)
53 #define REG_PWM_IDR2 (0x40020038U)
54 #define REG_PWM_IMR2 (0x4002003CU)
55 #define REG_PWM_ISR2 (0x40020040U)
56 #define REG_PWM_OOV (0x40020044U)
57 #define REG_PWM_OS (0x40020048U)
58 #define REG_PWM_OSS (0x4002004CU)
59 #define REG_PWM_OSC (0x40020050U)
60 #define REG_PWM_OSSUPD (0x40020054U)
61 #define REG_PWM_OSCUPD (0x40020058U)
62 #define REG_PWM_FMR (0x4002005CU)
63 #define REG_PWM_FSR (0x40020060U)
64 #define REG_PWM_FCR (0x40020064U)
65 #define REG_PWM_FPV (0x40020068U)
66 #define REG_PWM_FPE (0x4002006CU)
67 #define REG_PWM_ELMR (0x4002007CU)
68 #define REG_PWM_SMMR (0x400200B0U)
69 #define REG_PWM_WPCR (0x400200E4U)
70 #define REG_PWM_WPSR (0x400200E8U)
71 #define REG_PWM_TPR (0x40020108U)
72 #define REG_PWM_TCR (0x4002010CU)
73 #define REG_PWM_TNPR (0x40020118U)
74 #define REG_PWM_TNCR (0x4002011CU)
75 #define REG_PWM_PTCR (0x40020120U)
76 #define REG_PWM_PTSR (0x40020124U)
77 #define REG_PWM_CMPV0 (0x40020130U)
78 #define REG_PWM_CMPVUPD0 (0x40020134U)
79 #define REG_PWM_CMPM0 (0x40020138U)
80 #define REG_PWM_CMPMUPD0 (0x4002013CU)
81 #define REG_PWM_CMPV1 (0x40020140U)
82 #define REG_PWM_CMPVUPD1 (0x40020144U)
83 #define REG_PWM_CMPM1 (0x40020148U)
84 #define REG_PWM_CMPMUPD1 (0x4002014CU)
85 #define REG_PWM_CMPV2 (0x40020150U)
86 #define REG_PWM_CMPVUPD2 (0x40020154U)
87 #define REG_PWM_CMPM2 (0x40020158U)
88 #define REG_PWM_CMPMUPD2 (0x4002015CU)
89 #define REG_PWM_CMPV3 (0x40020160U)
90 #define REG_PWM_CMPVUPD3 (0x40020164U)
91 #define REG_PWM_CMPM3 (0x40020168U)
92 #define REG_PWM_CMPMUPD3 (0x4002016CU)
93 #define REG_PWM_CMPV4 (0x40020170U)
94 #define REG_PWM_CMPVUPD4 (0x40020174U)
95 #define REG_PWM_CMPM4 (0x40020178U)
96 #define REG_PWM_CMPMUPD4 (0x4002017CU)
97 #define REG_PWM_CMPV5 (0x40020180U)
98 #define REG_PWM_CMPVUPD5 (0x40020184U)
99 #define REG_PWM_CMPM5 (0x40020188U)
100 #define REG_PWM_CMPMUPD5 (0x4002018CU)
101 #define REG_PWM_CMPV6 (0x40020190U)
102 #define REG_PWM_CMPVUPD6 (0x40020194U)
103 #define REG_PWM_CMPM6 (0x40020198U)
104 #define REG_PWM_CMPMUPD6 (0x4002019CU)
105 #define REG_PWM_CMPV7 (0x400201A0U)
106 #define REG_PWM_CMPVUPD7 (0x400201A4U)
107 #define REG_PWM_CMPM7 (0x400201A8U)
108 #define REG_PWM_CMPMUPD7 (0x400201ACU)
109 #define REG_PWM_CMR0 (0x40020200U)
110 #define REG_PWM_CDTY0 (0x40020204U)
111 #define REG_PWM_CDTYUPD0 (0x40020208U)
112 #define REG_PWM_CPRD0 (0x4002020CU)
113 #define REG_PWM_CPRDUPD0 (0x40020210U)
114 #define REG_PWM_CCNT0 (0x40020214U)
115 #define REG_PWM_DT0 (0x40020218U)
116 #define REG_PWM_DTUPD0 (0x4002021CU)
117 #define REG_PWM_CMR1 (0x40020220U)
118 #define REG_PWM_CDTY1 (0x40020224U)
119 #define REG_PWM_CDTYUPD1 (0x40020228U)
120 #define REG_PWM_CPRD1 (0x4002022CU)
121 #define REG_PWM_CPRDUPD1 (0x40020230U)
122 #define REG_PWM_CCNT1 (0x40020234U)
123 #define REG_PWM_DT1 (0x40020238U)
124 #define REG_PWM_DTUPD1 (0x4002023CU)
125 #define REG_PWM_CMR2 (0x40020240U)
126 #define REG_PWM_CDTY2 (0x40020244U)
127 #define REG_PWM_CDTYUPD2 (0x40020248U)
128 #define REG_PWM_CPRD2 (0x4002024CU)
129 #define REG_PWM_CPRDUPD2 (0x40020250U)
130 #define REG_PWM_CCNT2 (0x40020254U)
131 #define REG_PWM_DT2 (0x40020258U)
132 #define REG_PWM_DTUPD2 (0x4002025CU)
133 #define REG_PWM_CMR3 (0x40020260U)
134 #define REG_PWM_CDTY3 (0x40020264U)
135 #define REG_PWM_CDTYUPD3 (0x40020268U)
136 #define REG_PWM_CPRD3 (0x4002026CU)
137 #define REG_PWM_CPRDUPD3 (0x40020270U)
138 #define REG_PWM_CCNT3 (0x40020274U)
139 #define REG_PWM_DT3 (0x40020278U)
140 #define REG_PWM_DTUPD3 (0x4002027CU)
141#else
142 #define REG_PWM_CLK (*(__IO uint32_t*)0x40020000U)
143 #define REG_PWM_ENA (*(__O uint32_t*)0x40020004U)
144 #define REG_PWM_DIS (*(__O uint32_t*)0x40020008U)
145 #define REG_PWM_SR (*(__I uint32_t*)0x4002000CU)
146 #define REG_PWM_IER1 (*(__O uint32_t*)0x40020010U)
147 #define REG_PWM_IDR1 (*(__O uint32_t*)0x40020014U)
148 #define REG_PWM_IMR1 (*(__I uint32_t*)0x40020018U)
149 #define REG_PWM_ISR1 (*(__I uint32_t*)0x4002001CU)
150 #define REG_PWM_SCM (*(__IO uint32_t*)0x40020020U)
151 #define REG_PWM_SCUC (*(__IO uint32_t*)0x40020028U)
152 #define REG_PWM_SCUP (*(__IO uint32_t*)0x4002002CU)
153 #define REG_PWM_SCUPUPD (*(__O uint32_t*)0x40020030U)
154 #define REG_PWM_IER2 (*(__O uint32_t*)0x40020034U)
155 #define REG_PWM_IDR2 (*(__O uint32_t*)0x40020038U)
156 #define REG_PWM_IMR2 (*(__I uint32_t*)0x4002003CU)
157 #define REG_PWM_ISR2 (*(__I uint32_t*)0x40020040U)
158 #define REG_PWM_OOV (*(__IO uint32_t*)0x40020044U)
159 #define REG_PWM_OS (*(__IO uint32_t*)0x40020048U)
160 #define REG_PWM_OSS (*(__O uint32_t*)0x4002004CU)
161 #define REG_PWM_OSC (*(__O uint32_t*)0x40020050U)
162 #define REG_PWM_OSSUPD (*(__O uint32_t*)0x40020054U)
163 #define REG_PWM_OSCUPD (*(__O uint32_t*)0x40020058U)
164 #define REG_PWM_FMR (*(__IO uint32_t*)0x4002005CU)
165 #define REG_PWM_FSR (*(__I uint32_t*)0x40020060U)
166 #define REG_PWM_FCR (*(__O uint32_t*)0x40020064U)
167 #define REG_PWM_FPV (*(__IO uint32_t*)0x40020068U)
168 #define REG_PWM_FPE (*(__IO uint32_t*)0x4002006CU)
169 #define REG_PWM_ELMR (*(__IO uint32_t*)0x4002007CU)
170 #define REG_PWM_SMMR (*(__IO uint32_t*)0x400200B0U)
171 #define REG_PWM_WPCR (*(__O uint32_t*)0x400200E4U)
172 #define REG_PWM_WPSR (*(__I uint32_t*)0x400200E8U)
173 #define REG_PWM_TPR (*(__IO uint32_t*)0x40020108U)
174 #define REG_PWM_TCR (*(__IO uint32_t*)0x4002010CU)
175 #define REG_PWM_TNPR (*(__IO uint32_t*)0x40020118U)
176 #define REG_PWM_TNCR (*(__IO uint32_t*)0x4002011CU)
177 #define REG_PWM_PTCR (*(__O uint32_t*)0x40020120U)
178 #define REG_PWM_PTSR (*(__I uint32_t*)0x40020124U)
179 #define REG_PWM_CMPV0 (*(__IO uint32_t*)0x40020130U)
180 #define REG_PWM_CMPVUPD0 (*(__O uint32_t*)0x40020134U)
181 #define REG_PWM_CMPM0 (*(__IO uint32_t*)0x40020138U)
182 #define REG_PWM_CMPMUPD0 (*(__O uint32_t*)0x4002013CU)
183 #define REG_PWM_CMPV1 (*(__IO uint32_t*)0x40020140U)
184 #define REG_PWM_CMPVUPD1 (*(__O uint32_t*)0x40020144U)
185 #define REG_PWM_CMPM1 (*(__IO uint32_t*)0x40020148U)
186 #define REG_PWM_CMPMUPD1 (*(__O uint32_t*)0x4002014CU)
187 #define REG_PWM_CMPV2 (*(__IO uint32_t*)0x40020150U)
188 #define REG_PWM_CMPVUPD2 (*(__O uint32_t*)0x40020154U)
189 #define REG_PWM_CMPM2 (*(__IO uint32_t*)0x40020158U)
190 #define REG_PWM_CMPMUPD2 (*(__O uint32_t*)0x4002015CU)
191 #define REG_PWM_CMPV3 (*(__IO uint32_t*)0x40020160U)
192 #define REG_PWM_CMPVUPD3 (*(__O uint32_t*)0x40020164U)
193 #define REG_PWM_CMPM3 (*(__IO uint32_t*)0x40020168U)
194 #define REG_PWM_CMPMUPD3 (*(__O uint32_t*)0x4002016CU)
195 #define REG_PWM_CMPV4 (*(__IO uint32_t*)0x40020170U)
196 #define REG_PWM_CMPVUPD4 (*(__O uint32_t*)0x40020174U)
197 #define REG_PWM_CMPM4 (*(__IO uint32_t*)0x40020178U)
198 #define REG_PWM_CMPMUPD4 (*(__O uint32_t*)0x4002017CU)
199 #define REG_PWM_CMPV5 (*(__IO uint32_t*)0x40020180U)
200 #define REG_PWM_CMPVUPD5 (*(__O uint32_t*)0x40020184U)
201 #define REG_PWM_CMPM5 (*(__IO uint32_t*)0x40020188U)
202 #define REG_PWM_CMPMUPD5 (*(__O uint32_t*)0x4002018CU)
203 #define REG_PWM_CMPV6 (*(__IO uint32_t*)0x40020190U)
204 #define REG_PWM_CMPVUPD6 (*(__O uint32_t*)0x40020194U)
205 #define REG_PWM_CMPM6 (*(__IO uint32_t*)0x40020198U)
206 #define REG_PWM_CMPMUPD6 (*(__O uint32_t*)0x4002019CU)
207 #define REG_PWM_CMPV7 (*(__IO uint32_t*)0x400201A0U)
208 #define REG_PWM_CMPVUPD7 (*(__O uint32_t*)0x400201A4U)
209 #define REG_PWM_CMPM7 (*(__IO uint32_t*)0x400201A8U)
210 #define REG_PWM_CMPMUPD7 (*(__O uint32_t*)0x400201ACU)
211 #define REG_PWM_CMR0 (*(__IO uint32_t*)0x40020200U)
212 #define REG_PWM_CDTY0 (*(__IO uint32_t*)0x40020204U)
213 #define REG_PWM_CDTYUPD0 (*(__O uint32_t*)0x40020208U)
214 #define REG_PWM_CPRD0 (*(__IO uint32_t*)0x4002020CU)
215 #define REG_PWM_CPRDUPD0 (*(__O uint32_t*)0x40020210U)
216 #define REG_PWM_CCNT0 (*(__I uint32_t*)0x40020214U)
217 #define REG_PWM_DT0 (*(__IO uint32_t*)0x40020218U)
218 #define REG_PWM_DTUPD0 (*(__O uint32_t*)0x4002021CU)
219 #define REG_PWM_CMR1 (*(__IO uint32_t*)0x40020220U)
220 #define REG_PWM_CDTY1 (*(__IO uint32_t*)0x40020224U)
221 #define REG_PWM_CDTYUPD1 (*(__O uint32_t*)0x40020228U)
222 #define REG_PWM_CPRD1 (*(__IO uint32_t*)0x4002022CU)
223 #define REG_PWM_CPRDUPD1 (*(__O uint32_t*)0x40020230U)
224 #define REG_PWM_CCNT1 (*(__I uint32_t*)0x40020234U)
225 #define REG_PWM_DT1 (*(__IO uint32_t*)0x40020238U)
226 #define REG_PWM_DTUPD1 (*(__O uint32_t*)0x4002023CU)
227 #define REG_PWM_CMR2 (*(__IO uint32_t*)0x40020240U)
228 #define REG_PWM_CDTY2 (*(__IO uint32_t*)0x40020244U)
229 #define REG_PWM_CDTYUPD2 (*(__O uint32_t*)0x40020248U)
230 #define REG_PWM_CPRD2 (*(__IO uint32_t*)0x4002024CU)
231 #define REG_PWM_CPRDUPD2 (*(__O uint32_t*)0x40020250U)
232 #define REG_PWM_CCNT2 (*(__I uint32_t*)0x40020254U)
233 #define REG_PWM_DT2 (*(__IO uint32_t*)0x40020258U)
234 #define REG_PWM_DTUPD2 (*(__O uint32_t*)0x4002025CU)
235 #define REG_PWM_CMR3 (*(__IO uint32_t*)0x40020260U)
236 #define REG_PWM_CDTY3 (*(__IO uint32_t*)0x40020264U)
237 #define REG_PWM_CDTYUPD3 (*(__O uint32_t*)0x40020268U)
238 #define REG_PWM_CPRD3 (*(__IO uint32_t*)0x4002026CU)
239 #define REG_PWM_CPRDUPD3 (*(__O uint32_t*)0x40020270U)
240 #define REG_PWM_CCNT3 (*(__I uint32_t*)0x40020274U)
241 #define REG_PWM_DT3 (*(__IO uint32_t*)0x40020278U)
242 #define REG_PWM_DTUPD3 (*(__O uint32_t*)0x4002027CU)
243#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
244
245#endif /* _SAM4S_PWM_INSTANCE_ */