Macros
#define	REG_PWM_CCNT0 ((__I uint32_t)0x40020214U)
	(PWM) PWM Channel Counter Register (ch_num = 0)
#define	REG_PWM_CCNT1 ((__I uint32_t)0x40020234U)
	(PWM) PWM Channel Counter Register (ch_num = 1)
#define	REG_PWM_CCNT2 ((__I uint32_t)0x40020254U)
	(PWM) PWM Channel Counter Register (ch_num = 2)
#define	REG_PWM_CCNT3 ((__I uint32_t)0x40020274U)
	(PWM) PWM Channel Counter Register (ch_num = 3)
#define	REG_PWM_CDTY0 ((__IO uint32_t)0x40020204U)
	(PWM) PWM Channel Duty Cycle Register (ch_num = 0)
#define	REG_PWM_CDTY1 ((__IO uint32_t)0x40020224U)
	(PWM) PWM Channel Duty Cycle Register (ch_num = 1)
#define	REG_PWM_CDTY2 ((__IO uint32_t)0x40020244U)
	(PWM) PWM Channel Duty Cycle Register (ch_num = 2)
#define	REG_PWM_CDTY3 ((__IO uint32_t)0x40020264U)
	(PWM) PWM Channel Duty Cycle Register (ch_num = 3)
#define	REG_PWM_CDTYUPD0 ((__O uint32_t)0x40020208U)
	(PWM) PWM Channel Duty Cycle Update Register (ch_num = 0)
#define	REG_PWM_CDTYUPD1 ((__O uint32_t)0x40020228U)
	(PWM) PWM Channel Duty Cycle Update Register (ch_num = 1)
#define	REG_PWM_CDTYUPD2 ((__O uint32_t)0x40020248U)
	(PWM) PWM Channel Duty Cycle Update Register (ch_num = 2)
#define	REG_PWM_CDTYUPD3 ((__O uint32_t)0x40020268U)
	(PWM) PWM Channel Duty Cycle Update Register (ch_num = 3)
#define	REG_PWM_CLK ((__IO uint32_t)0x40020000U)
	(PWM) PWM Clock Register
#define	REG_PWM_CMPM0 ((__IO uint32_t)0x40020138U)
	(PWM) PWM Comparison 0 Mode Register
#define	REG_PWM_CMPM1 ((__IO uint32_t)0x40020148U)
	(PWM) PWM Comparison 1 Mode Register
#define	REG_PWM_CMPM2 ((__IO uint32_t)0x40020158U)
	(PWM) PWM Comparison 2 Mode Register
#define	REG_PWM_CMPM3 ((__IO uint32_t)0x40020168U)
	(PWM) PWM Comparison 3 Mode Register
#define	REG_PWM_CMPM4 ((__IO uint32_t)0x40020178U)
	(PWM) PWM Comparison 4 Mode Register
#define	REG_PWM_CMPM5 ((__IO uint32_t)0x40020188U)
	(PWM) PWM Comparison 5 Mode Register
#define	REG_PWM_CMPM6 ((__IO uint32_t)0x40020198U)
	(PWM) PWM Comparison 6 Mode Register
#define	REG_PWM_CMPM7 ((__IO uint32_t)0x400201A8U)
	(PWM) PWM Comparison 7 Mode Register
#define	REG_PWM_CMPMUPD0 ((__O uint32_t)0x4002013CU)
	(PWM) PWM Comparison 0 Mode Update Register
#define	REG_PWM_CMPMUPD1 ((__O uint32_t)0x4002014CU)
	(PWM) PWM Comparison 1 Mode Update Register
#define	REG_PWM_CMPMUPD2 ((__O uint32_t)0x4002015CU)
	(PWM) PWM Comparison 2 Mode Update Register
#define	REG_PWM_CMPMUPD3 ((__O uint32_t)0x4002016CU)
	(PWM) PWM Comparison 3 Mode Update Register
#define	REG_PWM_CMPMUPD4 ((__O uint32_t)0x4002017CU)
	(PWM) PWM Comparison 4 Mode Update Register
#define	REG_PWM_CMPMUPD5 ((__O uint32_t)0x4002018CU)
	(PWM) PWM Comparison 5 Mode Update Register
#define	REG_PWM_CMPMUPD6 ((__O uint32_t)0x4002019CU)
	(PWM) PWM Comparison 6 Mode Update Register
#define	REG_PWM_CMPMUPD7 ((__O uint32_t)0x400201ACU)
	(PWM) PWM Comparison 7 Mode Update Register
#define	REG_PWM_CMPV0 ((__IO uint32_t)0x40020130U)
	(PWM) PWM Comparison 0 Value Register
#define	REG_PWM_CMPV1 ((__IO uint32_t)0x40020140U)
	(PWM) PWM Comparison 1 Value Register
#define	REG_PWM_CMPV2 ((__IO uint32_t)0x40020150U)
	(PWM) PWM Comparison 2 Value Register
#define	REG_PWM_CMPV3 ((__IO uint32_t)0x40020160U)
	(PWM) PWM Comparison 3 Value Register
#define	REG_PWM_CMPV4 ((__IO uint32_t)0x40020170U)
	(PWM) PWM Comparison 4 Value Register
#define	REG_PWM_CMPV5 ((__IO uint32_t)0x40020180U)
	(PWM) PWM Comparison 5 Value Register
#define	REG_PWM_CMPV6 ((__IO uint32_t)0x40020190U)
	(PWM) PWM Comparison 6 Value Register
#define	REG_PWM_CMPV7 ((__IO uint32_t)0x400201A0U)
	(PWM) PWM Comparison 7 Value Register
#define	REG_PWM_CMPVUPD0 ((__O uint32_t)0x40020134U)
	(PWM) PWM Comparison 0 Value Update Register
#define	REG_PWM_CMPVUPD1 ((__O uint32_t)0x40020144U)
	(PWM) PWM Comparison 1 Value Update Register
#define	REG_PWM_CMPVUPD2 ((__O uint32_t)0x40020154U)
	(PWM) PWM Comparison 2 Value Update Register
#define	REG_PWM_CMPVUPD3 ((__O uint32_t)0x40020164U)
	(PWM) PWM Comparison 3 Value Update Register
#define	REG_PWM_CMPVUPD4 ((__O uint32_t)0x40020174U)
	(PWM) PWM Comparison 4 Value Update Register
#define	REG_PWM_CMPVUPD5 ((__O uint32_t)0x40020184U)
	(PWM) PWM Comparison 5 Value Update Register
#define	REG_PWM_CMPVUPD6 ((__O uint32_t)0x40020194U)
	(PWM) PWM Comparison 6 Value Update Register
#define	REG_PWM_CMPVUPD7 ((__O uint32_t)0x400201A4U)
	(PWM) PWM Comparison 7 Value Update Register
#define	REG_PWM_CMR0 ((__IO uint32_t)0x40020200U)
	(PWM) PWM Channel Mode Register (ch_num = 0)
#define	REG_PWM_CMR1 ((__IO uint32_t)0x40020220U)
	(PWM) PWM Channel Mode Register (ch_num = 1)
#define	REG_PWM_CMR2 ((__IO uint32_t)0x40020240U)
	(PWM) PWM Channel Mode Register (ch_num = 2)
#define	REG_PWM_CMR3 ((__IO uint32_t)0x40020260U)
	(PWM) PWM Channel Mode Register (ch_num = 3)
#define	REG_PWM_CPRD0 ((__IO uint32_t)0x4002020CU)
	(PWM) PWM Channel Period Register (ch_num = 0)
#define	REG_PWM_CPRD1 ((__IO uint32_t)0x4002022CU)
	(PWM) PWM Channel Period Register (ch_num = 1)
#define	REG_PWM_CPRD2 ((__IO uint32_t)0x4002024CU)
	(PWM) PWM Channel Period Register (ch_num = 2)
#define	REG_PWM_CPRD3 ((__IO uint32_t)0x4002026CU)
	(PWM) PWM Channel Period Register (ch_num = 3)
#define	REG_PWM_CPRDUPD0 ((__O uint32_t)0x40020210U)
	(PWM) PWM Channel Period Update Register (ch_num = 0)
#define	REG_PWM_CPRDUPD1 ((__O uint32_t)0x40020230U)
	(PWM) PWM Channel Period Update Register (ch_num = 1)
#define	REG_PWM_CPRDUPD2 ((__O uint32_t)0x40020250U)
	(PWM) PWM Channel Period Update Register (ch_num = 2)
#define	REG_PWM_CPRDUPD3 ((__O uint32_t)0x40020270U)
	(PWM) PWM Channel Period Update Register (ch_num = 3)
#define	REG_PWM_DIS ((__O uint32_t)0x40020008U)
	(PWM) PWM Disable Register
#define	REG_PWM_DT0 ((__IO uint32_t)0x40020218U)
	(PWM) PWM Channel Dead Time Register (ch_num = 0)
#define	REG_PWM_DT1 ((__IO uint32_t)0x40020238U)
	(PWM) PWM Channel Dead Time Register (ch_num = 1)
#define	REG_PWM_DT2 ((__IO uint32_t)0x40020258U)
	(PWM) PWM Channel Dead Time Register (ch_num = 2)
#define	REG_PWM_DT3 ((__IO uint32_t)0x40020278U)
	(PWM) PWM Channel Dead Time Register (ch_num = 3)
#define	REG_PWM_DTUPD0 ((__O uint32_t)0x4002021CU)
	(PWM) PWM Channel Dead Time Update Register (ch_num = 0)
#define	REG_PWM_DTUPD1 ((__O uint32_t)0x4002023CU)
	(PWM) PWM Channel Dead Time Update Register (ch_num = 1)
#define	REG_PWM_DTUPD2 ((__O uint32_t)0x4002025CU)
	(PWM) PWM Channel Dead Time Update Register (ch_num = 2)
#define	REG_PWM_DTUPD3 ((__O uint32_t)0x4002027CU)
	(PWM) PWM Channel Dead Time Update Register (ch_num = 3)
#define	REG_PWM_ELMR ((__IO uint32_t)0x4002007CU)
	(PWM) PWM Event Line 0 Mode Register
#define	REG_PWM_ENA ((__O uint32_t)0x40020004U)
	(PWM) PWM Enable Register
#define	REG_PWM_FCR ((__O uint32_t)0x40020064U)
	(PWM) PWM Fault Clear Register
#define	REG_PWM_FMR ((__IO uint32_t)0x4002005CU)
	(PWM) PWM Fault Mode Register
#define	REG_PWM_FPE ((__IO uint32_t)0x4002006CU)
	(PWM) PWM Fault Protection Enable Register
#define	REG_PWM_FPV ((__IO uint32_t)0x40020068U)
	(PWM) PWM Fault Protection Value Register
#define	REG_PWM_FSR ((__I uint32_t)0x40020060U)
	(PWM) PWM Fault Status Register
#define	REG_PWM_IDR1 ((__O uint32_t)0x40020014U)
	(PWM) PWM Interrupt Disable Register 1
#define	REG_PWM_IDR2 ((__O uint32_t)0x40020038U)
	(PWM) PWM Interrupt Disable Register 2
#define	REG_PWM_IER1 ((__O uint32_t)0x40020010U)
	(PWM) PWM Interrupt Enable Register 1
#define	REG_PWM_IER2 ((__O uint32_t)0x40020034U)
	(PWM) PWM Interrupt Enable Register 2
#define	REG_PWM_IMR1 ((__I uint32_t)0x40020018U)
	(PWM) PWM Interrupt Mask Register 1
#define	REG_PWM_IMR2 ((__I uint32_t)0x4002003CU)
	(PWM) PWM Interrupt Mask Register 2
#define	REG_PWM_ISR1 ((__I uint32_t)0x4002001CU)
	(PWM) PWM Interrupt Status Register 1
#define	REG_PWM_ISR2 ((__I uint32_t)0x40020040U)
	(PWM) PWM Interrupt Status Register 2
#define	REG_PWM_OOV ((__IO uint32_t)0x40020044U)
	(PWM) PWM Output Override Value Register
#define	REG_PWM_OS ((__IO uint32_t)0x40020048U)
	(PWM) PWM Output Selection Register
#define	REG_PWM_OSC ((__O uint32_t)0x40020050U)
	(PWM) PWM Output Selection Clear Register
#define	REG_PWM_OSCUPD ((__O uint32_t)0x40020058U)
	(PWM) PWM Output Selection Clear Update Register
#define	REG_PWM_OSS ((__O uint32_t)0x4002004CU)
	(PWM) PWM Output Selection Set Register
#define	REG_PWM_OSSUPD ((__O uint32_t)0x40020054U)
	(PWM) PWM Output Selection Set Update Register
#define	REG_PWM_PTCR ((__O uint32_t)0x40020120U)
	(PWM) Transfer Control Register
#define	REG_PWM_PTSR ((__I uint32_t)0x40020124U)
	(PWM) Transfer Status Register
#define	REG_PWM_SCM ((__IO uint32_t)0x40020020U)
	(PWM) PWM Sync Channels Mode Register
#define	REG_PWM_SCUC ((__IO uint32_t)0x40020028U)
	(PWM) PWM Sync Channels Update Control Register
#define	REG_PWM_SCUP ((__IO uint32_t)0x4002002CU)
	(PWM) PWM Sync Channels Update Period Register
#define	REG_PWM_SCUPUPD ((__O uint32_t)0x40020030U)
	(PWM) PWM Sync Channels Update Period Update Register
#define	REG_PWM_SMMR ((__IO uint32_t)0x400200B0U)
	(PWM) PWM Stepper Motor Mode Register
#define	REG_PWM_SR ((__I uint32_t)0x4002000CU)
	(PWM) PWM Status Register
#define	REG_PWM_TCR ((__IO uint32_t)0x4002010CU)
	(PWM) Transmit Counter Register
#define	REG_PWM_TNCR ((__IO uint32_t)0x4002011CU)
	(PWM) Transmit Next Counter Register
#define	REG_PWM_TNPR ((__IO uint32_t)0x40020118U)
	(PWM) Transmit Next Pointer Register
#define	REG_PWM_TPR ((__IO uint32_t)0x40020108U)
	(PWM) Transmit Pointer Register
#define	REG_PWM_WPCR ((__O uint32_t)0x400200E4U)
	(PWM) PWM Write Protection Control Register
#define	REG_PWM_WPSR ((__I uint32_t)0x400200E8U)
	(PWM) PWM Write Protection Status Register

Detailed Description

and its subsidiaries.

\cond ASF_LICENSE

Definition in file instance_pwm.h.

Macro Definition Documentation

◆ REG_PWM_CCNT0

#define REG_PWM_CCNT0 (*(__I uint32_t*)0x40020214U)

(PWM) PWM Channel Counter Register (ch_num = 0)

Definition at line 216 of file instance_pwm.h.

◆ REG_PWM_CCNT1

#define REG_PWM_CCNT1 (*(__I uint32_t*)0x40020234U)

(PWM) PWM Channel Counter Register (ch_num = 1)

Definition at line 224 of file instance_pwm.h.

◆ REG_PWM_CCNT2

#define REG_PWM_CCNT2 (*(__I uint32_t*)0x40020254U)

(PWM) PWM Channel Counter Register (ch_num = 2)

Definition at line 232 of file instance_pwm.h.

◆ REG_PWM_CCNT3

#define REG_PWM_CCNT3 (*(__I uint32_t*)0x40020274U)

(PWM) PWM Channel Counter Register (ch_num = 3)

Definition at line 240 of file instance_pwm.h.

◆ REG_PWM_CDTY0

#define REG_PWM_CDTY0 (*(__IO uint32_t*)0x40020204U)

(PWM) PWM Channel Duty Cycle Register (ch_num = 0)

Definition at line 212 of file instance_pwm.h.

◆ REG_PWM_CDTY1

#define REG_PWM_CDTY1 (*(__IO uint32_t*)0x40020224U)

(PWM) PWM Channel Duty Cycle Register (ch_num = 1)

Definition at line 220 of file instance_pwm.h.

◆ REG_PWM_CDTY2

#define REG_PWM_CDTY2 (*(__IO uint32_t*)0x40020244U)

(PWM) PWM Channel Duty Cycle Register (ch_num = 2)

Definition at line 228 of file instance_pwm.h.

◆ REG_PWM_CDTY3

#define REG_PWM_CDTY3 (*(__IO uint32_t*)0x40020264U)

(PWM) PWM Channel Duty Cycle Register (ch_num = 3)

Definition at line 236 of file instance_pwm.h.

◆ REG_PWM_CDTYUPD0

#define REG_PWM_CDTYUPD0 (*(__O uint32_t*)0x40020208U)

(PWM) PWM Channel Duty Cycle Update Register (ch_num = 0)

Definition at line 213 of file instance_pwm.h.

◆ REG_PWM_CDTYUPD1

#define REG_PWM_CDTYUPD1 (*(__O uint32_t*)0x40020228U)

(PWM) PWM Channel Duty Cycle Update Register (ch_num = 1)

Definition at line 221 of file instance_pwm.h.

◆ REG_PWM_CDTYUPD2

#define REG_PWM_CDTYUPD2 (*(__O uint32_t*)0x40020248U)

(PWM) PWM Channel Duty Cycle Update Register (ch_num = 2)

Definition at line 229 of file instance_pwm.h.

◆ REG_PWM_CDTYUPD3

#define REG_PWM_CDTYUPD3 (*(__O uint32_t*)0x40020268U)

(PWM) PWM Channel Duty Cycle Update Register (ch_num = 3)

Definition at line 237 of file instance_pwm.h.

◆ REG_PWM_CLK

#define REG_PWM_CLK (*(__IO uint32_t*)0x40020000U)

(PWM) PWM Clock Register

Definition at line 142 of file instance_pwm.h.

◆ REG_PWM_CMPM0

#define REG_PWM_CMPM0 (*(__IO uint32_t*)0x40020138U)

(PWM) PWM Comparison 0 Mode Register

Definition at line 181 of file instance_pwm.h.

◆ REG_PWM_CMPM1

#define REG_PWM_CMPM1 (*(__IO uint32_t*)0x40020148U)

(PWM) PWM Comparison 1 Mode Register

Definition at line 185 of file instance_pwm.h.

◆ REG_PWM_CMPM2

#define REG_PWM_CMPM2 (*(__IO uint32_t*)0x40020158U)

(PWM) PWM Comparison 2 Mode Register

Definition at line 189 of file instance_pwm.h.

◆ REG_PWM_CMPM3

#define REG_PWM_CMPM3 (*(__IO uint32_t*)0x40020168U)

(PWM) PWM Comparison 3 Mode Register

Definition at line 193 of file instance_pwm.h.

◆ REG_PWM_CMPM4

#define REG_PWM_CMPM4 (*(__IO uint32_t*)0x40020178U)

(PWM) PWM Comparison 4 Mode Register

Definition at line 197 of file instance_pwm.h.

◆ REG_PWM_CMPM5

#define REG_PWM_CMPM5 (*(__IO uint32_t*)0x40020188U)

(PWM) PWM Comparison 5 Mode Register

Definition at line 201 of file instance_pwm.h.

◆ REG_PWM_CMPM6

#define REG_PWM_CMPM6 (*(__IO uint32_t*)0x40020198U)

(PWM) PWM Comparison 6 Mode Register

Definition at line 205 of file instance_pwm.h.

◆ REG_PWM_CMPM7

#define REG_PWM_CMPM7 (*(__IO uint32_t*)0x400201A8U)

(PWM) PWM Comparison 7 Mode Register

Definition at line 209 of file instance_pwm.h.

◆ REG_PWM_CMPMUPD0

#define REG_PWM_CMPMUPD0 (*(__O uint32_t*)0x4002013CU)

(PWM) PWM Comparison 0 Mode Update Register

Definition at line 182 of file instance_pwm.h.

◆ REG_PWM_CMPMUPD1

#define REG_PWM_CMPMUPD1 (*(__O uint32_t*)0x4002014CU)

(PWM) PWM Comparison 1 Mode Update Register

Definition at line 186 of file instance_pwm.h.

◆ REG_PWM_CMPMUPD2

#define REG_PWM_CMPMUPD2 (*(__O uint32_t*)0x4002015CU)

(PWM) PWM Comparison 2 Mode Update Register

Definition at line 190 of file instance_pwm.h.

◆ REG_PWM_CMPMUPD3

#define REG_PWM_CMPMUPD3 (*(__O uint32_t*)0x4002016CU)

(PWM) PWM Comparison 3 Mode Update Register

Definition at line 194 of file instance_pwm.h.

◆ REG_PWM_CMPMUPD4

#define REG_PWM_CMPMUPD4 (*(__O uint32_t*)0x4002017CU)

(PWM) PWM Comparison 4 Mode Update Register

Definition at line 198 of file instance_pwm.h.

◆ REG_PWM_CMPMUPD5

#define REG_PWM_CMPMUPD5 (*(__O uint32_t*)0x4002018CU)

(PWM) PWM Comparison 5 Mode Update Register

Definition at line 202 of file instance_pwm.h.

◆ REG_PWM_CMPMUPD6

#define REG_PWM_CMPMUPD6 (*(__O uint32_t*)0x4002019CU)

(PWM) PWM Comparison 6 Mode Update Register

Definition at line 206 of file instance_pwm.h.

◆ REG_PWM_CMPMUPD7

#define REG_PWM_CMPMUPD7 (*(__O uint32_t*)0x400201ACU)

(PWM) PWM Comparison 7 Mode Update Register

Definition at line 210 of file instance_pwm.h.

◆ REG_PWM_CMPV0

#define REG_PWM_CMPV0 (*(__IO uint32_t*)0x40020130U)

(PWM) PWM Comparison 0 Value Register

Definition at line 179 of file instance_pwm.h.

◆ REG_PWM_CMPV1

#define REG_PWM_CMPV1 (*(__IO uint32_t*)0x40020140U)

(PWM) PWM Comparison 1 Value Register

Definition at line 183 of file instance_pwm.h.

◆ REG_PWM_CMPV2

#define REG_PWM_CMPV2 (*(__IO uint32_t*)0x40020150U)

(PWM) PWM Comparison 2 Value Register

Definition at line 187 of file instance_pwm.h.

◆ REG_PWM_CMPV3

#define REG_PWM_CMPV3 (*(__IO uint32_t*)0x40020160U)

(PWM) PWM Comparison 3 Value Register

Definition at line 191 of file instance_pwm.h.

◆ REG_PWM_CMPV4

#define REG_PWM_CMPV4 (*(__IO uint32_t*)0x40020170U)

(PWM) PWM Comparison 4 Value Register

Definition at line 195 of file instance_pwm.h.

◆ REG_PWM_CMPV5

#define REG_PWM_CMPV5 (*(__IO uint32_t*)0x40020180U)

(PWM) PWM Comparison 5 Value Register

Definition at line 199 of file instance_pwm.h.

◆ REG_PWM_CMPV6

#define REG_PWM_CMPV6 (*(__IO uint32_t*)0x40020190U)

(PWM) PWM Comparison 6 Value Register

Definition at line 203 of file instance_pwm.h.

◆ REG_PWM_CMPV7

#define REG_PWM_CMPV7 (*(__IO uint32_t*)0x400201A0U)

(PWM) PWM Comparison 7 Value Register

Definition at line 207 of file instance_pwm.h.

◆ REG_PWM_CMPVUPD0

#define REG_PWM_CMPVUPD0 (*(__O uint32_t*)0x40020134U)

(PWM) PWM Comparison 0 Value Update Register

Definition at line 180 of file instance_pwm.h.

◆ REG_PWM_CMPVUPD1

#define REG_PWM_CMPVUPD1 (*(__O uint32_t*)0x40020144U)

(PWM) PWM Comparison 1 Value Update Register

Definition at line 184 of file instance_pwm.h.

◆ REG_PWM_CMPVUPD2

#define REG_PWM_CMPVUPD2 (*(__O uint32_t*)0x40020154U)

(PWM) PWM Comparison 2 Value Update Register

Definition at line 188 of file instance_pwm.h.

◆ REG_PWM_CMPVUPD3

#define REG_PWM_CMPVUPD3 (*(__O uint32_t*)0x40020164U)

(PWM) PWM Comparison 3 Value Update Register

Definition at line 192 of file instance_pwm.h.

◆ REG_PWM_CMPVUPD4

#define REG_PWM_CMPVUPD4 (*(__O uint32_t*)0x40020174U)

(PWM) PWM Comparison 4 Value Update Register

Definition at line 196 of file instance_pwm.h.

◆ REG_PWM_CMPVUPD5

#define REG_PWM_CMPVUPD5 (*(__O uint32_t*)0x40020184U)

(PWM) PWM Comparison 5 Value Update Register

Definition at line 200 of file instance_pwm.h.

◆ REG_PWM_CMPVUPD6

#define REG_PWM_CMPVUPD6 (*(__O uint32_t*)0x40020194U)

(PWM) PWM Comparison 6 Value Update Register

Definition at line 204 of file instance_pwm.h.

◆ REG_PWM_CMPVUPD7

#define REG_PWM_CMPVUPD7 (*(__O uint32_t*)0x400201A4U)

(PWM) PWM Comparison 7 Value Update Register

Definition at line 208 of file instance_pwm.h.

◆ REG_PWM_CMR0

#define REG_PWM_CMR0 (*(__IO uint32_t*)0x40020200U)

(PWM) PWM Channel Mode Register (ch_num = 0)

Definition at line 211 of file instance_pwm.h.

◆ REG_PWM_CMR1

#define REG_PWM_CMR1 (*(__IO uint32_t*)0x40020220U)

(PWM) PWM Channel Mode Register (ch_num = 1)

Definition at line 219 of file instance_pwm.h.

◆ REG_PWM_CMR2

#define REG_PWM_CMR2 (*(__IO uint32_t*)0x40020240U)

(PWM) PWM Channel Mode Register (ch_num = 2)

Definition at line 227 of file instance_pwm.h.

◆ REG_PWM_CMR3

#define REG_PWM_CMR3 (*(__IO uint32_t*)0x40020260U)

(PWM) PWM Channel Mode Register (ch_num = 3)

Definition at line 235 of file instance_pwm.h.

◆ REG_PWM_CPRD0

#define REG_PWM_CPRD0 (*(__IO uint32_t*)0x4002020CU)

(PWM) PWM Channel Period Register (ch_num = 0)

Definition at line 214 of file instance_pwm.h.

◆ REG_PWM_CPRD1

#define REG_PWM_CPRD1 (*(__IO uint32_t*)0x4002022CU)

(PWM) PWM Channel Period Register (ch_num = 1)

Definition at line 222 of file instance_pwm.h.

◆ REG_PWM_CPRD2

#define REG_PWM_CPRD2 (*(__IO uint32_t*)0x4002024CU)

(PWM) PWM Channel Period Register (ch_num = 2)

Definition at line 230 of file instance_pwm.h.

◆ REG_PWM_CPRD3

#define REG_PWM_CPRD3 (*(__IO uint32_t*)0x4002026CU)

(PWM) PWM Channel Period Register (ch_num = 3)

Definition at line 238 of file instance_pwm.h.

◆ REG_PWM_CPRDUPD0

#define REG_PWM_CPRDUPD0 (*(__O uint32_t*)0x40020210U)

(PWM) PWM Channel Period Update Register (ch_num = 0)

Definition at line 215 of file instance_pwm.h.

◆ REG_PWM_CPRDUPD1

#define REG_PWM_CPRDUPD1 (*(__O uint32_t*)0x40020230U)

(PWM) PWM Channel Period Update Register (ch_num = 1)

Definition at line 223 of file instance_pwm.h.

◆ REG_PWM_CPRDUPD2

#define REG_PWM_CPRDUPD2 (*(__O uint32_t*)0x40020250U)

(PWM) PWM Channel Period Update Register (ch_num = 2)

Definition at line 231 of file instance_pwm.h.

◆ REG_PWM_CPRDUPD3

#define REG_PWM_CPRDUPD3 (*(__O uint32_t*)0x40020270U)

(PWM) PWM Channel Period Update Register (ch_num = 3)

Definition at line 239 of file instance_pwm.h.

◆ REG_PWM_DIS

#define REG_PWM_DIS (*(__O uint32_t*)0x40020008U)

(PWM) PWM Disable Register

Definition at line 144 of file instance_pwm.h.

◆ REG_PWM_DT0

#define REG_PWM_DT0 (*(__IO uint32_t*)0x40020218U)

(PWM) PWM Channel Dead Time Register (ch_num = 0)

Definition at line 217 of file instance_pwm.h.

◆ REG_PWM_DT1

#define REG_PWM_DT1 (*(__IO uint32_t*)0x40020238U)

(PWM) PWM Channel Dead Time Register (ch_num = 1)

Definition at line 225 of file instance_pwm.h.

◆ REG_PWM_DT2

#define REG_PWM_DT2 (*(__IO uint32_t*)0x40020258U)

(PWM) PWM Channel Dead Time Register (ch_num = 2)

Definition at line 233 of file instance_pwm.h.

◆ REG_PWM_DT3

#define REG_PWM_DT3 (*(__IO uint32_t*)0x40020278U)

(PWM) PWM Channel Dead Time Register (ch_num = 3)

Definition at line 241 of file instance_pwm.h.

◆ REG_PWM_DTUPD0

#define REG_PWM_DTUPD0 (*(__O uint32_t*)0x4002021CU)

(PWM) PWM Channel Dead Time Update Register (ch_num = 0)

Definition at line 218 of file instance_pwm.h.

◆ REG_PWM_DTUPD1

#define REG_PWM_DTUPD1 (*(__O uint32_t*)0x4002023CU)

(PWM) PWM Channel Dead Time Update Register (ch_num = 1)

Definition at line 226 of file instance_pwm.h.

◆ REG_PWM_DTUPD2

#define REG_PWM_DTUPD2 (*(__O uint32_t*)0x4002025CU)

(PWM) PWM Channel Dead Time Update Register (ch_num = 2)

Definition at line 234 of file instance_pwm.h.

◆ REG_PWM_DTUPD3

#define REG_PWM_DTUPD3 (*(__O uint32_t*)0x4002027CU)

(PWM) PWM Channel Dead Time Update Register (ch_num = 3)

Definition at line 242 of file instance_pwm.h.

◆ REG_PWM_ELMR

#define REG_PWM_ELMR (*(__IO uint32_t*)0x4002007CU)

(PWM) PWM Event Line 0 Mode Register

Definition at line 169 of file instance_pwm.h.

◆ REG_PWM_ENA

#define REG_PWM_ENA (*(__O uint32_t*)0x40020004U)

(PWM) PWM Enable Register

Definition at line 143 of file instance_pwm.h.

◆ REG_PWM_FCR

#define REG_PWM_FCR (*(__O uint32_t*)0x40020064U)

(PWM) PWM Fault Clear Register

Definition at line 166 of file instance_pwm.h.

◆ REG_PWM_FMR

#define REG_PWM_FMR (*(__IO uint32_t*)0x4002005CU)

(PWM) PWM Fault Mode Register

Definition at line 164 of file instance_pwm.h.

◆ REG_PWM_FPE

#define REG_PWM_FPE (*(__IO uint32_t*)0x4002006CU)

(PWM) PWM Fault Protection Enable Register

Definition at line 168 of file instance_pwm.h.

◆ REG_PWM_FPV

#define REG_PWM_FPV (*(__IO uint32_t*)0x40020068U)

(PWM) PWM Fault Protection Value Register

Definition at line 167 of file instance_pwm.h.

◆ REG_PWM_FSR

#define REG_PWM_FSR (*(__I uint32_t*)0x40020060U)

(PWM) PWM Fault Status Register

Definition at line 165 of file instance_pwm.h.

◆ REG_PWM_IDR1

#define REG_PWM_IDR1 (*(__O uint32_t*)0x40020014U)

(PWM) PWM Interrupt Disable Register 1

Definition at line 147 of file instance_pwm.h.

◆ REG_PWM_IDR2

#define REG_PWM_IDR2 (*(__O uint32_t*)0x40020038U)

(PWM) PWM Interrupt Disable Register 2

Definition at line 155 of file instance_pwm.h.

◆ REG_PWM_IER1

#define REG_PWM_IER1 (*(__O uint32_t*)0x40020010U)

(PWM) PWM Interrupt Enable Register 1

Definition at line 146 of file instance_pwm.h.

◆ REG_PWM_IER2

#define REG_PWM_IER2 (*(__O uint32_t*)0x40020034U)

(PWM) PWM Interrupt Enable Register 2

Definition at line 154 of file instance_pwm.h.

◆ REG_PWM_IMR1

#define REG_PWM_IMR1 (*(__I uint32_t*)0x40020018U)

(PWM) PWM Interrupt Mask Register 1

Definition at line 148 of file instance_pwm.h.

◆ REG_PWM_IMR2

#define REG_PWM_IMR2 (*(__I uint32_t*)0x4002003CU)

(PWM) PWM Interrupt Mask Register 2

Definition at line 156 of file instance_pwm.h.

◆ REG_PWM_ISR1

#define REG_PWM_ISR1 (*(__I uint32_t*)0x4002001CU)

(PWM) PWM Interrupt Status Register 1

Definition at line 149 of file instance_pwm.h.

◆ REG_PWM_ISR2

#define REG_PWM_ISR2 (*(__I uint32_t*)0x40020040U)

(PWM) PWM Interrupt Status Register 2

Definition at line 157 of file instance_pwm.h.

◆ REG_PWM_OOV

#define REG_PWM_OOV (*(__IO uint32_t*)0x40020044U)

(PWM) PWM Output Override Value Register

Definition at line 158 of file instance_pwm.h.

◆ REG_PWM_OS

#define REG_PWM_OS (*(__IO uint32_t*)0x40020048U)

(PWM) PWM Output Selection Register

Definition at line 159 of file instance_pwm.h.

◆ REG_PWM_OSC

#define REG_PWM_OSC (*(__O uint32_t*)0x40020050U)

(PWM) PWM Output Selection Clear Register

Definition at line 161 of file instance_pwm.h.

◆ REG_PWM_OSCUPD

#define REG_PWM_OSCUPD (*(__O uint32_t*)0x40020058U)

(PWM) PWM Output Selection Clear Update Register

Definition at line 163 of file instance_pwm.h.

◆ REG_PWM_OSS

#define REG_PWM_OSS (*(__O uint32_t*)0x4002004CU)

(PWM) PWM Output Selection Set Register

Definition at line 160 of file instance_pwm.h.

◆ REG_PWM_OSSUPD

#define REG_PWM_OSSUPD (*(__O uint32_t*)0x40020054U)

(PWM) PWM Output Selection Set Update Register

Definition at line 162 of file instance_pwm.h.

◆ REG_PWM_PTCR

#define REG_PWM_PTCR (*(__O uint32_t*)0x40020120U)

(PWM) Transfer Control Register

Definition at line 177 of file instance_pwm.h.

◆ REG_PWM_PTSR

#define REG_PWM_PTSR (*(__I uint32_t*)0x40020124U)

(PWM) Transfer Status Register

Definition at line 178 of file instance_pwm.h.

◆ REG_PWM_SCM

#define REG_PWM_SCM (*(__IO uint32_t*)0x40020020U)

(PWM) PWM Sync Channels Mode Register

Definition at line 150 of file instance_pwm.h.

◆ REG_PWM_SCUC

#define REG_PWM_SCUC (*(__IO uint32_t*)0x40020028U)

(PWM) PWM Sync Channels Update Control Register

Definition at line 151 of file instance_pwm.h.

◆ REG_PWM_SCUP

#define REG_PWM_SCUP (*(__IO uint32_t*)0x4002002CU)

(PWM) PWM Sync Channels Update Period Register

Definition at line 152 of file instance_pwm.h.

◆ REG_PWM_SCUPUPD

#define REG_PWM_SCUPUPD (*(__O uint32_t*)0x40020030U)

(PWM) PWM Sync Channels Update Period Update Register

Definition at line 153 of file instance_pwm.h.

◆ REG_PWM_SMMR

#define REG_PWM_SMMR (*(__IO uint32_t*)0x400200B0U)

(PWM) PWM Stepper Motor Mode Register

Definition at line 170 of file instance_pwm.h.

◆ REG_PWM_SR

#define REG_PWM_SR (*(__I uint32_t*)0x4002000CU)

(PWM) PWM Status Register

Definition at line 145 of file instance_pwm.h.

◆ REG_PWM_TCR

#define REG_PWM_TCR (*(__IO uint32_t*)0x4002010CU)

(PWM) Transmit Counter Register

Definition at line 174 of file instance_pwm.h.

◆ REG_PWM_TNCR

#define REG_PWM_TNCR (*(__IO uint32_t*)0x4002011CU)

(PWM) Transmit Next Counter Register

Definition at line 176 of file instance_pwm.h.

◆ REG_PWM_TNPR

#define REG_PWM_TNPR (*(__IO uint32_t*)0x40020118U)

(PWM) Transmit Next Pointer Register

Definition at line 175 of file instance_pwm.h.

◆ REG_PWM_TPR

#define REG_PWM_TPR (*(__IO uint32_t*)0x40020108U)

(PWM) Transmit Pointer Register

Definition at line 173 of file instance_pwm.h.

◆ REG_PWM_WPCR

#define REG_PWM_WPCR (*(__O uint32_t*)0x400200E4U)

(PWM) PWM Write Protection Control Register

Definition at line 171 of file instance_pwm.h.

◆ REG_PWM_WPSR

#define REG_PWM_WPSR (*(__I uint32_t*)0x400200E8U)

(PWM) PWM Write Protection Status Register

Definition at line 172 of file instance_pwm.h.

Macros