Macros
#define	REG_SPI_CR ((__O uint32_t)0x40008000U)
	(SPI) Control Register
#define	REG_SPI_CSR ((__IO uint32_t)0x40008030U)
	(SPI) Chip Select Register
#define	REG_SPI_IDR ((__O uint32_t)0x40008018U)
	(SPI) Interrupt Disable Register
#define	REG_SPI_IER ((__O uint32_t)0x40008014U)
	(SPI) Interrupt Enable Register
#define	REG_SPI_IMR ((__I uint32_t)0x4000801CU)
	(SPI) Interrupt Mask Register
#define	REG_SPI_MR ((__IO uint32_t)0x40008004U)
	(SPI) Mode Register
#define	REG_SPI_PTCR ((__O uint32_t)0x40008120U)
	(SPI) Transfer Control Register
#define	REG_SPI_PTSR ((__I uint32_t)0x40008124U)
	(SPI) Transfer Status Register
#define	REG_SPI_RCR ((__IO uint32_t)0x40008104U)
	(SPI) Receive Counter Register
#define	REG_SPI_RDR ((__I uint32_t)0x40008008U)
	(SPI) Receive Data Register
#define	REG_SPI_RNCR ((__IO uint32_t)0x40008114U)
	(SPI) Receive Next Counter Register
#define	REG_SPI_RNPR ((__IO uint32_t)0x40008110U)
	(SPI) Receive Next Pointer Register
#define	REG_SPI_RPR ((__IO uint32_t)0x40008100U)
	(SPI) Receive Pointer Register
#define	REG_SPI_SR ((__I uint32_t)0x40008010U)
	(SPI) Status Register
#define	REG_SPI_TCR ((__IO uint32_t)0x4000810CU)
	(SPI) Transmit Counter Register
#define	REG_SPI_TDR ((__O uint32_t)0x4000800CU)
	(SPI) Transmit Data Register
#define	REG_SPI_TNCR ((__IO uint32_t)0x4000811CU)
	(SPI) Transmit Next Counter Register
#define	REG_SPI_TNPR ((__IO uint32_t)0x40008118U)
	(SPI) Transmit Next Pointer Register
#define	REG_SPI_TPR ((__IO uint32_t)0x40008108U)
	(SPI) Transmit Pointer Register
#define	REG_SPI_WPMR ((__IO uint32_t)0x400080E4U)
	(SPI) Write Protection Control Register
#define	REG_SPI_WPSR ((__I uint32_t)0x400080E8U)
	(SPI) Write Protection Status Register

Detailed Description

and its subsidiaries.

\cond ASF_LICENSE

Definition in file instance_spi.h.

Macro Definition Documentation

◆ REG_SPI_CR

#define REG_SPI_CR (*(__O uint32_t*)0x40008000U)

(SPI) Control Register

Definition at line 62 of file instance_spi.h.

◆ REG_SPI_CSR

#define REG_SPI_CSR (*(__IO uint32_t*)0x40008030U)

(SPI) Chip Select Register

Definition at line 70 of file instance_spi.h.

◆ REG_SPI_IDR

#define REG_SPI_IDR (*(__O uint32_t*)0x40008018U)

(SPI) Interrupt Disable Register

Definition at line 68 of file instance_spi.h.

◆ REG_SPI_IER

#define REG_SPI_IER (*(__O uint32_t*)0x40008014U)

(SPI) Interrupt Enable Register

Definition at line 67 of file instance_spi.h.

◆ REG_SPI_IMR

#define REG_SPI_IMR (*(__I uint32_t*)0x4000801CU)

(SPI) Interrupt Mask Register

Definition at line 69 of file instance_spi.h.

◆ REG_SPI_MR

#define REG_SPI_MR (*(__IO uint32_t*)0x40008004U)

(SPI) Mode Register

Definition at line 63 of file instance_spi.h.

◆ REG_SPI_PTCR

#define REG_SPI_PTCR (*(__O uint32_t*)0x40008120U)

(SPI) Transfer Control Register

Definition at line 81 of file instance_spi.h.

◆ REG_SPI_PTSR

#define REG_SPI_PTSR (*(__I uint32_t*)0x40008124U)

(SPI) Transfer Status Register

Definition at line 82 of file instance_spi.h.

◆ REG_SPI_RCR

#define REG_SPI_RCR (*(__IO uint32_t*)0x40008104U)

(SPI) Receive Counter Register

Definition at line 74 of file instance_spi.h.

◆ REG_SPI_RDR

#define REG_SPI_RDR (*(__I uint32_t*)0x40008008U)

(SPI) Receive Data Register

Definition at line 64 of file instance_spi.h.

◆ REG_SPI_RNCR

#define REG_SPI_RNCR (*(__IO uint32_t*)0x40008114U)

(SPI) Receive Next Counter Register

Definition at line 78 of file instance_spi.h.

◆ REG_SPI_RNPR

#define REG_SPI_RNPR (*(__IO uint32_t*)0x40008110U)

(SPI) Receive Next Pointer Register

Definition at line 77 of file instance_spi.h.

◆ REG_SPI_RPR

#define REG_SPI_RPR (*(__IO uint32_t*)0x40008100U)

(SPI) Receive Pointer Register

Definition at line 73 of file instance_spi.h.

◆ REG_SPI_SR

#define REG_SPI_SR (*(__I uint32_t*)0x40008010U)

(SPI) Status Register

Definition at line 66 of file instance_spi.h.

◆ REG_SPI_TCR

#define REG_SPI_TCR (*(__IO uint32_t*)0x4000810CU)

(SPI) Transmit Counter Register

Definition at line 76 of file instance_spi.h.

◆ REG_SPI_TDR

#define REG_SPI_TDR (*(__O uint32_t*)0x4000800CU)

(SPI) Transmit Data Register

Definition at line 65 of file instance_spi.h.

◆ REG_SPI_TNCR

#define REG_SPI_TNCR (*(__IO uint32_t*)0x4000811CU)

(SPI) Transmit Next Counter Register

Definition at line 80 of file instance_spi.h.

◆ REG_SPI_TNPR

#define REG_SPI_TNPR (*(__IO uint32_t*)0x40008118U)

(SPI) Transmit Next Pointer Register

Definition at line 79 of file instance_spi.h.

◆ REG_SPI_TPR

#define REG_SPI_TPR (*(__IO uint32_t*)0x40008108U)

(SPI) Transmit Pointer Register

Definition at line 75 of file instance_spi.h.

◆ REG_SPI_WPMR

#define REG_SPI_WPMR (*(__IO uint32_t*)0x400080E4U)

(SPI) Write Protection Control Register

Definition at line 71 of file instance_spi.h.

◆ REG_SPI_WPSR

#define REG_SPI_WPSR (*(__I uint32_t*)0x400080E8U)

(SPI) Write Protection Status Register

Definition at line 72 of file instance_spi.h.

Macros