instance_tc0.h

Go to the documentation of this file.

/*
 * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
 */
 
#ifndef _SAM4S_TC0_INSTANCE_
#define _SAM4S_TC0_INSTANCE_
 
/* ========== Register definition for TC0 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
  #define REG_TC0_CCR0                   (0x40010000U) 
  #define REG_TC0_CMR0                   (0x40010004U) 
  #define REG_TC0_SMMR0                  (0x40010008U) 
  #define REG_TC0_CV0                    (0x40010010U) 
  #define REG_TC0_RA0                    (0x40010014U) 
  #define REG_TC0_RB0                    (0x40010018U) 
  #define REG_TC0_RC0                    (0x4001001CU) 
  #define REG_TC0_SR0                    (0x40010020U) 
  #define REG_TC0_IER0                   (0x40010024U) 
  #define REG_TC0_IDR0                   (0x40010028U) 
  #define REG_TC0_IMR0                   (0x4001002CU) 
  #define REG_TC0_CCR1                   (0x40010040U) 
  #define REG_TC0_CMR1                   (0x40010044U) 
  #define REG_TC0_SMMR1                  (0x40010048U) 
  #define REG_TC0_CV1                    (0x40010050U) 
  #define REG_TC0_RA1                    (0x40010054U) 
  #define REG_TC0_RB1                    (0x40010058U) 
  #define REG_TC0_RC1                    (0x4001005CU) 
  #define REG_TC0_SR1                    (0x40010060U) 
  #define REG_TC0_IER1                   (0x40010064U) 
  #define REG_TC0_IDR1                   (0x40010068U) 
  #define REG_TC0_IMR1                   (0x4001006CU) 
  #define REG_TC0_CCR2                   (0x40010080U) 
  #define REG_TC0_CMR2                   (0x40010084U) 
  #define REG_TC0_SMMR2                  (0x40010088U) 
  #define REG_TC0_CV2                    (0x40010090U) 
  #define REG_TC0_RA2                    (0x40010094U) 
  #define REG_TC0_RB2                    (0x40010098U) 
  #define REG_TC0_RC2                    (0x4001009CU) 
  #define REG_TC0_SR2                    (0x400100A0U) 
  #define REG_TC0_IER2                   (0x400100A4U) 
  #define REG_TC0_IDR2                   (0x400100A8U) 
  #define REG_TC0_IMR2                   (0x400100ACU) 
  #define REG_TC0_BCR                    (0x400100C0U) 
  #define REG_TC0_BMR                    (0x400100C4U) 
  #define REG_TC0_QIER                   (0x400100C8U) 
  #define REG_TC0_QIDR                   (0x400100CCU) 
  #define REG_TC0_QIMR                   (0x400100D0U) 
  #define REG_TC0_QISR                   (0x400100D4U) 
  #define REG_TC0_FMR                    (0x400100D8U) 
  #define REG_TC0_WPMR                   (0x400100E4U) 
#else
  #define REG_TC0_CCR0  (*(__O  uint32_t*)0x40010000U) 
  #define REG_TC0_CMR0  (*(__IO uint32_t*)0x40010004U) 
  #define REG_TC0_SMMR0 (*(__IO uint32_t*)0x40010008U) 
  #define REG_TC0_CV0   (*(__I  uint32_t*)0x40010010U) 
  #define REG_TC0_RA0   (*(__IO uint32_t*)0x40010014U) 
  #define REG_TC0_RB0   (*(__IO uint32_t*)0x40010018U) 
  #define REG_TC0_RC0   (*(__IO uint32_t*)0x4001001CU) 
  #define REG_TC0_SR0   (*(__I  uint32_t*)0x40010020U) 
  #define REG_TC0_IER0  (*(__O  uint32_t*)0x40010024U) 
  #define REG_TC0_IDR0  (*(__O  uint32_t*)0x40010028U) 
  #define REG_TC0_IMR0  (*(__I  uint32_t*)0x4001002CU) 
  #define REG_TC0_CCR1  (*(__O  uint32_t*)0x40010040U) 
  #define REG_TC0_CMR1  (*(__IO uint32_t*)0x40010044U) 
  #define REG_TC0_SMMR1 (*(__IO uint32_t*)0x40010048U) 
  #define REG_TC0_CV1   (*(__I  uint32_t*)0x40010050U) 
  #define REG_TC0_RA1   (*(__IO uint32_t*)0x40010054U) 
  #define REG_TC0_RB1   (*(__IO uint32_t*)0x40010058U) 
  #define REG_TC0_RC1   (*(__IO uint32_t*)0x4001005CU) 
  #define REG_TC0_SR1   (*(__I  uint32_t*)0x40010060U) 
  #define REG_TC0_IER1  (*(__O  uint32_t*)0x40010064U) 
  #define REG_TC0_IDR1  (*(__O  uint32_t*)0x40010068U) 
  #define REG_TC0_IMR1  (*(__I  uint32_t*)0x4001006CU) 
  #define REG_TC0_CCR2  (*(__O  uint32_t*)0x40010080U) 
  #define REG_TC0_CMR2  (*(__IO uint32_t*)0x40010084U) 
  #define REG_TC0_SMMR2 (*(__IO uint32_t*)0x40010088U) 
  #define REG_TC0_CV2   (*(__I  uint32_t*)0x40010090U) 
  #define REG_TC0_RA2   (*(__IO uint32_t*)0x40010094U) 
  #define REG_TC0_RB2   (*(__IO uint32_t*)0x40010098U) 
  #define REG_TC0_RC2   (*(__IO uint32_t*)0x4001009CU) 
  #define REG_TC0_SR2   (*(__I  uint32_t*)0x400100A0U) 
  #define REG_TC0_IER2  (*(__O  uint32_t*)0x400100A4U) 
  #define REG_TC0_IDR2  (*(__O  uint32_t*)0x400100A8U) 
  #define REG_TC0_IMR2  (*(__I  uint32_t*)0x400100ACU) 
  #define REG_TC0_BCR   (*(__O  uint32_t*)0x400100C0U) 
  #define REG_TC0_BMR   (*(__IO uint32_t*)0x400100C4U) 
  #define REG_TC0_QIER  (*(__O  uint32_t*)0x400100C8U) 
  #define REG_TC0_QIDR  (*(__O  uint32_t*)0x400100CCU) 
  #define REG_TC0_QIMR  (*(__I  uint32_t*)0x400100D0U) 
  #define REG_TC0_QISR  (*(__I  uint32_t*)0x400100D4U) 
  #define REG_TC0_FMR   (*(__IO uint32_t*)0x400100D8U) 
  #define REG_TC0_WPMR  (*(__IO uint32_t*)0x400100E4U) 
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#endif /* _SAM4S_TC0_INSTANCE_ */