Macros
#define	REG_TC0_BCR ((__O uint32_t)0x400100C0U)
	(TC0) Block Control Register
#define	REG_TC0_BMR ((__IO uint32_t)0x400100C4U)
	(TC0) Block Mode Register
#define	REG_TC0_CCR0 ((__O uint32_t)0x40010000U)
	(TC0) Channel Control Register (channel = 0)
#define	REG_TC0_CCR1 ((__O uint32_t)0x40010040U)
	(TC0) Channel Control Register (channel = 1)
#define	REG_TC0_CCR2 ((__O uint32_t)0x40010080U)
	(TC0) Channel Control Register (channel = 2)
#define	REG_TC0_CMR0 ((__IO uint32_t)0x40010004U)
	(TC0) Channel Mode Register (channel = 0)
#define	REG_TC0_CMR1 ((__IO uint32_t)0x40010044U)
	(TC0) Channel Mode Register (channel = 1)
#define	REG_TC0_CMR2 ((__IO uint32_t)0x40010084U)
	(TC0) Channel Mode Register (channel = 2)
#define	REG_TC0_CV0 ((__I uint32_t)0x40010010U)
	(TC0) Counter Value (channel = 0)
#define	REG_TC0_CV1 ((__I uint32_t)0x40010050U)
	(TC0) Counter Value (channel = 1)
#define	REG_TC0_CV2 ((__I uint32_t)0x40010090U)
	(TC0) Counter Value (channel = 2)
#define	REG_TC0_FMR ((__IO uint32_t)0x400100D8U)
	(TC0) Fault Mode Register
#define	REG_TC0_IDR0 ((__O uint32_t)0x40010028U)
	(TC0) Interrupt Disable Register (channel = 0)
#define	REG_TC0_IDR1 ((__O uint32_t)0x40010068U)
	(TC0) Interrupt Disable Register (channel = 1)
#define	REG_TC0_IDR2 ((__O uint32_t)0x400100A8U)
	(TC0) Interrupt Disable Register (channel = 2)
#define	REG_TC0_IER0 ((__O uint32_t)0x40010024U)
	(TC0) Interrupt Enable Register (channel = 0)
#define	REG_TC0_IER1 ((__O uint32_t)0x40010064U)
	(TC0) Interrupt Enable Register (channel = 1)
#define	REG_TC0_IER2 ((__O uint32_t)0x400100A4U)
	(TC0) Interrupt Enable Register (channel = 2)
#define	REG_TC0_IMR0 ((__I uint32_t)0x4001002CU)
	(TC0) Interrupt Mask Register (channel = 0)
#define	REG_TC0_IMR1 ((__I uint32_t)0x4001006CU)
	(TC0) Interrupt Mask Register (channel = 1)
#define	REG_TC0_IMR2 ((__I uint32_t)0x400100ACU)
	(TC0) Interrupt Mask Register (channel = 2)
#define	REG_TC0_QIDR ((__O uint32_t)0x400100CCU)
	(TC0) QDEC Interrupt Disable Register
#define	REG_TC0_QIER ((__O uint32_t)0x400100C8U)
	(TC0) QDEC Interrupt Enable Register
#define	REG_TC0_QIMR ((__I uint32_t)0x400100D0U)
	(TC0) QDEC Interrupt Mask Register
#define	REG_TC0_QISR ((__I uint32_t)0x400100D4U)
	(TC0) QDEC Interrupt Status Register
#define	REG_TC0_RA0 ((__IO uint32_t)0x40010014U)
	(TC0) Register A (channel = 0)
#define	REG_TC0_RA1 ((__IO uint32_t)0x40010054U)
	(TC0) Register A (channel = 1)
#define	REG_TC0_RA2 ((__IO uint32_t)0x40010094U)
	(TC0) Register A (channel = 2)
#define	REG_TC0_RB0 ((__IO uint32_t)0x40010018U)
	(TC0) Register B (channel = 0)
#define	REG_TC0_RB1 ((__IO uint32_t)0x40010058U)
	(TC0) Register B (channel = 1)
#define	REG_TC0_RB2 ((__IO uint32_t)0x40010098U)
	(TC0) Register B (channel = 2)
#define	REG_TC0_RC0 ((__IO uint32_t)0x4001001CU)
	(TC0) Register C (channel = 0)
#define	REG_TC0_RC1 ((__IO uint32_t)0x4001005CU)
	(TC0) Register C (channel = 1)
#define	REG_TC0_RC2 ((__IO uint32_t)0x4001009CU)
	(TC0) Register C (channel = 2)
#define	REG_TC0_SMMR0 ((__IO uint32_t)0x40010008U)
	(TC0) Stepper Motor Mode Register (channel = 0)
#define	REG_TC0_SMMR1 ((__IO uint32_t)0x40010048U)
	(TC0) Stepper Motor Mode Register (channel = 1)
#define	REG_TC0_SMMR2 ((__IO uint32_t)0x40010088U)
	(TC0) Stepper Motor Mode Register (channel = 2)
#define	REG_TC0_SR0 ((__I uint32_t)0x40010020U)
	(TC0) Status Register (channel = 0)
#define	REG_TC0_SR1 ((__I uint32_t)0x40010060U)
	(TC0) Status Register (channel = 1)
#define	REG_TC0_SR2 ((__I uint32_t)0x400100A0U)
	(TC0) Status Register (channel = 2)
#define	REG_TC0_WPMR ((__IO uint32_t)0x400100E4U)
	(TC0) Write Protect Mode Register

Detailed Description

and its subsidiaries.

\cond ASF_LICENSE

Definition in file instance_tc0.h.

Macro Definition Documentation

◆ REG_TC0_BCR

#define REG_TC0_BCR (*(__O uint32_t*)0x400100C0U)

(TC0) Block Control Register

Definition at line 115 of file instance_tc0.h.

◆ REG_TC0_BMR

#define REG_TC0_BMR (*(__IO uint32_t*)0x400100C4U)

(TC0) Block Mode Register

Definition at line 116 of file instance_tc0.h.

◆ REG_TC0_CCR0

#define REG_TC0_CCR0 (*(__O uint32_t*)0x40010000U)

(TC0) Channel Control Register (channel = 0)

Definition at line 82 of file instance_tc0.h.

◆ REG_TC0_CCR1

#define REG_TC0_CCR1 (*(__O uint32_t*)0x40010040U)

(TC0) Channel Control Register (channel = 1)

Definition at line 93 of file instance_tc0.h.

◆ REG_TC0_CCR2

#define REG_TC0_CCR2 (*(__O uint32_t*)0x40010080U)

(TC0) Channel Control Register (channel = 2)

Definition at line 104 of file instance_tc0.h.

◆ REG_TC0_CMR0

#define REG_TC0_CMR0 (*(__IO uint32_t*)0x40010004U)

(TC0) Channel Mode Register (channel = 0)

Definition at line 83 of file instance_tc0.h.

◆ REG_TC0_CMR1

#define REG_TC0_CMR1 (*(__IO uint32_t*)0x40010044U)

(TC0) Channel Mode Register (channel = 1)

Definition at line 94 of file instance_tc0.h.

◆ REG_TC0_CMR2

#define REG_TC0_CMR2 (*(__IO uint32_t*)0x40010084U)

(TC0) Channel Mode Register (channel = 2)

Definition at line 105 of file instance_tc0.h.

◆ REG_TC0_CV0

#define REG_TC0_CV0 (*(__I uint32_t*)0x40010010U)

(TC0) Counter Value (channel = 0)

Definition at line 85 of file instance_tc0.h.

◆ REG_TC0_CV1

#define REG_TC0_CV1 (*(__I uint32_t*)0x40010050U)

(TC0) Counter Value (channel = 1)

Definition at line 96 of file instance_tc0.h.

◆ REG_TC0_CV2

#define REG_TC0_CV2 (*(__I uint32_t*)0x40010090U)

(TC0) Counter Value (channel = 2)

Definition at line 107 of file instance_tc0.h.

◆ REG_TC0_FMR

#define REG_TC0_FMR (*(__IO uint32_t*)0x400100D8U)

(TC0) Fault Mode Register

Definition at line 121 of file instance_tc0.h.

◆ REG_TC0_IDR0

#define REG_TC0_IDR0 (*(__O uint32_t*)0x40010028U)

(TC0) Interrupt Disable Register (channel = 0)

Definition at line 91 of file instance_tc0.h.

◆ REG_TC0_IDR1

#define REG_TC0_IDR1 (*(__O uint32_t*)0x40010068U)

(TC0) Interrupt Disable Register (channel = 1)

Definition at line 102 of file instance_tc0.h.

◆ REG_TC0_IDR2

#define REG_TC0_IDR2 (*(__O uint32_t*)0x400100A8U)

(TC0) Interrupt Disable Register (channel = 2)

Definition at line 113 of file instance_tc0.h.

◆ REG_TC0_IER0

#define REG_TC0_IER0 (*(__O uint32_t*)0x40010024U)

(TC0) Interrupt Enable Register (channel = 0)

Definition at line 90 of file instance_tc0.h.

◆ REG_TC0_IER1

#define REG_TC0_IER1 (*(__O uint32_t*)0x40010064U)

(TC0) Interrupt Enable Register (channel = 1)

Definition at line 101 of file instance_tc0.h.

◆ REG_TC0_IER2

#define REG_TC0_IER2 (*(__O uint32_t*)0x400100A4U)

(TC0) Interrupt Enable Register (channel = 2)

Definition at line 112 of file instance_tc0.h.

◆ REG_TC0_IMR0

#define REG_TC0_IMR0 (*(__I uint32_t*)0x4001002CU)

(TC0) Interrupt Mask Register (channel = 0)

Definition at line 92 of file instance_tc0.h.

◆ REG_TC0_IMR1

#define REG_TC0_IMR1 (*(__I uint32_t*)0x4001006CU)

(TC0) Interrupt Mask Register (channel = 1)

Definition at line 103 of file instance_tc0.h.

◆ REG_TC0_IMR2

#define REG_TC0_IMR2 (*(__I uint32_t*)0x400100ACU)

(TC0) Interrupt Mask Register (channel = 2)

Definition at line 114 of file instance_tc0.h.

◆ REG_TC0_QIDR

#define REG_TC0_QIDR (*(__O uint32_t*)0x400100CCU)

(TC0) QDEC Interrupt Disable Register

Definition at line 118 of file instance_tc0.h.

◆ REG_TC0_QIER

#define REG_TC0_QIER (*(__O uint32_t*)0x400100C8U)

(TC0) QDEC Interrupt Enable Register

Definition at line 117 of file instance_tc0.h.

◆ REG_TC0_QIMR

#define REG_TC0_QIMR (*(__I uint32_t*)0x400100D0U)

(TC0) QDEC Interrupt Mask Register

Definition at line 119 of file instance_tc0.h.

◆ REG_TC0_QISR

#define REG_TC0_QISR (*(__I uint32_t*)0x400100D4U)

(TC0) QDEC Interrupt Status Register

Definition at line 120 of file instance_tc0.h.

◆ REG_TC0_RA0

#define REG_TC0_RA0 (*(__IO uint32_t*)0x40010014U)

(TC0) Register A (channel = 0)

Definition at line 86 of file instance_tc0.h.

◆ REG_TC0_RA1

#define REG_TC0_RA1 (*(__IO uint32_t*)0x40010054U)

(TC0) Register A (channel = 1)

Definition at line 97 of file instance_tc0.h.

◆ REG_TC0_RA2

#define REG_TC0_RA2 (*(__IO uint32_t*)0x40010094U)

(TC0) Register A (channel = 2)

Definition at line 108 of file instance_tc0.h.

◆ REG_TC0_RB0

#define REG_TC0_RB0 (*(__IO uint32_t*)0x40010018U)

(TC0) Register B (channel = 0)

Definition at line 87 of file instance_tc0.h.

◆ REG_TC0_RB1

#define REG_TC0_RB1 (*(__IO uint32_t*)0x40010058U)

(TC0) Register B (channel = 1)

Definition at line 98 of file instance_tc0.h.

◆ REG_TC0_RB2

#define REG_TC0_RB2 (*(__IO uint32_t*)0x40010098U)

(TC0) Register B (channel = 2)

Definition at line 109 of file instance_tc0.h.

◆ REG_TC0_RC0

#define REG_TC0_RC0 (*(__IO uint32_t*)0x4001001CU)

(TC0) Register C (channel = 0)

Definition at line 88 of file instance_tc0.h.

◆ REG_TC0_RC1

#define REG_TC0_RC1 (*(__IO uint32_t*)0x4001005CU)

(TC0) Register C (channel = 1)

Definition at line 99 of file instance_tc0.h.

◆ REG_TC0_RC2

#define REG_TC0_RC2 (*(__IO uint32_t*)0x4001009CU)

(TC0) Register C (channel = 2)

Definition at line 110 of file instance_tc0.h.

◆ REG_TC0_SMMR0

#define REG_TC0_SMMR0 (*(__IO uint32_t*)0x40010008U)

(TC0) Stepper Motor Mode Register (channel = 0)

Definition at line 84 of file instance_tc0.h.

◆ REG_TC0_SMMR1

#define REG_TC0_SMMR1 (*(__IO uint32_t*)0x40010048U)

(TC0) Stepper Motor Mode Register (channel = 1)

Definition at line 95 of file instance_tc0.h.

◆ REG_TC0_SMMR2

#define REG_TC0_SMMR2 (*(__IO uint32_t*)0x40010088U)

(TC0) Stepper Motor Mode Register (channel = 2)

Definition at line 106 of file instance_tc0.h.

◆ REG_TC0_SR0

#define REG_TC0_SR0 (*(__I uint32_t*)0x40010020U)

(TC0) Status Register (channel = 0)

Definition at line 89 of file instance_tc0.h.

◆ REG_TC0_SR1

#define REG_TC0_SR1 (*(__I uint32_t*)0x40010060U)

(TC0) Status Register (channel = 1)

Definition at line 100 of file instance_tc0.h.

◆ REG_TC0_SR2

#define REG_TC0_SR2 (*(__I uint32_t*)0x400100A0U)

(TC0) Status Register (channel = 2)

Definition at line 111 of file instance_tc0.h.

◆ REG_TC0_WPMR

#define REG_TC0_WPMR (*(__IO uint32_t*)0x400100E4U)

(TC0) Write Protect Mode Register

Definition at line 122 of file instance_tc0.h.

Macros