SAM4SD32 (SAM4S-EK2)
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instance_twi0.h
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1
31/*
32 * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
33 */
34
35#ifndef _SAM4S_TWI0_INSTANCE_
36#define _SAM4S_TWI0_INSTANCE_
37
38/* ========== Register definition for TWI0 peripheral ========== */
39#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
40 #define REG_TWI0_CR (0x40018000U)
41 #define REG_TWI0_MMR (0x40018004U)
42 #define REG_TWI0_SMR (0x40018008U)
43 #define REG_TWI0_IADR (0x4001800CU)
44 #define REG_TWI0_CWGR (0x40018010U)
45 #define REG_TWI0_SR (0x40018020U)
46 #define REG_TWI0_IER (0x40018024U)
47 #define REG_TWI0_IDR (0x40018028U)
48 #define REG_TWI0_IMR (0x4001802CU)
49 #define REG_TWI0_RHR (0x40018030U)
50 #define REG_TWI0_THR (0x40018034U)
51 #define REG_TWI0_RPR (0x40018100U)
52 #define REG_TWI0_RCR (0x40018104U)
53 #define REG_TWI0_TPR (0x40018108U)
54 #define REG_TWI0_TCR (0x4001810CU)
55 #define REG_TWI0_RNPR (0x40018110U)
56 #define REG_TWI0_RNCR (0x40018114U)
57 #define REG_TWI0_TNPR (0x40018118U)
58 #define REG_TWI0_TNCR (0x4001811CU)
59 #define REG_TWI0_PTCR (0x40018120U)
60 #define REG_TWI0_PTSR (0x40018124U)
61#else
62 #define REG_TWI0_CR (*(__O uint32_t*)0x40018000U)
63 #define REG_TWI0_MMR (*(__IO uint32_t*)0x40018004U)
64 #define REG_TWI0_SMR (*(__IO uint32_t*)0x40018008U)
65 #define REG_TWI0_IADR (*(__IO uint32_t*)0x4001800CU)
66 #define REG_TWI0_CWGR (*(__IO uint32_t*)0x40018010U)
67 #define REG_TWI0_SR (*(__I uint32_t*)0x40018020U)
68 #define REG_TWI0_IER (*(__O uint32_t*)0x40018024U)
69 #define REG_TWI0_IDR (*(__O uint32_t*)0x40018028U)
70 #define REG_TWI0_IMR (*(__I uint32_t*)0x4001802CU)
71 #define REG_TWI0_RHR (*(__I uint32_t*)0x40018030U)
72 #define REG_TWI0_THR (*(__O uint32_t*)0x40018034U)
73 #define REG_TWI0_RPR (*(__IO uint32_t*)0x40018100U)
74 #define REG_TWI0_RCR (*(__IO uint32_t*)0x40018104U)
75 #define REG_TWI0_TPR (*(__IO uint32_t*)0x40018108U)
76 #define REG_TWI0_TCR (*(__IO uint32_t*)0x4001810CU)
77 #define REG_TWI0_RNPR (*(__IO uint32_t*)0x40018110U)
78 #define REG_TWI0_RNCR (*(__IO uint32_t*)0x40018114U)
79 #define REG_TWI0_TNPR (*(__IO uint32_t*)0x40018118U)
80 #define REG_TWI0_TNCR (*(__IO uint32_t*)0x4001811CU)
81 #define REG_TWI0_PTCR (*(__O uint32_t*)0x40018120U)
82 #define REG_TWI0_PTSR (*(__I uint32_t*)0x40018124U)
83#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
84
85#endif /* _SAM4S_TWI0_INSTANCE_ */