Macros
#define	REG_TWI0_CR ((__O uint32_t)0x40018000U)
	(TWI0) Control Register
#define	REG_TWI0_CWGR ((__IO uint32_t)0x40018010U)
	(TWI0) Clock Waveform Generator Register
#define	REG_TWI0_IADR ((__IO uint32_t)0x4001800CU)
	(TWI0) Internal Address Register
#define	REG_TWI0_IDR ((__O uint32_t)0x40018028U)
	(TWI0) Interrupt Disable Register
#define	REG_TWI0_IER ((__O uint32_t)0x40018024U)
	(TWI0) Interrupt Enable Register
#define	REG_TWI0_IMR ((__I uint32_t)0x4001802CU)
	(TWI0) Interrupt Mask Register
#define	REG_TWI0_MMR ((__IO uint32_t)0x40018004U)
	(TWI0) Master Mode Register
#define	REG_TWI0_PTCR ((__O uint32_t)0x40018120U)
	(TWI0) Transfer Control Register
#define	REG_TWI0_PTSR ((__I uint32_t)0x40018124U)
	(TWI0) Transfer Status Register
#define	REG_TWI0_RCR ((__IO uint32_t)0x40018104U)
	(TWI0) Receive Counter Register
#define	REG_TWI0_RHR ((__I uint32_t)0x40018030U)
	(TWI0) Receive Holding Register
#define	REG_TWI0_RNCR ((__IO uint32_t)0x40018114U)
	(TWI0) Receive Next Counter Register
#define	REG_TWI0_RNPR ((__IO uint32_t)0x40018110U)
	(TWI0) Receive Next Pointer Register
#define	REG_TWI0_RPR ((__IO uint32_t)0x40018100U)
	(TWI0) Receive Pointer Register
#define	REG_TWI0_SMR ((__IO uint32_t)0x40018008U)
	(TWI0) Slave Mode Register
#define	REG_TWI0_SR ((__I uint32_t)0x40018020U)
	(TWI0) Status Register
#define	REG_TWI0_TCR ((__IO uint32_t)0x4001810CU)
	(TWI0) Transmit Counter Register
#define	REG_TWI0_THR ((__O uint32_t)0x40018034U)
	(TWI0) Transmit Holding Register
#define	REG_TWI0_TNCR ((__IO uint32_t)0x4001811CU)
	(TWI0) Transmit Next Counter Register
#define	REG_TWI0_TNPR ((__IO uint32_t)0x40018118U)
	(TWI0) Transmit Next Pointer Register
#define	REG_TWI0_TPR ((__IO uint32_t)0x40018108U)
	(TWI0) Transmit Pointer Register

Detailed Description

and its subsidiaries.

\cond ASF_LICENSE

Definition in file instance_twi0.h.

Macro Definition Documentation

◆ REG_TWI0_CR

#define REG_TWI0_CR (*(__O uint32_t*)0x40018000U)

(TWI0) Control Register

Definition at line 62 of file instance_twi0.h.

◆ REG_TWI0_CWGR

#define REG_TWI0_CWGR (*(__IO uint32_t*)0x40018010U)

(TWI0) Clock Waveform Generator Register

Definition at line 66 of file instance_twi0.h.

◆ REG_TWI0_IADR

#define REG_TWI0_IADR (*(__IO uint32_t*)0x4001800CU)

(TWI0) Internal Address Register

Definition at line 65 of file instance_twi0.h.

◆ REG_TWI0_IDR

#define REG_TWI0_IDR (*(__O uint32_t*)0x40018028U)

(TWI0) Interrupt Disable Register

Definition at line 69 of file instance_twi0.h.

◆ REG_TWI0_IER

#define REG_TWI0_IER (*(__O uint32_t*)0x40018024U)

(TWI0) Interrupt Enable Register

Definition at line 68 of file instance_twi0.h.

◆ REG_TWI0_IMR

#define REG_TWI0_IMR (*(__I uint32_t*)0x4001802CU)

(TWI0) Interrupt Mask Register

Definition at line 70 of file instance_twi0.h.

◆ REG_TWI0_MMR

#define REG_TWI0_MMR (*(__IO uint32_t*)0x40018004U)

(TWI0) Master Mode Register

Definition at line 63 of file instance_twi0.h.

◆ REG_TWI0_PTCR

#define REG_TWI0_PTCR (*(__O uint32_t*)0x40018120U)

(TWI0) Transfer Control Register

Definition at line 81 of file instance_twi0.h.

◆ REG_TWI0_PTSR

#define REG_TWI0_PTSR (*(__I uint32_t*)0x40018124U)

(TWI0) Transfer Status Register

Definition at line 82 of file instance_twi0.h.

◆ REG_TWI0_RCR

#define REG_TWI0_RCR (*(__IO uint32_t*)0x40018104U)

(TWI0) Receive Counter Register

Definition at line 74 of file instance_twi0.h.

◆ REG_TWI0_RHR

#define REG_TWI0_RHR (*(__I uint32_t*)0x40018030U)

(TWI0) Receive Holding Register

Definition at line 71 of file instance_twi0.h.

◆ REG_TWI0_RNCR

#define REG_TWI0_RNCR (*(__IO uint32_t*)0x40018114U)

(TWI0) Receive Next Counter Register

Definition at line 78 of file instance_twi0.h.

◆ REG_TWI0_RNPR

#define REG_TWI0_RNPR (*(__IO uint32_t*)0x40018110U)

(TWI0) Receive Next Pointer Register

Definition at line 77 of file instance_twi0.h.

◆ REG_TWI0_RPR

#define REG_TWI0_RPR (*(__IO uint32_t*)0x40018100U)

(TWI0) Receive Pointer Register

Definition at line 73 of file instance_twi0.h.

◆ REG_TWI0_SMR

#define REG_TWI0_SMR (*(__IO uint32_t*)0x40018008U)

(TWI0) Slave Mode Register

Definition at line 64 of file instance_twi0.h.

◆ REG_TWI0_SR

#define REG_TWI0_SR (*(__I uint32_t*)0x40018020U)

(TWI0) Status Register

Definition at line 67 of file instance_twi0.h.

◆ REG_TWI0_TCR

#define REG_TWI0_TCR (*(__IO uint32_t*)0x4001810CU)

(TWI0) Transmit Counter Register

Definition at line 76 of file instance_twi0.h.

◆ REG_TWI0_THR

#define REG_TWI0_THR (*(__O uint32_t*)0x40018034U)

(TWI0) Transmit Holding Register

Definition at line 72 of file instance_twi0.h.

◆ REG_TWI0_TNCR

#define REG_TWI0_TNCR (*(__IO uint32_t*)0x4001811CU)

(TWI0) Transmit Next Counter Register

Definition at line 80 of file instance_twi0.h.

◆ REG_TWI0_TNPR

#define REG_TWI0_TNPR (*(__IO uint32_t*)0x40018118U)

(TWI0) Transmit Next Pointer Register

Definition at line 79 of file instance_twi0.h.

◆ REG_TWI0_TPR

#define REG_TWI0_TPR (*(__IO uint32_t*)0x40018108U)

(TWI0) Transmit Pointer Register

Definition at line 75 of file instance_twi0.h.

Macros