instance_twi1.h

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/*
 * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
 */
 
#ifndef _SAM4S_TWI1_INSTANCE_
#define _SAM4S_TWI1_INSTANCE_
 
/* ========== Register definition for TWI1 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
  #define REG_TWI1_CR                    (0x4001C000U) 
  #define REG_TWI1_MMR                   (0x4001C004U) 
  #define REG_TWI1_SMR                   (0x4001C008U) 
  #define REG_TWI1_IADR                  (0x4001C00CU) 
  #define REG_TWI1_CWGR                  (0x4001C010U) 
  #define REG_TWI1_SR                    (0x4001C020U) 
  #define REG_TWI1_IER                   (0x4001C024U) 
  #define REG_TWI1_IDR                   (0x4001C028U) 
  #define REG_TWI1_IMR                   (0x4001C02CU) 
  #define REG_TWI1_RHR                   (0x4001C030U) 
  #define REG_TWI1_THR                   (0x4001C034U) 
  #define REG_TWI1_RPR                   (0x4001C100U) 
  #define REG_TWI1_RCR                   (0x4001C104U) 
  #define REG_TWI1_TPR                   (0x4001C108U) 
  #define REG_TWI1_TCR                   (0x4001C10CU) 
  #define REG_TWI1_RNPR                  (0x4001C110U) 
  #define REG_TWI1_RNCR                  (0x4001C114U) 
  #define REG_TWI1_TNPR                  (0x4001C118U) 
  #define REG_TWI1_TNCR                  (0x4001C11CU) 
  #define REG_TWI1_PTCR                  (0x4001C120U) 
  #define REG_TWI1_PTSR                  (0x4001C124U) 
#else
  #define REG_TWI1_CR   (*(__O  uint32_t*)0x4001C000U) 
  #define REG_TWI1_MMR  (*(__IO uint32_t*)0x4001C004U) 
  #define REG_TWI1_SMR  (*(__IO uint32_t*)0x4001C008U) 
  #define REG_TWI1_IADR (*(__IO uint32_t*)0x4001C00CU) 
  #define REG_TWI1_CWGR (*(__IO uint32_t*)0x4001C010U) 
  #define REG_TWI1_SR   (*(__I  uint32_t*)0x4001C020U) 
  #define REG_TWI1_IER  (*(__O  uint32_t*)0x4001C024U) 
  #define REG_TWI1_IDR  (*(__O  uint32_t*)0x4001C028U) 
  #define REG_TWI1_IMR  (*(__I  uint32_t*)0x4001C02CU) 
  #define REG_TWI1_RHR  (*(__I  uint32_t*)0x4001C030U) 
  #define REG_TWI1_THR  (*(__O  uint32_t*)0x4001C034U) 
  #define REG_TWI1_RPR  (*(__IO uint32_t*)0x4001C100U) 
  #define REG_TWI1_RCR  (*(__IO uint32_t*)0x4001C104U) 
  #define REG_TWI1_TPR  (*(__IO uint32_t*)0x4001C108U) 
  #define REG_TWI1_TCR  (*(__IO uint32_t*)0x4001C10CU) 
  #define REG_TWI1_RNPR (*(__IO uint32_t*)0x4001C110U) 
  #define REG_TWI1_RNCR (*(__IO uint32_t*)0x4001C114U) 
  #define REG_TWI1_TNPR (*(__IO uint32_t*)0x4001C118U) 
  #define REG_TWI1_TNCR (*(__IO uint32_t*)0x4001C11CU) 
  #define REG_TWI1_PTCR (*(__O  uint32_t*)0x4001C120U) 
  #define REG_TWI1_PTSR (*(__I  uint32_t*)0x4001C124U) 
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
#endif /* _SAM4S_TWI1_INSTANCE_ */