Macros
#define	REG_TWI1_CR ((__O uint32_t)0x4001C000U)
	(TWI1) Control Register
#define	REG_TWI1_CWGR ((__IO uint32_t)0x4001C010U)
	(TWI1) Clock Waveform Generator Register
#define	REG_TWI1_IADR ((__IO uint32_t)0x4001C00CU)
	(TWI1) Internal Address Register
#define	REG_TWI1_IDR ((__O uint32_t)0x4001C028U)
	(TWI1) Interrupt Disable Register
#define	REG_TWI1_IER ((__O uint32_t)0x4001C024U)
	(TWI1) Interrupt Enable Register
#define	REG_TWI1_IMR ((__I uint32_t)0x4001C02CU)
	(TWI1) Interrupt Mask Register
#define	REG_TWI1_MMR ((__IO uint32_t)0x4001C004U)
	(TWI1) Master Mode Register
#define	REG_TWI1_PTCR ((__O uint32_t)0x4001C120U)
	(TWI1) Transfer Control Register
#define	REG_TWI1_PTSR ((__I uint32_t)0x4001C124U)
	(TWI1) Transfer Status Register
#define	REG_TWI1_RCR ((__IO uint32_t)0x4001C104U)
	(TWI1) Receive Counter Register
#define	REG_TWI1_RHR ((__I uint32_t)0x4001C030U)
	(TWI1) Receive Holding Register
#define	REG_TWI1_RNCR ((__IO uint32_t)0x4001C114U)
	(TWI1) Receive Next Counter Register
#define	REG_TWI1_RNPR ((__IO uint32_t)0x4001C110U)
	(TWI1) Receive Next Pointer Register
#define	REG_TWI1_RPR ((__IO uint32_t)0x4001C100U)
	(TWI1) Receive Pointer Register
#define	REG_TWI1_SMR ((__IO uint32_t)0x4001C008U)
	(TWI1) Slave Mode Register
#define	REG_TWI1_SR ((__I uint32_t)0x4001C020U)
	(TWI1) Status Register
#define	REG_TWI1_TCR ((__IO uint32_t)0x4001C10CU)
	(TWI1) Transmit Counter Register
#define	REG_TWI1_THR ((__O uint32_t)0x4001C034U)
	(TWI1) Transmit Holding Register
#define	REG_TWI1_TNCR ((__IO uint32_t)0x4001C11CU)
	(TWI1) Transmit Next Counter Register
#define	REG_TWI1_TNPR ((__IO uint32_t)0x4001C118U)
	(TWI1) Transmit Next Pointer Register
#define	REG_TWI1_TPR ((__IO uint32_t)0x4001C108U)
	(TWI1) Transmit Pointer Register

Detailed Description

and its subsidiaries.

\cond ASF_LICENSE

Definition in file instance_twi1.h.

Macro Definition Documentation

◆ REG_TWI1_CR

#define REG_TWI1_CR (*(__O uint32_t*)0x4001C000U)

(TWI1) Control Register

Definition at line 62 of file instance_twi1.h.

◆ REG_TWI1_CWGR

#define REG_TWI1_CWGR (*(__IO uint32_t*)0x4001C010U)

(TWI1) Clock Waveform Generator Register

Definition at line 66 of file instance_twi1.h.

◆ REG_TWI1_IADR

#define REG_TWI1_IADR (*(__IO uint32_t*)0x4001C00CU)

(TWI1) Internal Address Register

Definition at line 65 of file instance_twi1.h.

◆ REG_TWI1_IDR

#define REG_TWI1_IDR (*(__O uint32_t*)0x4001C028U)

(TWI1) Interrupt Disable Register

Definition at line 69 of file instance_twi1.h.

◆ REG_TWI1_IER

#define REG_TWI1_IER (*(__O uint32_t*)0x4001C024U)

(TWI1) Interrupt Enable Register

Definition at line 68 of file instance_twi1.h.

◆ REG_TWI1_IMR

#define REG_TWI1_IMR (*(__I uint32_t*)0x4001C02CU)

(TWI1) Interrupt Mask Register

Definition at line 70 of file instance_twi1.h.

◆ REG_TWI1_MMR

#define REG_TWI1_MMR (*(__IO uint32_t*)0x4001C004U)

(TWI1) Master Mode Register

Definition at line 63 of file instance_twi1.h.

◆ REG_TWI1_PTCR

#define REG_TWI1_PTCR (*(__O uint32_t*)0x4001C120U)

(TWI1) Transfer Control Register

Definition at line 81 of file instance_twi1.h.

◆ REG_TWI1_PTSR

#define REG_TWI1_PTSR (*(__I uint32_t*)0x4001C124U)

(TWI1) Transfer Status Register

Definition at line 82 of file instance_twi1.h.

◆ REG_TWI1_RCR

#define REG_TWI1_RCR (*(__IO uint32_t*)0x4001C104U)

(TWI1) Receive Counter Register

Definition at line 74 of file instance_twi1.h.

◆ REG_TWI1_RHR

#define REG_TWI1_RHR (*(__I uint32_t*)0x4001C030U)

(TWI1) Receive Holding Register

Definition at line 71 of file instance_twi1.h.

◆ REG_TWI1_RNCR

#define REG_TWI1_RNCR (*(__IO uint32_t*)0x4001C114U)

(TWI1) Receive Next Counter Register

Definition at line 78 of file instance_twi1.h.

◆ REG_TWI1_RNPR

#define REG_TWI1_RNPR (*(__IO uint32_t*)0x4001C110U)

(TWI1) Receive Next Pointer Register

Definition at line 77 of file instance_twi1.h.

◆ REG_TWI1_RPR

#define REG_TWI1_RPR (*(__IO uint32_t*)0x4001C100U)

(TWI1) Receive Pointer Register

Definition at line 73 of file instance_twi1.h.

◆ REG_TWI1_SMR

#define REG_TWI1_SMR (*(__IO uint32_t*)0x4001C008U)

(TWI1) Slave Mode Register

Definition at line 64 of file instance_twi1.h.

◆ REG_TWI1_SR

#define REG_TWI1_SR (*(__I uint32_t*)0x4001C020U)

(TWI1) Status Register

Definition at line 67 of file instance_twi1.h.

◆ REG_TWI1_TCR

#define REG_TWI1_TCR (*(__IO uint32_t*)0x4001C10CU)

(TWI1) Transmit Counter Register

Definition at line 76 of file instance_twi1.h.

◆ REG_TWI1_THR

#define REG_TWI1_THR (*(__O uint32_t*)0x4001C034U)

(TWI1) Transmit Holding Register

Definition at line 72 of file instance_twi1.h.

◆ REG_TWI1_TNCR

#define REG_TWI1_TNCR (*(__IO uint32_t*)0x4001C11CU)

(TWI1) Transmit Next Counter Register

Definition at line 80 of file instance_twi1.h.

◆ REG_TWI1_TNPR

#define REG_TWI1_TNPR (*(__IO uint32_t*)0x4001C118U)

(TWI1) Transmit Next Pointer Register

Definition at line 79 of file instance_twi1.h.

◆ REG_TWI1_TPR

#define REG_TWI1_TPR (*(__IO uint32_t*)0x4001C108U)

(TWI1) Transmit Pointer Register

Definition at line 75 of file instance_twi1.h.

Macros