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SAM4SD32 (SAM4S-EK2)
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Usart hardware registers. More...
#include <component_usart.h>
Data Fields | |
| __I uint32_t | Reserved1 [5] |
| __I uint32_t | Reserved2 [1] |
| __I uint32_t | Reserved3 [36] |
| __I uint32_t | Reserved4 [4] |
| __IO uint32_t | US_BRGR |
| (Usart Offset: 0x0020) Baud Rate Generator Register | |
| __O uint32_t | US_CR |
| (Usart Offset: 0x0000) Control Register | |
| __I uint32_t | US_CSR |
| (Usart Offset: 0x0014) Channel Status Register | |
| __IO uint32_t | US_FIDI |
| (Usart Offset: 0x0040) FI DI Ratio Register | |
| __O uint32_t | US_IDR |
| (Usart Offset: 0x000C) Interrupt Disable Register | |
| __O uint32_t | US_IER |
| (Usart Offset: 0x0008) Interrupt Enable Register | |
| __IO uint32_t | US_IF |
| (Usart Offset: 0x004C) IrDA Filter Register | |
| __I uint32_t | US_IMR |
| (Usart Offset: 0x0010) Interrupt Mask Register | |
| __IO uint32_t | US_MAN |
| (Usart Offset: 0x0050) Manchester Encoder Decoder Register | |
| __IO uint32_t | US_MR |
| (Usart Offset: 0x0004) Mode Register | |
| __I uint32_t | US_NER |
| (Usart Offset: 0x0044) Number of Errors Register | |
| __O uint32_t | US_PTCR |
| (Usart Offset: 0x120) Transfer Control Register | |
| __I uint32_t | US_PTSR |
| (Usart Offset: 0x124) Transfer Status Register | |
| __IO uint32_t | US_RCR |
| (Usart Offset: 0x104) Receive Counter Register | |
| __I uint32_t | US_RHR |
| (Usart Offset: 0x0018) Receiver Holding Register | |
| __IO uint32_t | US_RNCR |
| (Usart Offset: 0x114) Receive Next Counter Register | |
| __IO uint32_t | US_RNPR |
| (Usart Offset: 0x110) Receive Next Pointer Register | |
| __IO uint32_t | US_RPR |
| (Usart Offset: 0x100) Receive Pointer Register | |
| __IO uint32_t | US_RTOR |
| (Usart Offset: 0x0024) Receiver Time-out Register | |
| __IO uint32_t | US_TCR |
| (Usart Offset: 0x10C) Transmit Counter Register | |
| __O uint32_t | US_THR |
| (Usart Offset: 0x001C) Transmitter Holding Register | |
| __IO uint32_t | US_TNCR |
| (Usart Offset: 0x11C) Transmit Next Counter Register | |
| __IO uint32_t | US_TNPR |
| (Usart Offset: 0x118) Transmit Next Pointer Register | |
| __IO uint32_t | US_TPR |
| (Usart Offset: 0x108) Transmit Pointer Register | |
| __IO uint32_t | US_TTGR |
| (Usart Offset: 0x0028) Transmitter Timeguard Register | |
| __I uint32_t | US_VERSION |
| (Usart Offset: 0x00FC) Version Register | |
| __IO uint32_t | US_WPMR |
| (Usart Offset: 0x00E4) Write Protect Mode Register | |
| __I uint32_t | US_WPSR |
| (Usart Offset: 0x00E8) Write Protect Status Register | |
Usart hardware registers.
Definition at line 46 of file component_usart.h.
| __I uint32_t Usart::Reserved1[5] |
Definition at line 58 of file component_usart.h.
| __I uint32_t Usart::Reserved2[1] |
Definition at line 61 of file component_usart.h.
| __I uint32_t Usart::Reserved3[36] |
Definition at line 64 of file component_usart.h.
| __I uint32_t Usart::Reserved4[4] |
Definition at line 67 of file component_usart.h.
| __IO uint32_t Usart::US_BRGR |
(Usart Offset: 0x0020) Baud Rate Generator Register
Definition at line 55 of file component_usart.h.
Referenced by usart_set_async_baudrate(), usart_set_iso7816_clock(), usart_set_spi_master_baudrate(), and usart_set_sync_master_baudrate().
| __O uint32_t Usart::US_CR |
(Usart Offset: 0x0000) Control Register
Definition at line 47 of file component_usart.h.
Referenced by usart_disable_rx(), usart_disable_tx(), usart_drive_DTR_pin_high(), usart_drive_DTR_pin_low(), usart_drive_RTS_pin_high(), usart_drive_RTS_pin_low(), usart_enable_rx(), usart_enable_tx(), usart_reset_iterations(), usart_reset_nack(), usart_reset_rx(), usart_reset_status(), usart_reset_tx(), usart_restart_rx_timeout(), usart_send_address(), usart_spi_force_chip_select(), usart_spi_release_chip_select(), usart_start_rx_timeout(), usart_start_tx_break(), and usart_stop_tx_break().
| __I uint32_t Usart::US_CSR |
(Usart Offset: 0x0014) Channel Status Register
Definition at line 52 of file component_usart.h.
Referenced by usart_get_status(), usart_getchar(), usart_is_rx_buf_end(), usart_is_rx_buf_full(), usart_is_rx_ready(), usart_is_tx_buf_empty(), usart_is_tx_buf_end(), usart_is_tx_empty(), usart_is_tx_ready(), usart_putchar(), usart_read(), and usart_write().
| __IO uint32_t Usart::US_FIDI |
(Usart Offset: 0x0040) FI DI Ratio Register
Definition at line 59 of file component_usart.h.
Referenced by usart_init_iso7816().
| __O uint32_t Usart::US_IDR |
(Usart Offset: 0x000C) Interrupt Disable Register
Definition at line 50 of file component_usart.h.
Referenced by usart_disable_interrupt().
| __O uint32_t Usart::US_IER |
(Usart Offset: 0x0008) Interrupt Enable Register
Definition at line 49 of file component_usart.h.
Referenced by usart_enable_interrupt().
| __IO uint32_t Usart::US_IF |
(Usart Offset: 0x004C) IrDA Filter Register
Definition at line 62 of file component_usart.h.
Referenced by usart_init_irda().
| __I uint32_t Usart::US_IMR |
(Usart Offset: 0x0010) Interrupt Mask Register
Definition at line 51 of file component_usart.h.
Referenced by usart_get_interrupt_mask().
| __IO uint32_t Usart::US_MAN |
(Usart Offset: 0x0050) Manchester Encoder Decoder Register
Definition at line 63 of file component_usart.h.
Referenced by usart_man_disable_drift_compensation(), usart_man_enable_drift_compensation(), usart_man_set_rx_polarity(), usart_man_set_rx_pre_len(), usart_man_set_rx_pre_pattern(), usart_man_set_tx_polarity(), usart_man_set_tx_pre_len(), and usart_man_set_tx_pre_pattern().
| __IO uint32_t Usart::US_MR |
(Usart Offset: 0x0004) Mode Register
Definition at line 48 of file component_usart.h.
Referenced by usart_init_hw_handshaking(), usart_init_irda(), usart_init_iso7816(), usart_init_modem(), usart_init_rs232(), usart_init_rs485(), usart_init_spi_master(), usart_init_spi_slave(), usart_init_sync_master(), usart_init_sync_slave(), usart_reset(), usart_send_address(), usart_set_async_baudrate(), usart_set_iso7816_clock(), usart_set_spi_slave_baudrate(), usart_set_sync_master_baudrate(), and usart_set_sync_slave_baudrate().
| __I uint32_t Usart::US_NER |
(Usart Offset: 0x0044) Number of Errors Register
Definition at line 60 of file component_usart.h.
Referenced by usart_get_error_number().
| __O uint32_t Usart::US_PTCR |
(Usart Offset: 0x120) Transfer Control Register
Definition at line 77 of file component_usart.h.
| __I uint32_t Usart::US_PTSR |
(Usart Offset: 0x124) Transfer Status Register
Definition at line 78 of file component_usart.h.
| __IO uint32_t Usart::US_RCR |
(Usart Offset: 0x104) Receive Counter Register
Definition at line 70 of file component_usart.h.
| __I uint32_t Usart::US_RHR |
(Usart Offset: 0x0018) Receiver Holding Register
Definition at line 53 of file component_usart.h.
Referenced by usart_getchar(), and usart_read().
| __IO uint32_t Usart::US_RNCR |
(Usart Offset: 0x114) Receive Next Counter Register
Definition at line 74 of file component_usart.h.
| __IO uint32_t Usart::US_RNPR |
(Usart Offset: 0x110) Receive Next Pointer Register
Definition at line 73 of file component_usart.h.
| __IO uint32_t Usart::US_RPR |
(Usart Offset: 0x100) Receive Pointer Register
Definition at line 69 of file component_usart.h.
| __IO uint32_t Usart::US_RTOR |
(Usart Offset: 0x0024) Receiver Time-out Register
Definition at line 56 of file component_usart.h.
Referenced by usart_reset(), and usart_set_rx_timeout().
| __IO uint32_t Usart::US_TCR |
(Usart Offset: 0x10C) Transmit Counter Register
Definition at line 72 of file component_usart.h.
| __O uint32_t Usart::US_THR |
(Usart Offset: 0x001C) Transmitter Holding Register
Definition at line 54 of file component_usart.h.
Referenced by usart_putchar(), and usart_write().
| __IO uint32_t Usart::US_TNCR |
(Usart Offset: 0x11C) Transmit Next Counter Register
Definition at line 76 of file component_usart.h.
| __IO uint32_t Usart::US_TNPR |
(Usart Offset: 0x118) Transmit Next Pointer Register
Definition at line 75 of file component_usart.h.
| __IO uint32_t Usart::US_TPR |
(Usart Offset: 0x108) Transmit Pointer Register
Definition at line 71 of file component_usart.h.
| __IO uint32_t Usart::US_TTGR |
(Usart Offset: 0x0028) Transmitter Timeguard Register
Definition at line 57 of file component_usart.h.
Referenced by usart_reset(), and usart_set_tx_timeguard().
| __I uint32_t Usart::US_VERSION |
(Usart Offset: 0x00FC) Version Register
Definition at line 68 of file component_usart.h.
| __IO uint32_t Usart::US_WPMR |
(Usart Offset: 0x00E4) Write Protect Mode Register
Definition at line 65 of file component_usart.h.
Referenced by usart_disable_writeprotect(), and usart_enable_writeprotect().
| __I uint32_t Usart::US_WPSR |
(Usart Offset: 0x00E8) Write Protect Status Register
Definition at line 66 of file component_usart.h.
Referenced by usart_get_writeprotect_status().