SAM4SD32-SAM4S-EK2-IMT-Docs/html/component__adc_8h_source.html

/*

 * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>

 */


#ifndef _SAM4S_ADC_COMPONENT_

#define _SAM4S_ADC_COMPONENT_


/* ============================================================================= */

/* ============================================================================= */


#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))


typedef struct {

  __O  uint32_t ADC_CR;

  __IO uint32_t ADC_MR;

  __IO uint32_t ADC_SEQR1;

  __IO uint32_t ADC_SEQR2;

  __O  uint32_t ADC_CHER;

  __O  uint32_t ADC_CHDR;

  __I  uint32_t ADC_CHSR;

  __I  uint32_t Reserved1[1];

  __I  uint32_t ADC_LCDR;

  __O  uint32_t ADC_IER;

  __O  uint32_t ADC_IDR;

  __I  uint32_t ADC_IMR;

  __I  uint32_t ADC_ISR;

  __I  uint32_t Reserved2[2];

  __I  uint32_t ADC_OVER;

  __IO uint32_t ADC_EMR;

  __IO uint32_t ADC_CWR;

  __IO uint32_t ADC_CGR;

  __IO uint32_t ADC_COR;

  __I  uint32_t ADC_CDR[16];

  __I  uint32_t Reserved3[1];

  __IO uint32_t ADC_ACR;

  __I  uint32_t Reserved4[19];

  __IO uint32_t ADC_WPMR;

  __I  uint32_t ADC_WPSR;

  __I  uint32_t Reserved5[5];

  __IO uint32_t ADC_RPR;

  __IO uint32_t ADC_RCR;

  __I  uint32_t Reserved6[2];

  __IO uint32_t ADC_RNPR;

  __IO uint32_t ADC_RNCR;

  __I  uint32_t Reserved7[2];

  __O  uint32_t ADC_PTCR;

  __I  uint32_t ADC_PTSR;

} Adc;


#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

/* -------- ADC_CR : (ADC Offset: 0x00) Control Register -------- */

#define ADC_CR_SWRST (0x1u << 0)

#define ADC_CR_START (0x1u << 1)

#define ADC_CR_AUTOCAL (0x1u << 3)

/* -------- ADC_MR : (ADC Offset: 0x04) Mode Register -------- */

#define ADC_MR_TRGEN (0x1u << 0)

#define   ADC_MR_TRGEN_DIS (0x0u << 0)

#define   ADC_MR_TRGEN_EN (0x1u << 0)

#define ADC_MR_TRGSEL_Pos 1

#define ADC_MR_TRGSEL_Msk (0x7u << ADC_MR_TRGSEL_Pos)

#define   ADC_MR_TRGSEL_ADC_TRIG0 (0x0u << 1)

#define   ADC_MR_TRGSEL_ADC_TRIG1 (0x1u << 1)

#define   ADC_MR_TRGSEL_ADC_TRIG2 (0x2u << 1)

#define   ADC_MR_TRGSEL_ADC_TRIG3 (0x3u << 1)

#define   ADC_MR_TRGSEL_ADC_TRIG4 (0x4u << 1)

#define   ADC_MR_TRGSEL_ADC_TRIG5 (0x5u << 1)

#define ADC_MR_LOWRES (0x1u << 4)

#define   ADC_MR_LOWRES_BITS_12 (0x0u << 4)

#define   ADC_MR_LOWRES_BITS_10 (0x1u << 4)

#define ADC_MR_SLEEP (0x1u << 5)

#define   ADC_MR_SLEEP_NORMAL (0x0u << 5)

#define   ADC_MR_SLEEP_SLEEP (0x1u << 5)

#define ADC_MR_FWUP (0x1u << 6)

#define   ADC_MR_FWUP_OFF (0x0u << 6)

#define   ADC_MR_FWUP_ON (0x1u << 6)

#define ADC_MR_FREERUN (0x1u << 7)

#define   ADC_MR_FREERUN_OFF (0x0u << 7)

#define   ADC_MR_FREERUN_ON (0x1u << 7)

#define ADC_MR_PRESCAL_Pos 8

#define ADC_MR_PRESCAL_Msk (0xffu << ADC_MR_PRESCAL_Pos)

#define ADC_MR_PRESCAL(value) ((ADC_MR_PRESCAL_Msk & ((value) << ADC_MR_PRESCAL_Pos)))

#define ADC_MR_STARTUP_Pos 16

#define ADC_MR_STARTUP_Msk (0xfu << ADC_MR_STARTUP_Pos)

#define   ADC_MR_STARTUP_SUT0 (0x0u << 16)

#define   ADC_MR_STARTUP_SUT8 (0x1u << 16)

#define   ADC_MR_STARTUP_SUT16 (0x2u << 16)

#define   ADC_MR_STARTUP_SUT24 (0x3u << 16)

#define   ADC_MR_STARTUP_SUT64 (0x4u << 16)

#define   ADC_MR_STARTUP_SUT80 (0x5u << 16)

#define   ADC_MR_STARTUP_SUT96 (0x6u << 16)

#define   ADC_MR_STARTUP_SUT112 (0x7u << 16)

#define   ADC_MR_STARTUP_SUT512 (0x8u << 16)

#define   ADC_MR_STARTUP_SUT576 (0x9u << 16)

#define   ADC_MR_STARTUP_SUT640 (0xAu << 16)

#define   ADC_MR_STARTUP_SUT704 (0xBu << 16)

#define   ADC_MR_STARTUP_SUT768 (0xCu << 16)

#define   ADC_MR_STARTUP_SUT832 (0xDu << 16)

#define   ADC_MR_STARTUP_SUT896 (0xEu << 16)

#define   ADC_MR_STARTUP_SUT960 (0xFu << 16)

#define ADC_MR_SETTLING_Pos 20

#define ADC_MR_SETTLING_Msk (0x3u << ADC_MR_SETTLING_Pos)

#define   ADC_MR_SETTLING_AST3 (0x0u << 20)

#define   ADC_MR_SETTLING_AST5 (0x1u << 20)

#define   ADC_MR_SETTLING_AST9 (0x2u << 20)

#define   ADC_MR_SETTLING_AST17 (0x3u << 20)

#define ADC_MR_ANACH (0x1u << 23)

#define   ADC_MR_ANACH_NONE (0x0u << 23)

#define   ADC_MR_ANACH_ALLOWED (0x1u << 23)

#define ADC_MR_TRACKTIM_Pos 24

#define ADC_MR_TRACKTIM_Msk (0xfu << ADC_MR_TRACKTIM_Pos)

#define ADC_MR_TRACKTIM(value) ((ADC_MR_TRACKTIM_Msk & ((value) << ADC_MR_TRACKTIM_Pos)))

#define ADC_MR_TRANSFER_Pos 28

#define ADC_MR_TRANSFER_Msk (0x3u << ADC_MR_TRANSFER_Pos)

#define ADC_MR_TRANSFER(value) ((ADC_MR_TRANSFER_Msk & ((value) << ADC_MR_TRANSFER_Pos)))

#define ADC_MR_USEQ (0x1u << 31)

#define   ADC_MR_USEQ_NUM_ORDER (0x0u << 31)

#define   ADC_MR_USEQ_REG_ORDER (0x1u << 31)

/* -------- ADC_SEQR1 : (ADC Offset: 0x08) Channel Sequence Register 1 -------- */

#define ADC_SEQR1_USCH1_Pos 0

#define ADC_SEQR1_USCH1_Msk (0xfu << ADC_SEQR1_USCH1_Pos)

#define ADC_SEQR1_USCH1(value) ((ADC_SEQR1_USCH1_Msk & ((value) << ADC_SEQR1_USCH1_Pos)))

#define ADC_SEQR1_USCH2_Pos 4

#define ADC_SEQR1_USCH2_Msk (0xfu << ADC_SEQR1_USCH2_Pos)

#define ADC_SEQR1_USCH2(value) ((ADC_SEQR1_USCH2_Msk & ((value) << ADC_SEQR1_USCH2_Pos)))

#define ADC_SEQR1_USCH3_Pos 8

#define ADC_SEQR1_USCH3_Msk (0xfu << ADC_SEQR1_USCH3_Pos)

#define ADC_SEQR1_USCH3(value) ((ADC_SEQR1_USCH3_Msk & ((value) << ADC_SEQR1_USCH3_Pos)))

#define ADC_SEQR1_USCH4_Pos 12

#define ADC_SEQR1_USCH4_Msk (0xfu << ADC_SEQR1_USCH4_Pos)

#define ADC_SEQR1_USCH4(value) ((ADC_SEQR1_USCH4_Msk & ((value) << ADC_SEQR1_USCH4_Pos)))

#define ADC_SEQR1_USCH5_Pos 16

#define ADC_SEQR1_USCH5_Msk (0xfu << ADC_SEQR1_USCH5_Pos)

#define ADC_SEQR1_USCH5(value) ((ADC_SEQR1_USCH5_Msk & ((value) << ADC_SEQR1_USCH5_Pos)))

#define ADC_SEQR1_USCH6_Pos 20

#define ADC_SEQR1_USCH6_Msk (0xfu << ADC_SEQR1_USCH6_Pos)

#define ADC_SEQR1_USCH6(value) ((ADC_SEQR1_USCH6_Msk & ((value) << ADC_SEQR1_USCH6_Pos)))

#define ADC_SEQR1_USCH7_Pos 24

#define ADC_SEQR1_USCH7_Msk (0xfu << ADC_SEQR1_USCH7_Pos)

#define ADC_SEQR1_USCH7(value) ((ADC_SEQR1_USCH7_Msk & ((value) << ADC_SEQR1_USCH7_Pos)))

#define ADC_SEQR1_USCH8_Pos 28

#define ADC_SEQR1_USCH8_Msk (0xfu << ADC_SEQR1_USCH8_Pos)

#define ADC_SEQR1_USCH8(value) ((ADC_SEQR1_USCH8_Msk & ((value) << ADC_SEQR1_USCH8_Pos)))

/* -------- ADC_SEQR2 : (ADC Offset: 0x0C) Channel Sequence Register 2 -------- */

#define ADC_SEQR2_USCH9_Pos 0

#define ADC_SEQR2_USCH9_Msk (0xfu << ADC_SEQR2_USCH9_Pos)

#define ADC_SEQR2_USCH9(value) ((ADC_SEQR2_USCH9_Msk & ((value) << ADC_SEQR2_USCH9_Pos)))

#define ADC_SEQR2_USCH10_Pos 4

#define ADC_SEQR2_USCH10_Msk (0xfu << ADC_SEQR2_USCH10_Pos)

#define ADC_SEQR2_USCH10(value) ((ADC_SEQR2_USCH10_Msk & ((value) << ADC_SEQR2_USCH10_Pos)))

#define ADC_SEQR2_USCH11_Pos 8

#define ADC_SEQR2_USCH11_Msk (0xfu << ADC_SEQR2_USCH11_Pos)

#define ADC_SEQR2_USCH11(value) ((ADC_SEQR2_USCH11_Msk & ((value) << ADC_SEQR2_USCH11_Pos)))

#define ADC_SEQR2_USCH12_Pos 12

#define ADC_SEQR2_USCH12_Msk (0xfu << ADC_SEQR2_USCH12_Pos)

#define ADC_SEQR2_USCH12(value) ((ADC_SEQR2_USCH12_Msk & ((value) << ADC_SEQR2_USCH12_Pos)))

#define ADC_SEQR2_USCH13_Pos 16

#define ADC_SEQR2_USCH13_Msk (0xfu << ADC_SEQR2_USCH13_Pos)

#define ADC_SEQR2_USCH13(value) ((ADC_SEQR2_USCH13_Msk & ((value) << ADC_SEQR2_USCH13_Pos)))

#define ADC_SEQR2_USCH14_Pos 20

#define ADC_SEQR2_USCH14_Msk (0xfu << ADC_SEQR2_USCH14_Pos)

#define ADC_SEQR2_USCH14(value) ((ADC_SEQR2_USCH14_Msk & ((value) << ADC_SEQR2_USCH14_Pos)))

#define ADC_SEQR2_USCH15_Pos 24

#define ADC_SEQR2_USCH15_Msk (0xfu << ADC_SEQR2_USCH15_Pos)

#define ADC_SEQR2_USCH15(value) ((ADC_SEQR2_USCH15_Msk & ((value) << ADC_SEQR2_USCH15_Pos)))

/* -------- ADC_CHER : (ADC Offset: 0x10) Channel Enable Register -------- */

#define ADC_CHER_CH0 (0x1u << 0)

#define ADC_CHER_CH1 (0x1u << 1)

#define ADC_CHER_CH2 (0x1u << 2)

#define ADC_CHER_CH3 (0x1u << 3)

#define ADC_CHER_CH4 (0x1u << 4)

#define ADC_CHER_CH5 (0x1u << 5)

#define ADC_CHER_CH6 (0x1u << 6)

#define ADC_CHER_CH7 (0x1u << 7)

#define ADC_CHER_CH8 (0x1u << 8)

#define ADC_CHER_CH9 (0x1u << 9)

#define ADC_CHER_CH10 (0x1u << 10)

#define ADC_CHER_CH11 (0x1u << 11)

#define ADC_CHER_CH12 (0x1u << 12)

#define ADC_CHER_CH13 (0x1u << 13)

#define ADC_CHER_CH14 (0x1u << 14)

#define ADC_CHER_CH15 (0x1u << 15)

/* -------- ADC_CHDR : (ADC Offset: 0x14) Channel Disable Register -------- */

#define ADC_CHDR_CH0 (0x1u << 0)

#define ADC_CHDR_CH1 (0x1u << 1)

#define ADC_CHDR_CH2 (0x1u << 2)

#define ADC_CHDR_CH3 (0x1u << 3)

#define ADC_CHDR_CH4 (0x1u << 4)

#define ADC_CHDR_CH5 (0x1u << 5)

#define ADC_CHDR_CH6 (0x1u << 6)

#define ADC_CHDR_CH7 (0x1u << 7)

#define ADC_CHDR_CH8 (0x1u << 8)

#define ADC_CHDR_CH9 (0x1u << 9)

#define ADC_CHDR_CH10 (0x1u << 10)

#define ADC_CHDR_CH11 (0x1u << 11)

#define ADC_CHDR_CH12 (0x1u << 12)

#define ADC_CHDR_CH13 (0x1u << 13)

#define ADC_CHDR_CH14 (0x1u << 14)

#define ADC_CHDR_CH15 (0x1u << 15)

/* -------- ADC_CHSR : (ADC Offset: 0x18) Channel Status Register -------- */

#define ADC_CHSR_CH0 (0x1u << 0)

#define ADC_CHSR_CH1 (0x1u << 1)

#define ADC_CHSR_CH2 (0x1u << 2)

#define ADC_CHSR_CH3 (0x1u << 3)

#define ADC_CHSR_CH4 (0x1u << 4)

#define ADC_CHSR_CH5 (0x1u << 5)

#define ADC_CHSR_CH6 (0x1u << 6)

#define ADC_CHSR_CH7 (0x1u << 7)

#define ADC_CHSR_CH8 (0x1u << 8)

#define ADC_CHSR_CH9 (0x1u << 9)

#define ADC_CHSR_CH10 (0x1u << 10)

#define ADC_CHSR_CH11 (0x1u << 11)

#define ADC_CHSR_CH12 (0x1u << 12)

#define ADC_CHSR_CH13 (0x1u << 13)

#define ADC_CHSR_CH14 (0x1u << 14)

#define ADC_CHSR_CH15 (0x1u << 15)

/* -------- ADC_LCDR : (ADC Offset: 0x20) Last Converted Data Register -------- */

#define ADC_LCDR_LDATA_Pos 0

#define ADC_LCDR_LDATA_Msk (0xfffu << ADC_LCDR_LDATA_Pos)

#define ADC_LCDR_CHNB_Pos 12

#define ADC_LCDR_CHNB_Msk (0xfu << ADC_LCDR_CHNB_Pos)

/* -------- ADC_IER : (ADC Offset: 0x24) Interrupt Enable Register -------- */

#define ADC_IER_EOC0 (0x1u << 0)

#define ADC_IER_EOC1 (0x1u << 1)

#define ADC_IER_EOC2 (0x1u << 2)

#define ADC_IER_EOC3 (0x1u << 3)

#define ADC_IER_EOC4 (0x1u << 4)

#define ADC_IER_EOC5 (0x1u << 5)

#define ADC_IER_EOC6 (0x1u << 6)

#define ADC_IER_EOC7 (0x1u << 7)

#define ADC_IER_EOC8 (0x1u << 8)

#define ADC_IER_EOC9 (0x1u << 9)

#define ADC_IER_EOC10 (0x1u << 10)

#define ADC_IER_EOC11 (0x1u << 11)

#define ADC_IER_EOC12 (0x1u << 12)

#define ADC_IER_EOC13 (0x1u << 13)

#define ADC_IER_EOC14 (0x1u << 14)

#define ADC_IER_EOC15 (0x1u << 15)

#define ADC_IER_EOCAL (0x1u << 23)

#define ADC_IER_DRDY (0x1u << 24)

#define ADC_IER_GOVRE (0x1u << 25)

#define ADC_IER_COMPE (0x1u << 26)

#define ADC_IER_ENDRX (0x1u << 27)

#define ADC_IER_RXBUFF (0x1u << 28)

/* -------- ADC_IDR : (ADC Offset: 0x28) Interrupt Disable Register -------- */

#define ADC_IDR_EOC0 (0x1u << 0)

#define ADC_IDR_EOC1 (0x1u << 1)

#define ADC_IDR_EOC2 (0x1u << 2)

#define ADC_IDR_EOC3 (0x1u << 3)

#define ADC_IDR_EOC4 (0x1u << 4)

#define ADC_IDR_EOC5 (0x1u << 5)

#define ADC_IDR_EOC6 (0x1u << 6)

#define ADC_IDR_EOC7 (0x1u << 7)

#define ADC_IDR_EOC8 (0x1u << 8)

#define ADC_IDR_EOC9 (0x1u << 9)

#define ADC_IDR_EOC10 (0x1u << 10)

#define ADC_IDR_EOC11 (0x1u << 11)

#define ADC_IDR_EOC12 (0x1u << 12)

#define ADC_IDR_EOC13 (0x1u << 13)

#define ADC_IDR_EOC14 (0x1u << 14)

#define ADC_IDR_EOC15 (0x1u << 15)

#define ADC_IDR_EOCAL (0x1u << 23)

#define ADC_IDR_DRDY (0x1u << 24)

#define ADC_IDR_GOVRE (0x1u << 25)

#define ADC_IDR_COMPE (0x1u << 26)

#define ADC_IDR_ENDRX (0x1u << 27)

#define ADC_IDR_RXBUFF (0x1u << 28)

/* -------- ADC_IMR : (ADC Offset: 0x2C) Interrupt Mask Register -------- */

#define ADC_IMR_EOC0 (0x1u << 0)

#define ADC_IMR_EOC1 (0x1u << 1)

#define ADC_IMR_EOC2 (0x1u << 2)

#define ADC_IMR_EOC3 (0x1u << 3)

#define ADC_IMR_EOC4 (0x1u << 4)

#define ADC_IMR_EOC5 (0x1u << 5)

#define ADC_IMR_EOC6 (0x1u << 6)

#define ADC_IMR_EOC7 (0x1u << 7)

#define ADC_IMR_EOC8 (0x1u << 8)

#define ADC_IMR_EOC9 (0x1u << 9)

#define ADC_IMR_EOC10 (0x1u << 10)

#define ADC_IMR_EOC11 (0x1u << 11)

#define ADC_IMR_EOC12 (0x1u << 12)

#define ADC_IMR_EOC13 (0x1u << 13)

#define ADC_IMR_EOC14 (0x1u << 14)

#define ADC_IMR_EOC15 (0x1u << 15)

#define ADC_IMR_EOCAL (0x1u << 23)

#define ADC_IMR_DRDY (0x1u << 24)

#define ADC_IMR_GOVRE (0x1u << 25)

#define ADC_IMR_COMPE (0x1u << 26)

#define ADC_IMR_ENDRX (0x1u << 27)

#define ADC_IMR_RXBUFF (0x1u << 28)

/* -------- ADC_ISR : (ADC Offset: 0x30) Interrupt Status Register -------- */

#define ADC_ISR_EOC0 (0x1u << 0)

#define ADC_ISR_EOC1 (0x1u << 1)

#define ADC_ISR_EOC2 (0x1u << 2)

#define ADC_ISR_EOC3 (0x1u << 3)

#define ADC_ISR_EOC4 (0x1u << 4)

#define ADC_ISR_EOC5 (0x1u << 5)

#define ADC_ISR_EOC6 (0x1u << 6)

#define ADC_ISR_EOC7 (0x1u << 7)

#define ADC_ISR_EOC8 (0x1u << 8)

#define ADC_ISR_EOC9 (0x1u << 9)

#define ADC_ISR_EOC10 (0x1u << 10)

#define ADC_ISR_EOC11 (0x1u << 11)

#define ADC_ISR_EOC12 (0x1u << 12)

#define ADC_ISR_EOC13 (0x1u << 13)

#define ADC_ISR_EOC14 (0x1u << 14)

#define ADC_ISR_EOC15 (0x1u << 15)

#define ADC_ISR_EOCAL (0x1u << 23)

#define ADC_ISR_DRDY (0x1u << 24)

#define ADC_ISR_GOVRE (0x1u << 25)

#define ADC_ISR_COMPE (0x1u << 26)

#define ADC_ISR_ENDRX (0x1u << 27)

#define ADC_ISR_RXBUFF (0x1u << 28)

/* -------- ADC_OVER : (ADC Offset: 0x3C) Overrun Status Register -------- */

#define ADC_OVER_OVRE0 (0x1u << 0)

#define ADC_OVER_OVRE1 (0x1u << 1)

#define ADC_OVER_OVRE2 (0x1u << 2)

#define ADC_OVER_OVRE3 (0x1u << 3)

#define ADC_OVER_OVRE4 (0x1u << 4)

#define ADC_OVER_OVRE5 (0x1u << 5)

#define ADC_OVER_OVRE6 (0x1u << 6)

#define ADC_OVER_OVRE7 (0x1u << 7)

#define ADC_OVER_OVRE8 (0x1u << 8)

#define ADC_OVER_OVRE9 (0x1u << 9)

#define ADC_OVER_OVRE10 (0x1u << 10)

#define ADC_OVER_OVRE11 (0x1u << 11)

#define ADC_OVER_OVRE12 (0x1u << 12)

#define ADC_OVER_OVRE13 (0x1u << 13)

#define ADC_OVER_OVRE14 (0x1u << 14)

#define ADC_OVER_OVRE15 (0x1u << 15)

/* -------- ADC_EMR : (ADC Offset: 0x40) Extended Mode Register -------- */

#define ADC_EMR_CMPMODE_Pos 0

#define ADC_EMR_CMPMODE_Msk (0x3u << ADC_EMR_CMPMODE_Pos)

#define   ADC_EMR_CMPMODE_LOW (0x0u << 0)

#define   ADC_EMR_CMPMODE_HIGH (0x1u << 0)

#define   ADC_EMR_CMPMODE_IN (0x2u << 0)

#define   ADC_EMR_CMPMODE_OUT (0x3u << 0)

#define ADC_EMR_CMPSEL_Pos 4

#define ADC_EMR_CMPSEL_Msk (0xfu << ADC_EMR_CMPSEL_Pos)

#define ADC_EMR_CMPSEL(value) ((ADC_EMR_CMPSEL_Msk & ((value) << ADC_EMR_CMPSEL_Pos)))

#define ADC_EMR_CMPALL (0x1u << 9)

#define ADC_EMR_TAG (0x1u << 24)

/* -------- ADC_CWR : (ADC Offset: 0x44) Compare Window Register -------- */

#define ADC_CWR_LOWTHRES_Pos 0

#define ADC_CWR_LOWTHRES_Msk (0xfffu << ADC_CWR_LOWTHRES_Pos)

#define ADC_CWR_LOWTHRES(value) ((ADC_CWR_LOWTHRES_Msk & ((value) << ADC_CWR_LOWTHRES_Pos)))

#define ADC_CWR_HIGHTHRES_Pos 16

#define ADC_CWR_HIGHTHRES_Msk (0xfffu << ADC_CWR_HIGHTHRES_Pos)

#define ADC_CWR_HIGHTHRES(value) ((ADC_CWR_HIGHTHRES_Msk & ((value) << ADC_CWR_HIGHTHRES_Pos)))

/* -------- ADC_CGR : (ADC Offset: 0x48) Channel Gain Register -------- */

#define ADC_CGR_GAIN0_Pos 0

#define ADC_CGR_GAIN0_Msk (0x3u << ADC_CGR_GAIN0_Pos)

#define ADC_CGR_GAIN0(value) ((ADC_CGR_GAIN0_Msk & ((value) << ADC_CGR_GAIN0_Pos)))

#define ADC_CGR_GAIN1_Pos 2

#define ADC_CGR_GAIN1_Msk (0x3u << ADC_CGR_GAIN1_Pos)

#define ADC_CGR_GAIN1(value) ((ADC_CGR_GAIN1_Msk & ((value) << ADC_CGR_GAIN1_Pos)))

#define ADC_CGR_GAIN2_Pos 4

#define ADC_CGR_GAIN2_Msk (0x3u << ADC_CGR_GAIN2_Pos)

#define ADC_CGR_GAIN2(value) ((ADC_CGR_GAIN2_Msk & ((value) << ADC_CGR_GAIN2_Pos)))

#define ADC_CGR_GAIN3_Pos 6

#define ADC_CGR_GAIN3_Msk (0x3u << ADC_CGR_GAIN3_Pos)

#define ADC_CGR_GAIN3(value) ((ADC_CGR_GAIN3_Msk & ((value) << ADC_CGR_GAIN3_Pos)))

#define ADC_CGR_GAIN4_Pos 8

#define ADC_CGR_GAIN4_Msk (0x3u << ADC_CGR_GAIN4_Pos)

#define ADC_CGR_GAIN4(value) ((ADC_CGR_GAIN4_Msk & ((value) << ADC_CGR_GAIN4_Pos)))

#define ADC_CGR_GAIN5_Pos 10

#define ADC_CGR_GAIN5_Msk (0x3u << ADC_CGR_GAIN5_Pos)

#define ADC_CGR_GAIN5(value) ((ADC_CGR_GAIN5_Msk & ((value) << ADC_CGR_GAIN5_Pos)))

#define ADC_CGR_GAIN6_Pos 12

#define ADC_CGR_GAIN6_Msk (0x3u << ADC_CGR_GAIN6_Pos)

#define ADC_CGR_GAIN6(value) ((ADC_CGR_GAIN6_Msk & ((value) << ADC_CGR_GAIN6_Pos)))

#define ADC_CGR_GAIN7_Pos 14

#define ADC_CGR_GAIN7_Msk (0x3u << ADC_CGR_GAIN7_Pos)

#define ADC_CGR_GAIN7(value) ((ADC_CGR_GAIN7_Msk & ((value) << ADC_CGR_GAIN7_Pos)))

#define ADC_CGR_GAIN8_Pos 16

#define ADC_CGR_GAIN8_Msk (0x3u << ADC_CGR_GAIN8_Pos)

#define ADC_CGR_GAIN8(value) ((ADC_CGR_GAIN8_Msk & ((value) << ADC_CGR_GAIN8_Pos)))

#define ADC_CGR_GAIN9_Pos 18

#define ADC_CGR_GAIN9_Msk (0x3u << ADC_CGR_GAIN9_Pos)

#define ADC_CGR_GAIN9(value) ((ADC_CGR_GAIN9_Msk & ((value) << ADC_CGR_GAIN9_Pos)))

#define ADC_CGR_GAIN10_Pos 20

#define ADC_CGR_GAIN10_Msk (0x3u << ADC_CGR_GAIN10_Pos)

#define ADC_CGR_GAIN10(value) ((ADC_CGR_GAIN10_Msk & ((value) << ADC_CGR_GAIN10_Pos)))

#define ADC_CGR_GAIN11_Pos 22

#define ADC_CGR_GAIN11_Msk (0x3u << ADC_CGR_GAIN11_Pos)

#define ADC_CGR_GAIN11(value) ((ADC_CGR_GAIN11_Msk & ((value) << ADC_CGR_GAIN11_Pos)))

#define ADC_CGR_GAIN12_Pos 24

#define ADC_CGR_GAIN12_Msk (0x3u << ADC_CGR_GAIN12_Pos)

#define ADC_CGR_GAIN12(value) ((ADC_CGR_GAIN12_Msk & ((value) << ADC_CGR_GAIN12_Pos)))

#define ADC_CGR_GAIN13_Pos 26

#define ADC_CGR_GAIN13_Msk (0x3u << ADC_CGR_GAIN13_Pos)

#define ADC_CGR_GAIN13(value) ((ADC_CGR_GAIN13_Msk & ((value) << ADC_CGR_GAIN13_Pos)))

#define ADC_CGR_GAIN14_Pos 28

#define ADC_CGR_GAIN14_Msk (0x3u << ADC_CGR_GAIN14_Pos)

#define ADC_CGR_GAIN14(value) ((ADC_CGR_GAIN14_Msk & ((value) << ADC_CGR_GAIN14_Pos)))

#define ADC_CGR_GAIN15_Pos 30

#define ADC_CGR_GAIN15_Msk (0x3u << ADC_CGR_GAIN15_Pos)

#define ADC_CGR_GAIN15(value) ((ADC_CGR_GAIN15_Msk & ((value) << ADC_CGR_GAIN15_Pos)))

/* -------- ADC_COR : (ADC Offset: 0x4C) Channel Offset Register -------- */

#define ADC_COR_OFF0 (0x1u << 0)

#define ADC_COR_OFF1 (0x1u << 1)

#define ADC_COR_OFF2 (0x1u << 2)

#define ADC_COR_OFF3 (0x1u << 3)

#define ADC_COR_OFF4 (0x1u << 4)

#define ADC_COR_OFF5 (0x1u << 5)

#define ADC_COR_OFF6 (0x1u << 6)

#define ADC_COR_OFF7 (0x1u << 7)

#define ADC_COR_OFF8 (0x1u << 8)

#define ADC_COR_OFF9 (0x1u << 9)

#define ADC_COR_OFF10 (0x1u << 10)

#define ADC_COR_OFF11 (0x1u << 11)

#define ADC_COR_OFF12 (0x1u << 12)

#define ADC_COR_OFF13 (0x1u << 13)

#define ADC_COR_OFF14 (0x1u << 14)

#define ADC_COR_OFF15 (0x1u << 15)

#define ADC_COR_DIFF0 (0x1u << 16)

#define ADC_COR_DIFF1 (0x1u << 17)

#define ADC_COR_DIFF2 (0x1u << 18)

#define ADC_COR_DIFF3 (0x1u << 19)

#define ADC_COR_DIFF4 (0x1u << 20)

#define ADC_COR_DIFF5 (0x1u << 21)

#define ADC_COR_DIFF6 (0x1u << 22)

#define ADC_COR_DIFF7 (0x1u << 23)

#define ADC_COR_DIFF8 (0x1u << 24)

#define ADC_COR_DIFF9 (0x1u << 25)

#define ADC_COR_DIFF10 (0x1u << 26)

#define ADC_COR_DIFF11 (0x1u << 27)

#define ADC_COR_DIFF12 (0x1u << 28)

#define ADC_COR_DIFF13 (0x1u << 29)

#define ADC_COR_DIFF14 (0x1u << 30)

#define ADC_COR_DIFF15 (0x1u << 31)

/* -------- ADC_CDR[16] : (ADC Offset: 0x50) Channel Data Register -------- */

#define ADC_CDR_DATA_Pos 0

#define ADC_CDR_DATA_Msk (0xfffu << ADC_CDR_DATA_Pos)

/* -------- ADC_ACR : (ADC Offset: 0x94) Analog Control Register -------- */

#define ADC_ACR_TSON (0x1u << 4)

#define ADC_ACR_IBCTL_Pos 8

#define ADC_ACR_IBCTL_Msk (0x3u << ADC_ACR_IBCTL_Pos)

#define ADC_ACR_IBCTL(value) ((ADC_ACR_IBCTL_Msk & ((value) << ADC_ACR_IBCTL_Pos)))

/* -------- ADC_WPMR : (ADC Offset: 0xE4) Write Protect Mode Register -------- */

#define ADC_WPMR_WPEN (0x1u << 0)

#define ADC_WPMR_WPKEY_Pos 8

#define ADC_WPMR_WPKEY_Msk (0xffffffu << ADC_WPMR_WPKEY_Pos)

#define   ADC_WPMR_WPKEY_PASSWD (0x414443u << 8)

/* -------- ADC_WPSR : (ADC Offset: 0xE8) Write Protect Status Register -------- */

#define ADC_WPSR_WPVS (0x1u << 0)

#define ADC_WPSR_WPVSRC_Pos 8

#define ADC_WPSR_WPVSRC_Msk (0xffffu << ADC_WPSR_WPVSRC_Pos)

/* -------- ADC_RPR : (ADC Offset: 0x100) Receive Pointer Register -------- */

#define ADC_RPR_RXPTR_Pos 0

#define ADC_RPR_RXPTR_Msk (0xffffffffu << ADC_RPR_RXPTR_Pos)

#define ADC_RPR_RXPTR(value) ((ADC_RPR_RXPTR_Msk & ((value) << ADC_RPR_RXPTR_Pos)))

/* -------- ADC_RCR : (ADC Offset: 0x104) Receive Counter Register -------- */

#define ADC_RCR_RXCTR_Pos 0

#define ADC_RCR_RXCTR_Msk (0xffffu << ADC_RCR_RXCTR_Pos)

#define ADC_RCR_RXCTR(value) ((ADC_RCR_RXCTR_Msk & ((value) << ADC_RCR_RXCTR_Pos)))

/* -------- ADC_RNPR : (ADC Offset: 0x110) Receive Next Pointer Register -------- */

#define ADC_RNPR_RXNPTR_Pos 0

#define ADC_RNPR_RXNPTR_Msk (0xffffffffu << ADC_RNPR_RXNPTR_Pos)

#define ADC_RNPR_RXNPTR(value) ((ADC_RNPR_RXNPTR_Msk & ((value) << ADC_RNPR_RXNPTR_Pos)))

/* -------- ADC_RNCR : (ADC Offset: 0x114) Receive Next Counter Register -------- */

#define ADC_RNCR_RXNCTR_Pos 0

#define ADC_RNCR_RXNCTR_Msk (0xffffu << ADC_RNCR_RXNCTR_Pos)

#define ADC_RNCR_RXNCTR(value) ((ADC_RNCR_RXNCTR_Msk & ((value) << ADC_RNCR_RXNCTR_Pos)))

/* -------- ADC_PTCR : (ADC Offset: 0x120) Transfer Control Register -------- */

#define ADC_PTCR_RXTEN (0x1u << 0)

#define ADC_PTCR_RXTDIS (0x1u << 1)

#define ADC_PTCR_TXTEN (0x1u << 8)

#define ADC_PTCR_TXTDIS (0x1u << 9)

/* -------- ADC_PTSR : (ADC Offset: 0x124) Transfer Status Register -------- */

#define ADC_PTSR_RXTEN (0x1u << 0)

#define ADC_PTSR_TXTEN (0x1u << 8)


#endif /* _SAM4S_ADC_COMPONENT_ */

Adc
Adc hardware registers.
Definition component_adc.h:46

Adc::ADC_WPSR
__I uint32_t ADC_WPSR
(Adc Offset: 0xE8) Write Protect Status Register
Definition component_adc.h:71

Adc::ADC_EMR
__IO uint32_t ADC_EMR
(Adc Offset: 0x40) Extended Mode Register
Definition component_adc.h:62

Adc::ADC_PTCR
__O uint32_t ADC_PTCR
(Adc Offset: 0x120) Transfer Control Register
Definition component_adc.h:79

Adc::ADC_MR
__IO uint32_t ADC_MR
(Adc Offset: 0x04) Mode Register
Definition component_adc.h:48

Adc::ADC_CHSR
__I uint32_t ADC_CHSR
(Adc Offset: 0x18) Channel Status Register
Definition component_adc.h:53

Adc::ADC_IDR
__O uint32_t ADC_IDR
(Adc Offset: 0x28) Interrupt Disable Register
Definition component_adc.h:57

Adc::ADC_ISR
__I uint32_t ADC_ISR
(Adc Offset: 0x30) Interrupt Status Register
Definition component_adc.h:59

Adc::ADC_RCR
__IO uint32_t ADC_RCR
(Adc Offset: 0x104) Receive Counter Register
Definition component_adc.h:74

Adc::ADC_CHER
__O uint32_t ADC_CHER
(Adc Offset: 0x10) Channel Enable Register
Definition component_adc.h:51

Adc::ADC_IER
__O uint32_t ADC_IER
(Adc Offset: 0x24) Interrupt Enable Register
Definition component_adc.h:56

Adc::ADC_IMR
__I uint32_t ADC_IMR
(Adc Offset: 0x2C) Interrupt Mask Register
Definition component_adc.h:58

Adc::Reserved5
__I uint32_t Reserved5[5]
Definition component_adc.h:72

Adc::ADC_CWR
__IO uint32_t ADC_CWR
(Adc Offset: 0x44) Compare Window Register
Definition component_adc.h:63

Adc::ADC_COR
__IO uint32_t ADC_COR
(Adc Offset: 0x4C) Channel Offset Register
Definition component_adc.h:65

Adc::ADC_RPR
__IO uint32_t ADC_RPR
(Adc Offset: 0x100) Receive Pointer Register
Definition component_adc.h:73

Adc::Reserved2
__I uint32_t Reserved2[2]
Definition component_adc.h:60

Adc::ADC_CR
__O uint32_t ADC_CR
(Adc Offset: 0x00) Control Register
Definition component_adc.h:47

Adc::ADC_PTSR
__I uint32_t ADC_PTSR
(Adc Offset: 0x124) Transfer Status Register
Definition component_adc.h:80

Adc::Reserved6
__I uint32_t Reserved6[2]
Definition component_adc.h:75

Adc::ADC_LCDR
__I uint32_t ADC_LCDR
(Adc Offset: 0x20) Last Converted Data Register
Definition component_adc.h:55

Adc::ADC_SEQR2
__IO uint32_t ADC_SEQR2
(Adc Offset: 0x0C) Channel Sequence Register 2
Definition component_adc.h:50

Adc::ADC_OVER
__I uint32_t ADC_OVER
(Adc Offset: 0x3C) Overrun Status Register
Definition component_adc.h:61

Adc::Reserved3
__I uint32_t Reserved3[1]
Definition component_adc.h:67

Adc::Reserved1
__I uint32_t Reserved1[1]
Definition component_adc.h:54

Adc::Reserved7
__I uint32_t Reserved7[2]
Definition component_adc.h:78

Adc::ADC_CGR
__IO uint32_t ADC_CGR
(Adc Offset: 0x48) Channel Gain Register
Definition component_adc.h:64

Adc::ADC_SEQR1
__IO uint32_t ADC_SEQR1
(Adc Offset: 0x08) Channel Sequence Register 1
Definition component_adc.h:49

Adc::ADC_WPMR
__IO uint32_t ADC_WPMR
(Adc Offset: 0xE4) Write Protect Mode Register
Definition component_adc.h:70

Adc::ADC_RNCR
__IO uint32_t ADC_RNCR
(Adc Offset: 0x114) Receive Next Counter Register
Definition component_adc.h:77

Adc::Reserved4
__I uint32_t Reserved4[19]
Definition component_adc.h:69

Adc::ADC_ACR
__IO uint32_t ADC_ACR
(Adc Offset: 0x94) Analog Control Register
Definition component_adc.h:68

Adc::ADC_RNPR
__IO uint32_t ADC_RNPR
(Adc Offset: 0x110) Receive Next Pointer Register
Definition component_adc.h:76

Adc::ADC_CDR
__I uint32_t ADC_CDR[16]
(Adc Offset: 0x50) Channel Data Register
Definition component_adc.h:66

Adc::ADC_CHDR
__O uint32_t ADC_CHDR
(Adc Offset: 0x14) Channel Disable Register
Definition component_adc.h:52