Data Structures
struct	Adc
	Adc hardware registers. More...

Macros
#define	ADC_ACR_IBCTL(value)
#define	ADC_ACR_IBCTL_Msk (0x3u << ADC_ACR_IBCTL_Pos)
	(ADC_ACR) ADC Bias Current Control
#define	ADC_ACR_IBCTL_Pos 8
#define	ADC_ACR_TSON (0x1u << 4)
	(ADC_ACR) Temperature Sensor On
#define	ADC_CDR_DATA_Msk (0xfffu << ADC_CDR_DATA_Pos)
	(ADC_CDR[16]) Converted Data
#define	ADC_CDR_DATA_Pos 0
#define	ADC_CGR_GAIN0(value)
#define	ADC_CGR_GAIN0_Msk (0x3u << ADC_CGR_GAIN0_Pos)
	(ADC_CGR) Gain for Channel 0
#define	ADC_CGR_GAIN0_Pos 0
#define	ADC_CGR_GAIN1(value)
#define	ADC_CGR_GAIN10(value)
#define	ADC_CGR_GAIN10_Msk (0x3u << ADC_CGR_GAIN10_Pos)
	(ADC_CGR) Gain for Channel 10
#define	ADC_CGR_GAIN10_Pos 20
#define	ADC_CGR_GAIN11(value)
#define	ADC_CGR_GAIN11_Msk (0x3u << ADC_CGR_GAIN11_Pos)
	(ADC_CGR) Gain for Channel 11
#define	ADC_CGR_GAIN11_Pos 22
#define	ADC_CGR_GAIN12(value)
#define	ADC_CGR_GAIN12_Msk (0x3u << ADC_CGR_GAIN12_Pos)
	(ADC_CGR) Gain for Channel 12
#define	ADC_CGR_GAIN12_Pos 24
#define	ADC_CGR_GAIN13(value)
#define	ADC_CGR_GAIN13_Msk (0x3u << ADC_CGR_GAIN13_Pos)
	(ADC_CGR) Gain for Channel 13
#define	ADC_CGR_GAIN13_Pos 26
#define	ADC_CGR_GAIN14(value)
#define	ADC_CGR_GAIN14_Msk (0x3u << ADC_CGR_GAIN14_Pos)
	(ADC_CGR) Gain for Channel 14
#define	ADC_CGR_GAIN14_Pos 28
#define	ADC_CGR_GAIN15(value)
#define	ADC_CGR_GAIN15_Msk (0x3u << ADC_CGR_GAIN15_Pos)
	(ADC_CGR) Gain for Channel 15
#define	ADC_CGR_GAIN15_Pos 30
#define	ADC_CGR_GAIN1_Msk (0x3u << ADC_CGR_GAIN1_Pos)
	(ADC_CGR) Gain for Channel 1
#define	ADC_CGR_GAIN1_Pos 2
#define	ADC_CGR_GAIN2(value)
#define	ADC_CGR_GAIN2_Msk (0x3u << ADC_CGR_GAIN2_Pos)
	(ADC_CGR) Gain for Channel 2
#define	ADC_CGR_GAIN2_Pos 4
#define	ADC_CGR_GAIN3(value)
#define	ADC_CGR_GAIN3_Msk (0x3u << ADC_CGR_GAIN3_Pos)
	(ADC_CGR) Gain for Channel 3
#define	ADC_CGR_GAIN3_Pos 6
#define	ADC_CGR_GAIN4(value)
#define	ADC_CGR_GAIN4_Msk (0x3u << ADC_CGR_GAIN4_Pos)
	(ADC_CGR) Gain for Channel 4
#define	ADC_CGR_GAIN4_Pos 8
#define	ADC_CGR_GAIN5(value)
#define	ADC_CGR_GAIN5_Msk (0x3u << ADC_CGR_GAIN5_Pos)
	(ADC_CGR) Gain for Channel 5
#define	ADC_CGR_GAIN5_Pos 10
#define	ADC_CGR_GAIN6(value)
#define	ADC_CGR_GAIN6_Msk (0x3u << ADC_CGR_GAIN6_Pos)
	(ADC_CGR) Gain for Channel 6
#define	ADC_CGR_GAIN6_Pos 12
#define	ADC_CGR_GAIN7(value)
#define	ADC_CGR_GAIN7_Msk (0x3u << ADC_CGR_GAIN7_Pos)
	(ADC_CGR) Gain for Channel 7
#define	ADC_CGR_GAIN7_Pos 14
#define	ADC_CGR_GAIN8(value)
#define	ADC_CGR_GAIN8_Msk (0x3u << ADC_CGR_GAIN8_Pos)
	(ADC_CGR) Gain for Channel 8
#define	ADC_CGR_GAIN8_Pos 16
#define	ADC_CGR_GAIN9(value)
#define	ADC_CGR_GAIN9_Msk (0x3u << ADC_CGR_GAIN9_Pos)
	(ADC_CGR) Gain for Channel 9
#define	ADC_CGR_GAIN9_Pos 18
#define	ADC_CHDR_CH0 (0x1u << 0)
	(ADC_CHDR) Channel 0 Disable
#define	ADC_CHDR_CH1 (0x1u << 1)
	(ADC_CHDR) Channel 1 Disable
#define	ADC_CHDR_CH10 (0x1u << 10)
	(ADC_CHDR) Channel 10 Disable
#define	ADC_CHDR_CH11 (0x1u << 11)
	(ADC_CHDR) Channel 11 Disable
#define	ADC_CHDR_CH12 (0x1u << 12)
	(ADC_CHDR) Channel 12 Disable
#define	ADC_CHDR_CH13 (0x1u << 13)
	(ADC_CHDR) Channel 13 Disable
#define	ADC_CHDR_CH14 (0x1u << 14)
	(ADC_CHDR) Channel 14 Disable
#define	ADC_CHDR_CH15 (0x1u << 15)
	(ADC_CHDR) Channel 15 Disable
#define	ADC_CHDR_CH2 (0x1u << 2)
	(ADC_CHDR) Channel 2 Disable
#define	ADC_CHDR_CH3 (0x1u << 3)
	(ADC_CHDR) Channel 3 Disable
#define	ADC_CHDR_CH4 (0x1u << 4)
	(ADC_CHDR) Channel 4 Disable
#define	ADC_CHDR_CH5 (0x1u << 5)
	(ADC_CHDR) Channel 5 Disable
#define	ADC_CHDR_CH6 (0x1u << 6)
	(ADC_CHDR) Channel 6 Disable
#define	ADC_CHDR_CH7 (0x1u << 7)
	(ADC_CHDR) Channel 7 Disable
#define	ADC_CHDR_CH8 (0x1u << 8)
	(ADC_CHDR) Channel 8 Disable
#define	ADC_CHDR_CH9 (0x1u << 9)
	(ADC_CHDR) Channel 9 Disable
#define	ADC_CHER_CH0 (0x1u << 0)
	(ADC_CHER) Channel 0 Enable
#define	ADC_CHER_CH1 (0x1u << 1)
	(ADC_CHER) Channel 1 Enable
#define	ADC_CHER_CH10 (0x1u << 10)
	(ADC_CHER) Channel 10 Enable
#define	ADC_CHER_CH11 (0x1u << 11)
	(ADC_CHER) Channel 11 Enable
#define	ADC_CHER_CH12 (0x1u << 12)
	(ADC_CHER) Channel 12 Enable
#define	ADC_CHER_CH13 (0x1u << 13)
	(ADC_CHER) Channel 13 Enable
#define	ADC_CHER_CH14 (0x1u << 14)
	(ADC_CHER) Channel 14 Enable
#define	ADC_CHER_CH15 (0x1u << 15)
	(ADC_CHER) Channel 15 Enable
#define	ADC_CHER_CH2 (0x1u << 2)
	(ADC_CHER) Channel 2 Enable
#define	ADC_CHER_CH3 (0x1u << 3)
	(ADC_CHER) Channel 3 Enable
#define	ADC_CHER_CH4 (0x1u << 4)
	(ADC_CHER) Channel 4 Enable
#define	ADC_CHER_CH5 (0x1u << 5)
	(ADC_CHER) Channel 5 Enable
#define	ADC_CHER_CH6 (0x1u << 6)
	(ADC_CHER) Channel 6 Enable
#define	ADC_CHER_CH7 (0x1u << 7)
	(ADC_CHER) Channel 7 Enable
#define	ADC_CHER_CH8 (0x1u << 8)
	(ADC_CHER) Channel 8 Enable
#define	ADC_CHER_CH9 (0x1u << 9)
	(ADC_CHER) Channel 9 Enable
#define	ADC_CHSR_CH0 (0x1u << 0)
	(ADC_CHSR) Channel 0 Status
#define	ADC_CHSR_CH1 (0x1u << 1)
	(ADC_CHSR) Channel 1 Status
#define	ADC_CHSR_CH10 (0x1u << 10)
	(ADC_CHSR) Channel 10 Status
#define	ADC_CHSR_CH11 (0x1u << 11)
	(ADC_CHSR) Channel 11 Status
#define	ADC_CHSR_CH12 (0x1u << 12)
	(ADC_CHSR) Channel 12 Status
#define	ADC_CHSR_CH13 (0x1u << 13)
	(ADC_CHSR) Channel 13 Status
#define	ADC_CHSR_CH14 (0x1u << 14)
	(ADC_CHSR) Channel 14 Status
#define	ADC_CHSR_CH15 (0x1u << 15)
	(ADC_CHSR) Channel 15 Status
#define	ADC_CHSR_CH2 (0x1u << 2)
	(ADC_CHSR) Channel 2 Status
#define	ADC_CHSR_CH3 (0x1u << 3)
	(ADC_CHSR) Channel 3 Status
#define	ADC_CHSR_CH4 (0x1u << 4)
	(ADC_CHSR) Channel 4 Status
#define	ADC_CHSR_CH5 (0x1u << 5)
	(ADC_CHSR) Channel 5 Status
#define	ADC_CHSR_CH6 (0x1u << 6)
	(ADC_CHSR) Channel 6 Status
#define	ADC_CHSR_CH7 (0x1u << 7)
	(ADC_CHSR) Channel 7 Status
#define	ADC_CHSR_CH8 (0x1u << 8)
	(ADC_CHSR) Channel 8 Status
#define	ADC_CHSR_CH9 (0x1u << 9)
	(ADC_CHSR) Channel 9 Status
#define	ADC_COR_DIFF0 (0x1u << 16)
	(ADC_COR) Differential inputs for channel 0
#define	ADC_COR_DIFF1 (0x1u << 17)
	(ADC_COR) Differential inputs for channel 1
#define	ADC_COR_DIFF10 (0x1u << 26)
	(ADC_COR) Differential inputs for channel 10
#define	ADC_COR_DIFF11 (0x1u << 27)
	(ADC_COR) Differential inputs for channel 11
#define	ADC_COR_DIFF12 (0x1u << 28)
	(ADC_COR) Differential inputs for channel 12
#define	ADC_COR_DIFF13 (0x1u << 29)
	(ADC_COR) Differential inputs for channel 13
#define	ADC_COR_DIFF14 (0x1u << 30)
	(ADC_COR) Differential inputs for channel 14
#define	ADC_COR_DIFF15 (0x1u << 31)
	(ADC_COR) Differential inputs for channel 15
#define	ADC_COR_DIFF2 (0x1u << 18)
	(ADC_COR) Differential inputs for channel 2
#define	ADC_COR_DIFF3 (0x1u << 19)
	(ADC_COR) Differential inputs for channel 3
#define	ADC_COR_DIFF4 (0x1u << 20)
	(ADC_COR) Differential inputs for channel 4
#define	ADC_COR_DIFF5 (0x1u << 21)
	(ADC_COR) Differential inputs for channel 5
#define	ADC_COR_DIFF6 (0x1u << 22)
	(ADC_COR) Differential inputs for channel 6
#define	ADC_COR_DIFF7 (0x1u << 23)
	(ADC_COR) Differential inputs for channel 7
#define	ADC_COR_DIFF8 (0x1u << 24)
	(ADC_COR) Differential inputs for channel 8
#define	ADC_COR_DIFF9 (0x1u << 25)
	(ADC_COR) Differential inputs for channel 9
#define	ADC_COR_OFF0 (0x1u << 0)
	(ADC_COR) Offset for channel 0
#define	ADC_COR_OFF1 (0x1u << 1)
	(ADC_COR) Offset for channel 1
#define	ADC_COR_OFF10 (0x1u << 10)
	(ADC_COR) Offset for channel 10
#define	ADC_COR_OFF11 (0x1u << 11)
	(ADC_COR) Offset for channel 11
#define	ADC_COR_OFF12 (0x1u << 12)
	(ADC_COR) Offset for channel 12
#define	ADC_COR_OFF13 (0x1u << 13)
	(ADC_COR) Offset for channel 13
#define	ADC_COR_OFF14 (0x1u << 14)
	(ADC_COR) Offset for channel 14
#define	ADC_COR_OFF15 (0x1u << 15)
	(ADC_COR) Offset for channel 15
#define	ADC_COR_OFF2 (0x1u << 2)
	(ADC_COR) Offset for channel 2
#define	ADC_COR_OFF3 (0x1u << 3)
	(ADC_COR) Offset for channel 3
#define	ADC_COR_OFF4 (0x1u << 4)
	(ADC_COR) Offset for channel 4
#define	ADC_COR_OFF5 (0x1u << 5)
	(ADC_COR) Offset for channel 5
#define	ADC_COR_OFF6 (0x1u << 6)
	(ADC_COR) Offset for channel 6
#define	ADC_COR_OFF7 (0x1u << 7)
	(ADC_COR) Offset for channel 7
#define	ADC_COR_OFF8 (0x1u << 8)
	(ADC_COR) Offset for channel 8
#define	ADC_COR_OFF9 (0x1u << 9)
	(ADC_COR) Offset for channel 9
#define	ADC_CR_AUTOCAL (0x1u << 3)
	(ADC_CR) Automatic Calibration of ADC
#define	ADC_CR_START (0x1u << 1)
	(ADC_CR) Start Conversion
#define	ADC_CR_SWRST (0x1u << 0)
	(ADC_CR) Software Reset
#define	ADC_CWR_HIGHTHRES(value)
#define	ADC_CWR_HIGHTHRES_Msk (0xfffu << ADC_CWR_HIGHTHRES_Pos)
	(ADC_CWR) High Threshold
#define	ADC_CWR_HIGHTHRES_Pos 16
#define	ADC_CWR_LOWTHRES(value)
#define	ADC_CWR_LOWTHRES_Msk (0xfffu << ADC_CWR_LOWTHRES_Pos)
	(ADC_CWR) Low Threshold
#define	ADC_CWR_LOWTHRES_Pos 0
#define	ADC_EMR_CMPALL (0x1u << 9)
	(ADC_EMR) Compare All Channels
#define	ADC_EMR_CMPMODE_HIGH (0x1u << 0)
	(ADC_EMR) Generates an event when the converted data is higher than the high threshold of the window.
#define	ADC_EMR_CMPMODE_IN (0x2u << 0)
	(ADC_EMR) Generates an event when the converted data is in the comparison window.
#define	ADC_EMR_CMPMODE_LOW (0x0u << 0)
	(ADC_EMR) Generates an event when the converted data is lower than the low threshold of the window.
#define	ADC_EMR_CMPMODE_Msk (0x3u << ADC_EMR_CMPMODE_Pos)
	(ADC_EMR) Comparison Mode
#define	ADC_EMR_CMPMODE_OUT (0x3u << 0)
	(ADC_EMR) Generates an event when the converted data is out of the comparison window.
#define	ADC_EMR_CMPMODE_Pos 0
#define	ADC_EMR_CMPSEL(value)
#define	ADC_EMR_CMPSEL_Msk (0xfu << ADC_EMR_CMPSEL_Pos)
	(ADC_EMR) Comparison Selected Channel
#define	ADC_EMR_CMPSEL_Pos 4
#define	ADC_EMR_TAG (0x1u << 24)
	(ADC_EMR) TAG of the ADC_LDCR register
#define	ADC_IDR_COMPE (0x1u << 26)
	(ADC_IDR) Comparison Event Interrupt Disable
#define	ADC_IDR_DRDY (0x1u << 24)
	(ADC_IDR) Data Ready Interrupt Disable
#define	ADC_IDR_ENDRX (0x1u << 27)
	(ADC_IDR) End of Receive Buffer Interrupt Disable
#define	ADC_IDR_EOC0 (0x1u << 0)
	(ADC_IDR) End of Conversion Interrupt Disable 0
#define	ADC_IDR_EOC1 (0x1u << 1)
	(ADC_IDR) End of Conversion Interrupt Disable 1
#define	ADC_IDR_EOC10 (0x1u << 10)
	(ADC_IDR) End of Conversion Interrupt Disable 10
#define	ADC_IDR_EOC11 (0x1u << 11)
	(ADC_IDR) End of Conversion Interrupt Disable 11
#define	ADC_IDR_EOC12 (0x1u << 12)
	(ADC_IDR) End of Conversion Interrupt Disable 12
#define	ADC_IDR_EOC13 (0x1u << 13)
	(ADC_IDR) End of Conversion Interrupt Disable 13
#define	ADC_IDR_EOC14 (0x1u << 14)
	(ADC_IDR) End of Conversion Interrupt Disable 14
#define	ADC_IDR_EOC15 (0x1u << 15)
	(ADC_IDR) End of Conversion Interrupt Disable 15
#define	ADC_IDR_EOC2 (0x1u << 2)
	(ADC_IDR) End of Conversion Interrupt Disable 2
#define	ADC_IDR_EOC3 (0x1u << 3)
	(ADC_IDR) End of Conversion Interrupt Disable 3
#define	ADC_IDR_EOC4 (0x1u << 4)
	(ADC_IDR) End of Conversion Interrupt Disable 4
#define	ADC_IDR_EOC5 (0x1u << 5)
	(ADC_IDR) End of Conversion Interrupt Disable 5
#define	ADC_IDR_EOC6 (0x1u << 6)
	(ADC_IDR) End of Conversion Interrupt Disable 6
#define	ADC_IDR_EOC7 (0x1u << 7)
	(ADC_IDR) End of Conversion Interrupt Disable 7
#define	ADC_IDR_EOC8 (0x1u << 8)
	(ADC_IDR) End of Conversion Interrupt Disable 8
#define	ADC_IDR_EOC9 (0x1u << 9)
	(ADC_IDR) End of Conversion Interrupt Disable 9
#define	ADC_IDR_EOCAL (0x1u << 23)
	(ADC_IDR) End of Calibration Sequence
#define	ADC_IDR_GOVRE (0x1u << 25)
	(ADC_IDR) General Overrun Error Interrupt Disable
#define	ADC_IDR_RXBUFF (0x1u << 28)
	(ADC_IDR) Receive Buffer Full Interrupt Disable
#define	ADC_IER_COMPE (0x1u << 26)
	(ADC_IER) Comparison Event Interrupt Enable
#define	ADC_IER_DRDY (0x1u << 24)
	(ADC_IER) Data Ready Interrupt Enable
#define	ADC_IER_ENDRX (0x1u << 27)
	(ADC_IER) End of Receive Buffer Interrupt Enable
#define	ADC_IER_EOC0 (0x1u << 0)
	(ADC_IER) End of Conversion Interrupt Enable 0
#define	ADC_IER_EOC1 (0x1u << 1)
	(ADC_IER) End of Conversion Interrupt Enable 1
#define	ADC_IER_EOC10 (0x1u << 10)
	(ADC_IER) End of Conversion Interrupt Enable 10
#define	ADC_IER_EOC11 (0x1u << 11)
	(ADC_IER) End of Conversion Interrupt Enable 11
#define	ADC_IER_EOC12 (0x1u << 12)
	(ADC_IER) End of Conversion Interrupt Enable 12
#define	ADC_IER_EOC13 (0x1u << 13)
	(ADC_IER) End of Conversion Interrupt Enable 13
#define	ADC_IER_EOC14 (0x1u << 14)
	(ADC_IER) End of Conversion Interrupt Enable 14
#define	ADC_IER_EOC15 (0x1u << 15)
	(ADC_IER) End of Conversion Interrupt Enable 15
#define	ADC_IER_EOC2 (0x1u << 2)
	(ADC_IER) End of Conversion Interrupt Enable 2
#define	ADC_IER_EOC3 (0x1u << 3)
	(ADC_IER) End of Conversion Interrupt Enable 3
#define	ADC_IER_EOC4 (0x1u << 4)
	(ADC_IER) End of Conversion Interrupt Enable 4
#define	ADC_IER_EOC5 (0x1u << 5)
	(ADC_IER) End of Conversion Interrupt Enable 5
#define	ADC_IER_EOC6 (0x1u << 6)
	(ADC_IER) End of Conversion Interrupt Enable 6
#define	ADC_IER_EOC7 (0x1u << 7)
	(ADC_IER) End of Conversion Interrupt Enable 7
#define	ADC_IER_EOC8 (0x1u << 8)
	(ADC_IER) End of Conversion Interrupt Enable 8
#define	ADC_IER_EOC9 (0x1u << 9)
	(ADC_IER) End of Conversion Interrupt Enable 9
#define	ADC_IER_EOCAL (0x1u << 23)
	(ADC_IER) End of Calibration Sequence
#define	ADC_IER_GOVRE (0x1u << 25)
	(ADC_IER) General Overrun Error Interrupt Enable
#define	ADC_IER_RXBUFF (0x1u << 28)
	(ADC_IER) Receive Buffer Full Interrupt Enable
#define	ADC_IMR_COMPE (0x1u << 26)
	(ADC_IMR) Comparison Event Interrupt Mask
#define	ADC_IMR_DRDY (0x1u << 24)
	(ADC_IMR) Data Ready Interrupt Mask
#define	ADC_IMR_ENDRX (0x1u << 27)
	(ADC_IMR) End of Receive Buffer Interrupt Mask
#define	ADC_IMR_EOC0 (0x1u << 0)
	(ADC_IMR) End of Conversion Interrupt Mask 0
#define	ADC_IMR_EOC1 (0x1u << 1)
	(ADC_IMR) End of Conversion Interrupt Mask 1
#define	ADC_IMR_EOC10 (0x1u << 10)
	(ADC_IMR) End of Conversion Interrupt Mask 10
#define	ADC_IMR_EOC11 (0x1u << 11)
	(ADC_IMR) End of Conversion Interrupt Mask 11
#define	ADC_IMR_EOC12 (0x1u << 12)
	(ADC_IMR) End of Conversion Interrupt Mask 12
#define	ADC_IMR_EOC13 (0x1u << 13)
	(ADC_IMR) End of Conversion Interrupt Mask 13
#define	ADC_IMR_EOC14 (0x1u << 14)
	(ADC_IMR) End of Conversion Interrupt Mask 14
#define	ADC_IMR_EOC15 (0x1u << 15)
	(ADC_IMR) End of Conversion Interrupt Mask 15
#define	ADC_IMR_EOC2 (0x1u << 2)
	(ADC_IMR) End of Conversion Interrupt Mask 2
#define	ADC_IMR_EOC3 (0x1u << 3)
	(ADC_IMR) End of Conversion Interrupt Mask 3
#define	ADC_IMR_EOC4 (0x1u << 4)
	(ADC_IMR) End of Conversion Interrupt Mask 4
#define	ADC_IMR_EOC5 (0x1u << 5)
	(ADC_IMR) End of Conversion Interrupt Mask 5
#define	ADC_IMR_EOC6 (0x1u << 6)
	(ADC_IMR) End of Conversion Interrupt Mask 6
#define	ADC_IMR_EOC7 (0x1u << 7)
	(ADC_IMR) End of Conversion Interrupt Mask 7
#define	ADC_IMR_EOC8 (0x1u << 8)
	(ADC_IMR) End of Conversion Interrupt Mask 8
#define	ADC_IMR_EOC9 (0x1u << 9)
	(ADC_IMR) End of Conversion Interrupt Mask 9
#define	ADC_IMR_EOCAL (0x1u << 23)
	(ADC_IMR) End of Calibration Sequence
#define	ADC_IMR_GOVRE (0x1u << 25)
	(ADC_IMR) General Overrun Error Interrupt Mask
#define	ADC_IMR_RXBUFF (0x1u << 28)
	(ADC_IMR) Receive Buffer Full Interrupt Mask
#define	ADC_ISR_COMPE (0x1u << 26)
	(ADC_ISR) Comparison Error
#define	ADC_ISR_DRDY (0x1u << 24)
	(ADC_ISR) Data Ready
#define	ADC_ISR_ENDRX (0x1u << 27)
	(ADC_ISR) End of RX Buffer
#define	ADC_ISR_EOC0 (0x1u << 0)
	(ADC_ISR) End of Conversion 0
#define	ADC_ISR_EOC1 (0x1u << 1)
	(ADC_ISR) End of Conversion 1
#define	ADC_ISR_EOC10 (0x1u << 10)
	(ADC_ISR) End of Conversion 10
#define	ADC_ISR_EOC11 (0x1u << 11)
	(ADC_ISR) End of Conversion 11
#define	ADC_ISR_EOC12 (0x1u << 12)
	(ADC_ISR) End of Conversion 12
#define	ADC_ISR_EOC13 (0x1u << 13)
	(ADC_ISR) End of Conversion 13
#define	ADC_ISR_EOC14 (0x1u << 14)
	(ADC_ISR) End of Conversion 14
#define	ADC_ISR_EOC15 (0x1u << 15)
	(ADC_ISR) End of Conversion 15
#define	ADC_ISR_EOC2 (0x1u << 2)
	(ADC_ISR) End of Conversion 2
#define	ADC_ISR_EOC3 (0x1u << 3)
	(ADC_ISR) End of Conversion 3
#define	ADC_ISR_EOC4 (0x1u << 4)
	(ADC_ISR) End of Conversion 4
#define	ADC_ISR_EOC5 (0x1u << 5)
	(ADC_ISR) End of Conversion 5
#define	ADC_ISR_EOC6 (0x1u << 6)
	(ADC_ISR) End of Conversion 6
#define	ADC_ISR_EOC7 (0x1u << 7)
	(ADC_ISR) End of Conversion 7
#define	ADC_ISR_EOC8 (0x1u << 8)
	(ADC_ISR) End of Conversion 8
#define	ADC_ISR_EOC9 (0x1u << 9)
	(ADC_ISR) End of Conversion 9
#define	ADC_ISR_EOCAL (0x1u << 23)
	(ADC_ISR) End of Calibration Sequence
#define	ADC_ISR_GOVRE (0x1u << 25)
	(ADC_ISR) General Overrun Error
#define	ADC_ISR_RXBUFF (0x1u << 28)
	(ADC_ISR) RX Buffer Full
#define	ADC_LCDR_CHNB_Msk (0xfu << ADC_LCDR_CHNB_Pos)
	(ADC_LCDR) Channel Number
#define	ADC_LCDR_CHNB_Pos 12
#define	ADC_LCDR_LDATA_Msk (0xfffu << ADC_LCDR_LDATA_Pos)
	(ADC_LCDR) Last Data Converted
#define	ADC_LCDR_LDATA_Pos 0
#define	ADC_MR_ANACH (0x1u << 23)
	(ADC_MR) Analog Change
#define	ADC_MR_ANACH_ALLOWED (0x1u << 23)
	(ADC_MR) Allows different analog settings for each channel.
#define	ADC_MR_ANACH_NONE (0x0u << 23)
	(ADC_MR) No analog change on channel switching: DIFF0, GAIN0 and OFF0 are used for all channels
#define	ADC_MR_FREERUN (0x1u << 7)
	(ADC_MR) Free Run Mode
#define	ADC_MR_FREERUN_OFF (0x0u << 7)
	(ADC_MR) Normal Mode
#define	ADC_MR_FREERUN_ON (0x1u << 7)
	(ADC_MR) Free Run Mode: Never wait for any trigger.
#define	ADC_MR_FWUP (0x1u << 6)
	(ADC_MR) Fast Wake Up
#define	ADC_MR_FWUP_OFF (0x0u << 6)
	(ADC_MR) If SLEEP is 1 then both ADC Core and reference voltage circuitry are OFF between conversions
#define	ADC_MR_FWUP_ON (0x1u << 6)
	(ADC_MR) If SLEEP is 1 then Fast Wake-up Sleep Mode: The Voltage reference is ON between conversions and ADC Core is OFF
#define	ADC_MR_LOWRES (0x1u << 4)
	(ADC_MR) Resolution
#define	ADC_MR_LOWRES_BITS_10 (0x1u << 4)
	(ADC_MR) 10-bit resolution
#define	ADC_MR_LOWRES_BITS_12 (0x0u << 4)
	(ADC_MR) 12-bit resolution
#define	ADC_MR_PRESCAL(value)
#define	ADC_MR_PRESCAL_Msk (0xffu << ADC_MR_PRESCAL_Pos)
	(ADC_MR) Prescaler Rate Selection
#define	ADC_MR_PRESCAL_Pos 8
#define	ADC_MR_SETTLING_AST17 (0x3u << 20)
	(ADC_MR) 17 periods of ADCClock
#define	ADC_MR_SETTLING_AST3 (0x0u << 20)
	(ADC_MR) 3 periods of ADCClock
#define	ADC_MR_SETTLING_AST5 (0x1u << 20)
	(ADC_MR) 5 periods of ADCClock
#define	ADC_MR_SETTLING_AST9 (0x2u << 20)
	(ADC_MR) 9 periods of ADCClock
#define	ADC_MR_SETTLING_Msk (0x3u << ADC_MR_SETTLING_Pos)
	(ADC_MR) Analog Settling Time
#define	ADC_MR_SETTLING_Pos 20
#define	ADC_MR_SLEEP (0x1u << 5)
	(ADC_MR) Sleep Mode
#define	ADC_MR_SLEEP_NORMAL (0x0u << 5)
	(ADC_MR) Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions
#define	ADC_MR_SLEEP_SLEEP (0x1u << 5)
	(ADC_MR) Sleep Mode: The wake-up time can be modified by programming FWUP bit
#define	ADC_MR_STARTUP_Msk (0xfu << ADC_MR_STARTUP_Pos)
	(ADC_MR) Start Up Time
#define	ADC_MR_STARTUP_Pos 16
#define	ADC_MR_STARTUP_SUT0 (0x0u << 16)
	(ADC_MR) 0 periods of ADCClock
#define	ADC_MR_STARTUP_SUT112 (0x7u << 16)
	(ADC_MR) 112 periods of ADCClock
#define	ADC_MR_STARTUP_SUT16 (0x2u << 16)
	(ADC_MR) 16 periods of ADCClock
#define	ADC_MR_STARTUP_SUT24 (0x3u << 16)
	(ADC_MR) 24 periods of ADCClock
#define	ADC_MR_STARTUP_SUT512 (0x8u << 16)
	(ADC_MR) 512 periods of ADCClock
#define	ADC_MR_STARTUP_SUT576 (0x9u << 16)
	(ADC_MR) 576 periods of ADCClock
#define	ADC_MR_STARTUP_SUT64 (0x4u << 16)
	(ADC_MR) 64 periods of ADCClock
#define	ADC_MR_STARTUP_SUT640 (0xAu << 16)
	(ADC_MR) 640 periods of ADCClock
#define	ADC_MR_STARTUP_SUT704 (0xBu << 16)
	(ADC_MR) 704 periods of ADCClock
#define	ADC_MR_STARTUP_SUT768 (0xCu << 16)
	(ADC_MR) 768 periods of ADCClock
#define	ADC_MR_STARTUP_SUT8 (0x1u << 16)
	(ADC_MR) 8 periods of ADCClock
#define	ADC_MR_STARTUP_SUT80 (0x5u << 16)
	(ADC_MR) 80 periods of ADCClock
#define	ADC_MR_STARTUP_SUT832 (0xDu << 16)
	(ADC_MR) 832 periods of ADCClock
#define	ADC_MR_STARTUP_SUT896 (0xEu << 16)
	(ADC_MR) 896 periods of ADCClock
#define	ADC_MR_STARTUP_SUT96 (0x6u << 16)
	(ADC_MR) 96 periods of ADCClock
#define	ADC_MR_STARTUP_SUT960 (0xFu << 16)
	(ADC_MR) 960 periods of ADCClock
#define	ADC_MR_TRACKTIM(value)
#define	ADC_MR_TRACKTIM_Msk (0xfu << ADC_MR_TRACKTIM_Pos)
	(ADC_MR) Tracking Time
#define	ADC_MR_TRACKTIM_Pos 24
#define	ADC_MR_TRANSFER(value)
#define	ADC_MR_TRANSFER_Msk (0x3u << ADC_MR_TRANSFER_Pos)
	(ADC_MR) Transfer Period
#define	ADC_MR_TRANSFER_Pos 28
#define	ADC_MR_TRGEN (0x1u << 0)
	(ADC_MR) Trigger Enable
#define	ADC_MR_TRGEN_DIS (0x0u << 0)
	(ADC_MR) Hardware triggers are disabled.
#define	ADC_MR_TRGEN_EN (0x1u << 0)
	(ADC_MR) Hardware trigger selected by TRGSEL field is enabled.
#define	ADC_MR_TRGSEL_ADC_TRIG0 (0x0u << 1)
	(ADC_MR) External trigger
#define	ADC_MR_TRGSEL_ADC_TRIG1 (0x1u << 1)
	(ADC_MR) TIO Output of the Timer Counter Channel 0
#define	ADC_MR_TRGSEL_ADC_TRIG2 (0x2u << 1)
	(ADC_MR) TIO Output of the Timer Counter Channel 1
#define	ADC_MR_TRGSEL_ADC_TRIG3 (0x3u << 1)
	(ADC_MR) TIO Output of the Timer Counter Channel 2
#define	ADC_MR_TRGSEL_ADC_TRIG4 (0x4u << 1)
	(ADC_MR) PWM Event Line 0
#define	ADC_MR_TRGSEL_ADC_TRIG5 (0x5u << 1)
	(ADC_MR) PWM Event Line 1
#define	ADC_MR_TRGSEL_Msk (0x7u << ADC_MR_TRGSEL_Pos)
	(ADC_MR) Trigger Selection
#define	ADC_MR_TRGSEL_Pos 1
#define	ADC_MR_USEQ (0x1u << 31)
	(ADC_MR) Use Sequence Enable
#define	ADC_MR_USEQ_NUM_ORDER (0x0u << 31)
	(ADC_MR) Normal Mode: The controller converts channels in a simple numeric order depending only on the channel index.
#define	ADC_MR_USEQ_REG_ORDER (0x1u << 31)
	(ADC_MR) User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2 registers and can be used to convert several times the same channel.
#define	ADC_OVER_OVRE0 (0x1u << 0)
	(ADC_OVER) Overrun Error 0
#define	ADC_OVER_OVRE1 (0x1u << 1)
	(ADC_OVER) Overrun Error 1
#define	ADC_OVER_OVRE10 (0x1u << 10)
	(ADC_OVER) Overrun Error 10
#define	ADC_OVER_OVRE11 (0x1u << 11)
	(ADC_OVER) Overrun Error 11
#define	ADC_OVER_OVRE12 (0x1u << 12)
	(ADC_OVER) Overrun Error 12
#define	ADC_OVER_OVRE13 (0x1u << 13)
	(ADC_OVER) Overrun Error 13
#define	ADC_OVER_OVRE14 (0x1u << 14)
	(ADC_OVER) Overrun Error 14
#define	ADC_OVER_OVRE15 (0x1u << 15)
	(ADC_OVER) Overrun Error 15
#define	ADC_OVER_OVRE2 (0x1u << 2)
	(ADC_OVER) Overrun Error 2
#define	ADC_OVER_OVRE3 (0x1u << 3)
	(ADC_OVER) Overrun Error 3
#define	ADC_OVER_OVRE4 (0x1u << 4)
	(ADC_OVER) Overrun Error 4
#define	ADC_OVER_OVRE5 (0x1u << 5)
	(ADC_OVER) Overrun Error 5
#define	ADC_OVER_OVRE6 (0x1u << 6)
	(ADC_OVER) Overrun Error 6
#define	ADC_OVER_OVRE7 (0x1u << 7)
	(ADC_OVER) Overrun Error 7
#define	ADC_OVER_OVRE8 (0x1u << 8)
	(ADC_OVER) Overrun Error 8
#define	ADC_OVER_OVRE9 (0x1u << 9)
	(ADC_OVER) Overrun Error 9
#define	ADC_PTCR_RXTDIS (0x1u << 1)
	(ADC_PTCR) Receiver Transfer Disable
#define	ADC_PTCR_RXTEN (0x1u << 0)
	(ADC_PTCR) Receiver Transfer Enable
#define	ADC_PTCR_TXTDIS (0x1u << 9)
	(ADC_PTCR) Transmitter Transfer Disable
#define	ADC_PTCR_TXTEN (0x1u << 8)
	(ADC_PTCR) Transmitter Transfer Enable
#define	ADC_PTSR_RXTEN (0x1u << 0)
	(ADC_PTSR) Receiver Transfer Enable
#define	ADC_PTSR_TXTEN (0x1u << 8)
	(ADC_PTSR) Transmitter Transfer Enable
#define	ADC_RCR_RXCTR(value)
#define	ADC_RCR_RXCTR_Msk (0xffffu << ADC_RCR_RXCTR_Pos)
	(ADC_RCR) Receive Counter Register
#define	ADC_RCR_RXCTR_Pos 0
#define	ADC_RNCR_RXNCTR(value)
#define	ADC_RNCR_RXNCTR_Msk (0xffffu << ADC_RNCR_RXNCTR_Pos)
	(ADC_RNCR) Receive Next Counter
#define	ADC_RNCR_RXNCTR_Pos 0
#define	ADC_RNPR_RXNPTR(value)
#define	ADC_RNPR_RXNPTR_Msk (0xffffffffu << ADC_RNPR_RXNPTR_Pos)
	(ADC_RNPR) Receive Next Pointer
#define	ADC_RNPR_RXNPTR_Pos 0
#define	ADC_RPR_RXPTR(value)
#define	ADC_RPR_RXPTR_Msk (0xffffffffu << ADC_RPR_RXPTR_Pos)
	(ADC_RPR) Receive Pointer Register
#define	ADC_RPR_RXPTR_Pos 0
#define	ADC_SEQR1_USCH1(value)
#define	ADC_SEQR1_USCH1_Msk (0xfu << ADC_SEQR1_USCH1_Pos)
	(ADC_SEQR1) User Sequence Number 1
#define	ADC_SEQR1_USCH1_Pos 0
#define	ADC_SEQR1_USCH2(value)
#define	ADC_SEQR1_USCH2_Msk (0xfu << ADC_SEQR1_USCH2_Pos)
	(ADC_SEQR1) User Sequence Number 2
#define	ADC_SEQR1_USCH2_Pos 4
#define	ADC_SEQR1_USCH3(value)
#define	ADC_SEQR1_USCH3_Msk (0xfu << ADC_SEQR1_USCH3_Pos)
	(ADC_SEQR1) User Sequence Number 3
#define	ADC_SEQR1_USCH3_Pos 8
#define	ADC_SEQR1_USCH4(value)
#define	ADC_SEQR1_USCH4_Msk (0xfu << ADC_SEQR1_USCH4_Pos)
	(ADC_SEQR1) User Sequence Number 4
#define	ADC_SEQR1_USCH4_Pos 12
#define	ADC_SEQR1_USCH5(value)
#define	ADC_SEQR1_USCH5_Msk (0xfu << ADC_SEQR1_USCH5_Pos)
	(ADC_SEQR1) User Sequence Number 5
#define	ADC_SEQR1_USCH5_Pos 16
#define	ADC_SEQR1_USCH6(value)
#define	ADC_SEQR1_USCH6_Msk (0xfu << ADC_SEQR1_USCH6_Pos)
	(ADC_SEQR1) User Sequence Number 6
#define	ADC_SEQR1_USCH6_Pos 20
#define	ADC_SEQR1_USCH7(value)
#define	ADC_SEQR1_USCH7_Msk (0xfu << ADC_SEQR1_USCH7_Pos)
	(ADC_SEQR1) User Sequence Number 7
#define	ADC_SEQR1_USCH7_Pos 24
#define	ADC_SEQR1_USCH8(value)
#define	ADC_SEQR1_USCH8_Msk (0xfu << ADC_SEQR1_USCH8_Pos)
	(ADC_SEQR1) User Sequence Number 8
#define	ADC_SEQR1_USCH8_Pos 28
#define	ADC_SEQR2_USCH10(value)
#define	ADC_SEQR2_USCH10_Msk (0xfu << ADC_SEQR2_USCH10_Pos)
	(ADC_SEQR2) User Sequence Number 10
#define	ADC_SEQR2_USCH10_Pos 4
#define	ADC_SEQR2_USCH11(value)
#define	ADC_SEQR2_USCH11_Msk (0xfu << ADC_SEQR2_USCH11_Pos)
	(ADC_SEQR2) User Sequence Number 11
#define	ADC_SEQR2_USCH11_Pos 8
#define	ADC_SEQR2_USCH12(value)
#define	ADC_SEQR2_USCH12_Msk (0xfu << ADC_SEQR2_USCH12_Pos)
	(ADC_SEQR2) User Sequence Number 12
#define	ADC_SEQR2_USCH12_Pos 12
#define	ADC_SEQR2_USCH13(value)
#define	ADC_SEQR2_USCH13_Msk (0xfu << ADC_SEQR2_USCH13_Pos)
	(ADC_SEQR2) User Sequence Number 13
#define	ADC_SEQR2_USCH13_Pos 16
#define	ADC_SEQR2_USCH14(value)
#define	ADC_SEQR2_USCH14_Msk (0xfu << ADC_SEQR2_USCH14_Pos)
	(ADC_SEQR2) User Sequence Number 14
#define	ADC_SEQR2_USCH14_Pos 20
#define	ADC_SEQR2_USCH15(value)
#define	ADC_SEQR2_USCH15_Msk (0xfu << ADC_SEQR2_USCH15_Pos)
	(ADC_SEQR2) User Sequence Number 15
#define	ADC_SEQR2_USCH15_Pos 24
#define	ADC_SEQR2_USCH9(value)
#define	ADC_SEQR2_USCH9_Msk (0xfu << ADC_SEQR2_USCH9_Pos)
	(ADC_SEQR2) User Sequence Number 9
#define	ADC_SEQR2_USCH9_Pos 0
#define	ADC_WPMR_WPEN (0x1u << 0)
	(ADC_WPMR) Write Protect Enable
#define	ADC_WPMR_WPKEY_Msk (0xffffffu << ADC_WPMR_WPKEY_Pos)
	(ADC_WPMR) Write Protect KEY
#define	ADC_WPMR_WPKEY_PASSWD (0x414443u << 8)
	(ADC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0
#define	ADC_WPMR_WPKEY_Pos 8
#define	ADC_WPSR_WPVS (0x1u << 0)
	(ADC_WPSR) Write Protect Violation Status
#define	ADC_WPSR_WPVSRC_Msk (0xffffu << ADC_WPSR_WPVSRC_Pos)
	(ADC_WPSR) Write Protect Violation Source
#define	ADC_WPSR_WPVSRC_Pos 8

Detailed Description

and its subsidiaries.

\cond ASF_LICENSE

Definition in file component_adc.h.

Macro Definition Documentation

◆ ADC_ACR_IBCTL

#define ADC_ACR_IBCTL ( value )

Value:

((ADC_ACR_IBCTL_Msk & ((value) << ADC_ACR_IBCTL_Pos)))

ADC_ACR_IBCTL_Msk

#define ADC_ACR_IBCTL_Msk

(ADC_ACR) ADC Bias Current Control

Definition component_adc.h:469

ADC_ACR_IBCTL_Pos

#define ADC_ACR_IBCTL_Pos

Definition component_adc.h:468

Definition at line 470 of file component_adc.h.

Referenced by adc_set_bias_current().

◆ ADC_ACR_IBCTL_Msk

#define ADC_ACR_IBCTL_Msk (0x3u << ADC_ACR_IBCTL_Pos)

(ADC_ACR) ADC Bias Current Control

Definition at line 469 of file component_adc.h.

◆ ADC_ACR_IBCTL_Pos

#define ADC_ACR_IBCTL_Pos 8

Definition at line 468 of file component_adc.h.

◆ ADC_ACR_TSON

#define ADC_ACR_TSON (0x1u << 4)

(ADC_ACR) Temperature Sensor On

Definition at line 467 of file component_adc.h.

Referenced by adc_disable_ts(), and adc_enable_ts().

◆ ADC_CDR_DATA_Msk

#define ADC_CDR_DATA_Msk (0xfffu << ADC_CDR_DATA_Pos)

(ADC_CDR[16]) Converted Data

Definition at line 465 of file component_adc.h.

◆ ADC_CDR_DATA_Pos

#define ADC_CDR_DATA_Pos 0

Definition at line 464 of file component_adc.h.

◆ ADC_CGR_GAIN0

#define ADC_CGR_GAIN0 ( value )

Value:

((ADC_CGR_GAIN0_Msk & ((value) << ADC_CGR_GAIN0_Pos)))

ADC_CGR_GAIN0_Msk

#define ADC_CGR_GAIN0_Msk

(ADC_CGR) Gain for Channel 0

Definition component_adc.h:383

ADC_CGR_GAIN0_Pos

#define ADC_CGR_GAIN0_Pos

Definition component_adc.h:382

Definition at line 384 of file component_adc.h.

◆ ADC_CGR_GAIN0_Msk

#define ADC_CGR_GAIN0_Msk (0x3u << ADC_CGR_GAIN0_Pos)

(ADC_CGR) Gain for Channel 0

Definition at line 383 of file component_adc.h.

◆ ADC_CGR_GAIN0_Pos

#define ADC_CGR_GAIN0_Pos 0

Definition at line 382 of file component_adc.h.

◆ ADC_CGR_GAIN1

#define ADC_CGR_GAIN1 ( value )

Value:

((ADC_CGR_GAIN1_Msk & ((value) << ADC_CGR_GAIN1_Pos)))

ADC_CGR_GAIN1_Pos

#define ADC_CGR_GAIN1_Pos

Definition component_adc.h:385

ADC_CGR_GAIN1_Msk

#define ADC_CGR_GAIN1_Msk

(ADC_CGR) Gain for Channel 1

Definition component_adc.h:386

Definition at line 387 of file component_adc.h.

◆ ADC_CGR_GAIN10

#define ADC_CGR_GAIN10 ( value )

Value:

((ADC_CGR_GAIN10_Msk & ((value) << ADC_CGR_GAIN10_Pos)))

ADC_CGR_GAIN10_Pos

#define ADC_CGR_GAIN10_Pos

Definition component_adc.h:412

ADC_CGR_GAIN10_Msk

#define ADC_CGR_GAIN10_Msk

(ADC_CGR) Gain for Channel 10

Definition component_adc.h:413

Definition at line 414 of file component_adc.h.

◆ ADC_CGR_GAIN10_Msk

#define ADC_CGR_GAIN10_Msk (0x3u << ADC_CGR_GAIN10_Pos)

(ADC_CGR) Gain for Channel 10

Definition at line 413 of file component_adc.h.

◆ ADC_CGR_GAIN10_Pos

#define ADC_CGR_GAIN10_Pos 20

Definition at line 412 of file component_adc.h.

◆ ADC_CGR_GAIN11

#define ADC_CGR_GAIN11 ( value )

Value:

((ADC_CGR_GAIN11_Msk & ((value) << ADC_CGR_GAIN11_Pos)))

ADC_CGR_GAIN11_Pos

#define ADC_CGR_GAIN11_Pos

Definition component_adc.h:415

ADC_CGR_GAIN11_Msk

#define ADC_CGR_GAIN11_Msk

(ADC_CGR) Gain for Channel 11

Definition component_adc.h:416

Definition at line 417 of file component_adc.h.

◆ ADC_CGR_GAIN11_Msk

#define ADC_CGR_GAIN11_Msk (0x3u << ADC_CGR_GAIN11_Pos)

(ADC_CGR) Gain for Channel 11

Definition at line 416 of file component_adc.h.

◆ ADC_CGR_GAIN11_Pos

#define ADC_CGR_GAIN11_Pos 22

Definition at line 415 of file component_adc.h.

◆ ADC_CGR_GAIN12

#define ADC_CGR_GAIN12 ( value )

Value:

((ADC_CGR_GAIN12_Msk & ((value) << ADC_CGR_GAIN12_Pos)))

ADC_CGR_GAIN12_Msk

#define ADC_CGR_GAIN12_Msk

(ADC_CGR) Gain for Channel 12

Definition component_adc.h:419

ADC_CGR_GAIN12_Pos

#define ADC_CGR_GAIN12_Pos

Definition component_adc.h:418

Definition at line 420 of file component_adc.h.

◆ ADC_CGR_GAIN12_Msk

#define ADC_CGR_GAIN12_Msk (0x3u << ADC_CGR_GAIN12_Pos)

(ADC_CGR) Gain for Channel 12

Definition at line 419 of file component_adc.h.

◆ ADC_CGR_GAIN12_Pos

#define ADC_CGR_GAIN12_Pos 24

Definition at line 418 of file component_adc.h.

◆ ADC_CGR_GAIN13

#define ADC_CGR_GAIN13 ( value )

Value:

((ADC_CGR_GAIN13_Msk & ((value) << ADC_CGR_GAIN13_Pos)))

ADC_CGR_GAIN13_Pos

#define ADC_CGR_GAIN13_Pos

Definition component_adc.h:421

ADC_CGR_GAIN13_Msk

#define ADC_CGR_GAIN13_Msk

(ADC_CGR) Gain for Channel 13

Definition component_adc.h:422

Definition at line 423 of file component_adc.h.

◆ ADC_CGR_GAIN13_Msk

#define ADC_CGR_GAIN13_Msk (0x3u << ADC_CGR_GAIN13_Pos)

(ADC_CGR) Gain for Channel 13

Definition at line 422 of file component_adc.h.

◆ ADC_CGR_GAIN13_Pos

#define ADC_CGR_GAIN13_Pos 26

Definition at line 421 of file component_adc.h.

◆ ADC_CGR_GAIN14

#define ADC_CGR_GAIN14 ( value )

Value:

((ADC_CGR_GAIN14_Msk & ((value) << ADC_CGR_GAIN14_Pos)))

ADC_CGR_GAIN14_Msk

#define ADC_CGR_GAIN14_Msk

(ADC_CGR) Gain for Channel 14

Definition component_adc.h:425

ADC_CGR_GAIN14_Pos

#define ADC_CGR_GAIN14_Pos

Definition component_adc.h:424

Definition at line 426 of file component_adc.h.

◆ ADC_CGR_GAIN14_Msk

#define ADC_CGR_GAIN14_Msk (0x3u << ADC_CGR_GAIN14_Pos)

(ADC_CGR) Gain for Channel 14

Definition at line 425 of file component_adc.h.

◆ ADC_CGR_GAIN14_Pos

#define ADC_CGR_GAIN14_Pos 28

Definition at line 424 of file component_adc.h.

◆ ADC_CGR_GAIN15

#define ADC_CGR_GAIN15 ( value )

Value:

((ADC_CGR_GAIN15_Msk & ((value) << ADC_CGR_GAIN15_Pos)))

ADC_CGR_GAIN15_Pos

#define ADC_CGR_GAIN15_Pos

Definition component_adc.h:427

ADC_CGR_GAIN15_Msk

#define ADC_CGR_GAIN15_Msk

(ADC_CGR) Gain for Channel 15

Definition component_adc.h:428

Definition at line 429 of file component_adc.h.

◆ ADC_CGR_GAIN15_Msk

#define ADC_CGR_GAIN15_Msk (0x3u << ADC_CGR_GAIN15_Pos)

(ADC_CGR) Gain for Channel 15

Definition at line 428 of file component_adc.h.

◆ ADC_CGR_GAIN15_Pos

#define ADC_CGR_GAIN15_Pos 30

Definition at line 427 of file component_adc.h.

◆ ADC_CGR_GAIN1_Msk

#define ADC_CGR_GAIN1_Msk (0x3u << ADC_CGR_GAIN1_Pos)

(ADC_CGR) Gain for Channel 1

Definition at line 386 of file component_adc.h.

◆ ADC_CGR_GAIN1_Pos

#define ADC_CGR_GAIN1_Pos 2

Definition at line 385 of file component_adc.h.

◆ ADC_CGR_GAIN2

#define ADC_CGR_GAIN2 ( value )

Value:

((ADC_CGR_GAIN2_Msk & ((value) << ADC_CGR_GAIN2_Pos)))

ADC_CGR_GAIN2_Pos

#define ADC_CGR_GAIN2_Pos

Definition component_adc.h:388

ADC_CGR_GAIN2_Msk

#define ADC_CGR_GAIN2_Msk

(ADC_CGR) Gain for Channel 2

Definition component_adc.h:389

Definition at line 390 of file component_adc.h.

◆ ADC_CGR_GAIN2_Msk

#define ADC_CGR_GAIN2_Msk (0x3u << ADC_CGR_GAIN2_Pos)

(ADC_CGR) Gain for Channel 2

Definition at line 389 of file component_adc.h.

◆ ADC_CGR_GAIN2_Pos

#define ADC_CGR_GAIN2_Pos 4

Definition at line 388 of file component_adc.h.

◆ ADC_CGR_GAIN3

#define ADC_CGR_GAIN3 ( value )

Value:

((ADC_CGR_GAIN3_Msk & ((value) << ADC_CGR_GAIN3_Pos)))

ADC_CGR_GAIN3_Pos

#define ADC_CGR_GAIN3_Pos

Definition component_adc.h:391

ADC_CGR_GAIN3_Msk

#define ADC_CGR_GAIN3_Msk

(ADC_CGR) Gain for Channel 3

Definition component_adc.h:392

Definition at line 393 of file component_adc.h.

◆ ADC_CGR_GAIN3_Msk

#define ADC_CGR_GAIN3_Msk (0x3u << ADC_CGR_GAIN3_Pos)

(ADC_CGR) Gain for Channel 3

Definition at line 392 of file component_adc.h.

◆ ADC_CGR_GAIN3_Pos

#define ADC_CGR_GAIN3_Pos 6

Definition at line 391 of file component_adc.h.

◆ ADC_CGR_GAIN4

#define ADC_CGR_GAIN4 ( value )

Value:

((ADC_CGR_GAIN4_Msk & ((value) << ADC_CGR_GAIN4_Pos)))

ADC_CGR_GAIN4_Pos

#define ADC_CGR_GAIN4_Pos

Definition component_adc.h:394

ADC_CGR_GAIN4_Msk

#define ADC_CGR_GAIN4_Msk

(ADC_CGR) Gain for Channel 4

Definition component_adc.h:395

Definition at line 396 of file component_adc.h.

◆ ADC_CGR_GAIN4_Msk

#define ADC_CGR_GAIN4_Msk (0x3u << ADC_CGR_GAIN4_Pos)

(ADC_CGR) Gain for Channel 4

Definition at line 395 of file component_adc.h.

◆ ADC_CGR_GAIN4_Pos

#define ADC_CGR_GAIN4_Pos 8

Definition at line 394 of file component_adc.h.

◆ ADC_CGR_GAIN5

#define ADC_CGR_GAIN5 ( value )

Value:

((ADC_CGR_GAIN5_Msk & ((value) << ADC_CGR_GAIN5_Pos)))

ADC_CGR_GAIN5_Msk

#define ADC_CGR_GAIN5_Msk

(ADC_CGR) Gain for Channel 5

Definition component_adc.h:398

ADC_CGR_GAIN5_Pos

#define ADC_CGR_GAIN5_Pos

Definition component_adc.h:397

Definition at line 399 of file component_adc.h.

◆ ADC_CGR_GAIN5_Msk

#define ADC_CGR_GAIN5_Msk (0x3u << ADC_CGR_GAIN5_Pos)

(ADC_CGR) Gain for Channel 5

Definition at line 398 of file component_adc.h.

◆ ADC_CGR_GAIN5_Pos

#define ADC_CGR_GAIN5_Pos 10

Definition at line 397 of file component_adc.h.

◆ ADC_CGR_GAIN6

#define ADC_CGR_GAIN6 ( value )

Value:

((ADC_CGR_GAIN6_Msk & ((value) << ADC_CGR_GAIN6_Pos)))

ADC_CGR_GAIN6_Pos

#define ADC_CGR_GAIN6_Pos

Definition component_adc.h:400

ADC_CGR_GAIN6_Msk

#define ADC_CGR_GAIN6_Msk

(ADC_CGR) Gain for Channel 6

Definition component_adc.h:401

Definition at line 402 of file component_adc.h.

◆ ADC_CGR_GAIN6_Msk

#define ADC_CGR_GAIN6_Msk (0x3u << ADC_CGR_GAIN6_Pos)

(ADC_CGR) Gain for Channel 6

Definition at line 401 of file component_adc.h.

◆ ADC_CGR_GAIN6_Pos

#define ADC_CGR_GAIN6_Pos 12

Definition at line 400 of file component_adc.h.

◆ ADC_CGR_GAIN7

#define ADC_CGR_GAIN7 ( value )

Value:

((ADC_CGR_GAIN7_Msk & ((value) << ADC_CGR_GAIN7_Pos)))

ADC_CGR_GAIN7_Msk

#define ADC_CGR_GAIN7_Msk

(ADC_CGR) Gain for Channel 7

Definition component_adc.h:404

ADC_CGR_GAIN7_Pos

#define ADC_CGR_GAIN7_Pos

Definition component_adc.h:403

Definition at line 405 of file component_adc.h.

◆ ADC_CGR_GAIN7_Msk

#define ADC_CGR_GAIN7_Msk (0x3u << ADC_CGR_GAIN7_Pos)

(ADC_CGR) Gain for Channel 7

Definition at line 404 of file component_adc.h.

◆ ADC_CGR_GAIN7_Pos

#define ADC_CGR_GAIN7_Pos 14

Definition at line 403 of file component_adc.h.

◆ ADC_CGR_GAIN8

#define ADC_CGR_GAIN8 ( value )

Value:

((ADC_CGR_GAIN8_Msk & ((value) << ADC_CGR_GAIN8_Pos)))

ADC_CGR_GAIN8_Pos

#define ADC_CGR_GAIN8_Pos

Definition component_adc.h:406

ADC_CGR_GAIN8_Msk

#define ADC_CGR_GAIN8_Msk

(ADC_CGR) Gain for Channel 8

Definition component_adc.h:407

Definition at line 408 of file component_adc.h.

◆ ADC_CGR_GAIN8_Msk

#define ADC_CGR_GAIN8_Msk (0x3u << ADC_CGR_GAIN8_Pos)

(ADC_CGR) Gain for Channel 8

Definition at line 407 of file component_adc.h.

◆ ADC_CGR_GAIN8_Pos

#define ADC_CGR_GAIN8_Pos 16

Definition at line 406 of file component_adc.h.

◆ ADC_CGR_GAIN9

#define ADC_CGR_GAIN9 ( value )

Value:

((ADC_CGR_GAIN9_Msk & ((value) << ADC_CGR_GAIN9_Pos)))

ADC_CGR_GAIN9_Msk

#define ADC_CGR_GAIN9_Msk

(ADC_CGR) Gain for Channel 9

Definition component_adc.h:410

ADC_CGR_GAIN9_Pos

#define ADC_CGR_GAIN9_Pos

Definition component_adc.h:409

Definition at line 411 of file component_adc.h.

◆ ADC_CGR_GAIN9_Msk

#define ADC_CGR_GAIN9_Msk (0x3u << ADC_CGR_GAIN9_Pos)

(ADC_CGR) Gain for Channel 9

Definition at line 410 of file component_adc.h.

◆ ADC_CGR_GAIN9_Pos

#define ADC_CGR_GAIN9_Pos 18

Definition at line 409 of file component_adc.h.

◆ ADC_CHDR_CH0

#define ADC_CHDR_CH0 (0x1u << 0)

(ADC_CHDR) Channel 0 Disable

Definition at line 215 of file component_adc.h.

◆ ADC_CHDR_CH1

#define ADC_CHDR_CH1 (0x1u << 1)

(ADC_CHDR) Channel 1 Disable

Definition at line 216 of file component_adc.h.

◆ ADC_CHDR_CH10

#define ADC_CHDR_CH10 (0x1u << 10)

(ADC_CHDR) Channel 10 Disable

Definition at line 225 of file component_adc.h.

◆ ADC_CHDR_CH11

#define ADC_CHDR_CH11 (0x1u << 11)

(ADC_CHDR) Channel 11 Disable

Definition at line 226 of file component_adc.h.

◆ ADC_CHDR_CH12

#define ADC_CHDR_CH12 (0x1u << 12)

(ADC_CHDR) Channel 12 Disable

Definition at line 227 of file component_adc.h.

◆ ADC_CHDR_CH13

#define ADC_CHDR_CH13 (0x1u << 13)

(ADC_CHDR) Channel 13 Disable

Definition at line 228 of file component_adc.h.

◆ ADC_CHDR_CH14

#define ADC_CHDR_CH14 (0x1u << 14)

(ADC_CHDR) Channel 14 Disable

Definition at line 229 of file component_adc.h.

◆ ADC_CHDR_CH15

#define ADC_CHDR_CH15 (0x1u << 15)

(ADC_CHDR) Channel 15 Disable

Definition at line 230 of file component_adc.h.

◆ ADC_CHDR_CH2

#define ADC_CHDR_CH2 (0x1u << 2)

(ADC_CHDR) Channel 2 Disable

Definition at line 217 of file component_adc.h.

◆ ADC_CHDR_CH3

#define ADC_CHDR_CH3 (0x1u << 3)

(ADC_CHDR) Channel 3 Disable

Definition at line 218 of file component_adc.h.

◆ ADC_CHDR_CH4

#define ADC_CHDR_CH4 (0x1u << 4)

(ADC_CHDR) Channel 4 Disable

Definition at line 219 of file component_adc.h.

◆ ADC_CHDR_CH5

#define ADC_CHDR_CH5 (0x1u << 5)

(ADC_CHDR) Channel 5 Disable

Definition at line 220 of file component_adc.h.

◆ ADC_CHDR_CH6

#define ADC_CHDR_CH6 (0x1u << 6)

(ADC_CHDR) Channel 6 Disable

Definition at line 221 of file component_adc.h.

◆ ADC_CHDR_CH7

#define ADC_CHDR_CH7 (0x1u << 7)

(ADC_CHDR) Channel 7 Disable

Definition at line 222 of file component_adc.h.

◆ ADC_CHDR_CH8

#define ADC_CHDR_CH8 (0x1u << 8)

(ADC_CHDR) Channel 8 Disable

Definition at line 223 of file component_adc.h.

◆ ADC_CHDR_CH9

#define ADC_CHDR_CH9 (0x1u << 9)

(ADC_CHDR) Channel 9 Disable

Definition at line 224 of file component_adc.h.

◆ ADC_CHER_CH0

#define ADC_CHER_CH0 (0x1u << 0)

(ADC_CHER) Channel 0 Enable

Definition at line 198 of file component_adc.h.

◆ ADC_CHER_CH1

#define ADC_CHER_CH1 (0x1u << 1)

(ADC_CHER) Channel 1 Enable

Definition at line 199 of file component_adc.h.

◆ ADC_CHER_CH10

#define ADC_CHER_CH10 (0x1u << 10)

(ADC_CHER) Channel 10 Enable

Definition at line 208 of file component_adc.h.

◆ ADC_CHER_CH11

#define ADC_CHER_CH11 (0x1u << 11)

(ADC_CHER) Channel 11 Enable

Definition at line 209 of file component_adc.h.

◆ ADC_CHER_CH12

#define ADC_CHER_CH12 (0x1u << 12)

(ADC_CHER) Channel 12 Enable

Definition at line 210 of file component_adc.h.

◆ ADC_CHER_CH13

#define ADC_CHER_CH13 (0x1u << 13)

(ADC_CHER) Channel 13 Enable

Definition at line 211 of file component_adc.h.

◆ ADC_CHER_CH14

#define ADC_CHER_CH14 (0x1u << 14)

(ADC_CHER) Channel 14 Enable

Definition at line 212 of file component_adc.h.

◆ ADC_CHER_CH15

#define ADC_CHER_CH15 (0x1u << 15)

(ADC_CHER) Channel 15 Enable

Definition at line 213 of file component_adc.h.

◆ ADC_CHER_CH2

#define ADC_CHER_CH2 (0x1u << 2)

(ADC_CHER) Channel 2 Enable

Definition at line 200 of file component_adc.h.

◆ ADC_CHER_CH3

#define ADC_CHER_CH3 (0x1u << 3)

(ADC_CHER) Channel 3 Enable

Definition at line 201 of file component_adc.h.

◆ ADC_CHER_CH4

#define ADC_CHER_CH4 (0x1u << 4)

(ADC_CHER) Channel 4 Enable

Definition at line 202 of file component_adc.h.

◆ ADC_CHER_CH5

#define ADC_CHER_CH5 (0x1u << 5)

(ADC_CHER) Channel 5 Enable

Definition at line 203 of file component_adc.h.

◆ ADC_CHER_CH6

#define ADC_CHER_CH6 (0x1u << 6)

(ADC_CHER) Channel 6 Enable

Definition at line 204 of file component_adc.h.

◆ ADC_CHER_CH7

#define ADC_CHER_CH7 (0x1u << 7)

(ADC_CHER) Channel 7 Enable

Definition at line 205 of file component_adc.h.

◆ ADC_CHER_CH8

#define ADC_CHER_CH8 (0x1u << 8)

(ADC_CHER) Channel 8 Enable

Definition at line 206 of file component_adc.h.

◆ ADC_CHER_CH9

#define ADC_CHER_CH9 (0x1u << 9)

(ADC_CHER) Channel 9 Enable

Definition at line 207 of file component_adc.h.

◆ ADC_CHSR_CH0

#define ADC_CHSR_CH0 (0x1u << 0)

(ADC_CHSR) Channel 0 Status

Definition at line 232 of file component_adc.h.

◆ ADC_CHSR_CH1

#define ADC_CHSR_CH1 (0x1u << 1)

(ADC_CHSR) Channel 1 Status

Definition at line 233 of file component_adc.h.

◆ ADC_CHSR_CH10

#define ADC_CHSR_CH10 (0x1u << 10)

(ADC_CHSR) Channel 10 Status

Definition at line 242 of file component_adc.h.

◆ ADC_CHSR_CH11

#define ADC_CHSR_CH11 (0x1u << 11)

(ADC_CHSR) Channel 11 Status

Definition at line 243 of file component_adc.h.

◆ ADC_CHSR_CH12

#define ADC_CHSR_CH12 (0x1u << 12)

(ADC_CHSR) Channel 12 Status

Definition at line 244 of file component_adc.h.

◆ ADC_CHSR_CH13

#define ADC_CHSR_CH13 (0x1u << 13)

(ADC_CHSR) Channel 13 Status

Definition at line 245 of file component_adc.h.

◆ ADC_CHSR_CH14

#define ADC_CHSR_CH14 (0x1u << 14)

(ADC_CHSR) Channel 14 Status

Definition at line 246 of file component_adc.h.

◆ ADC_CHSR_CH15

#define ADC_CHSR_CH15 (0x1u << 15)

(ADC_CHSR) Channel 15 Status

Definition at line 247 of file component_adc.h.

◆ ADC_CHSR_CH2

#define ADC_CHSR_CH2 (0x1u << 2)

(ADC_CHSR) Channel 2 Status

Definition at line 234 of file component_adc.h.

◆ ADC_CHSR_CH3

#define ADC_CHSR_CH3 (0x1u << 3)

(ADC_CHSR) Channel 3 Status

Definition at line 235 of file component_adc.h.

◆ ADC_CHSR_CH4

#define ADC_CHSR_CH4 (0x1u << 4)

(ADC_CHSR) Channel 4 Status

Definition at line 236 of file component_adc.h.

◆ ADC_CHSR_CH5

#define ADC_CHSR_CH5 (0x1u << 5)

(ADC_CHSR) Channel 5 Status

Definition at line 237 of file component_adc.h.

◆ ADC_CHSR_CH6

#define ADC_CHSR_CH6 (0x1u << 6)

(ADC_CHSR) Channel 6 Status

Definition at line 238 of file component_adc.h.

◆ ADC_CHSR_CH7

#define ADC_CHSR_CH7 (0x1u << 7)

(ADC_CHSR) Channel 7 Status

Definition at line 239 of file component_adc.h.

◆ ADC_CHSR_CH8

#define ADC_CHSR_CH8 (0x1u << 8)

(ADC_CHSR) Channel 8 Status

Definition at line 240 of file component_adc.h.

◆ ADC_CHSR_CH9

#define ADC_CHSR_CH9 (0x1u << 9)

(ADC_CHSR) Channel 9 Status

Definition at line 241 of file component_adc.h.

◆ ADC_COR_DIFF0

#define ADC_COR_DIFF0 (0x1u << 16)

(ADC_COR) Differential inputs for channel 0

Definition at line 447 of file component_adc.h.

◆ ADC_COR_DIFF1

#define ADC_COR_DIFF1 (0x1u << 17)

(ADC_COR) Differential inputs for channel 1

Definition at line 448 of file component_adc.h.

◆ ADC_COR_DIFF10

#define ADC_COR_DIFF10 (0x1u << 26)

(ADC_COR) Differential inputs for channel 10

Definition at line 457 of file component_adc.h.

◆ ADC_COR_DIFF11

#define ADC_COR_DIFF11 (0x1u << 27)

(ADC_COR) Differential inputs for channel 11

Definition at line 458 of file component_adc.h.

◆ ADC_COR_DIFF12

#define ADC_COR_DIFF12 (0x1u << 28)

(ADC_COR) Differential inputs for channel 12

Definition at line 459 of file component_adc.h.

◆ ADC_COR_DIFF13

#define ADC_COR_DIFF13 (0x1u << 29)

(ADC_COR) Differential inputs for channel 13

Definition at line 460 of file component_adc.h.

◆ ADC_COR_DIFF14

#define ADC_COR_DIFF14 (0x1u << 30)

(ADC_COR) Differential inputs for channel 14

Definition at line 461 of file component_adc.h.

◆ ADC_COR_DIFF15

#define ADC_COR_DIFF15 (0x1u << 31)

(ADC_COR) Differential inputs for channel 15

Definition at line 462 of file component_adc.h.

◆ ADC_COR_DIFF2

#define ADC_COR_DIFF2 (0x1u << 18)

(ADC_COR) Differential inputs for channel 2

Definition at line 449 of file component_adc.h.

◆ ADC_COR_DIFF3

#define ADC_COR_DIFF3 (0x1u << 19)

(ADC_COR) Differential inputs for channel 3

Definition at line 450 of file component_adc.h.

◆ ADC_COR_DIFF4

#define ADC_COR_DIFF4 (0x1u << 20)

(ADC_COR) Differential inputs for channel 4

Definition at line 451 of file component_adc.h.

◆ ADC_COR_DIFF5

#define ADC_COR_DIFF5 (0x1u << 21)

(ADC_COR) Differential inputs for channel 5

Definition at line 452 of file component_adc.h.

◆ ADC_COR_DIFF6

#define ADC_COR_DIFF6 (0x1u << 22)

(ADC_COR) Differential inputs for channel 6

Definition at line 453 of file component_adc.h.

◆ ADC_COR_DIFF7

#define ADC_COR_DIFF7 (0x1u << 23)

(ADC_COR) Differential inputs for channel 7

Definition at line 454 of file component_adc.h.

◆ ADC_COR_DIFF8

#define ADC_COR_DIFF8 (0x1u << 24)

(ADC_COR) Differential inputs for channel 8

Definition at line 455 of file component_adc.h.

◆ ADC_COR_DIFF9

#define ADC_COR_DIFF9 (0x1u << 25)

(ADC_COR) Differential inputs for channel 9

Definition at line 456 of file component_adc.h.

◆ ADC_COR_OFF0

#define ADC_COR_OFF0 (0x1u << 0)

(ADC_COR) Offset for channel 0

Definition at line 431 of file component_adc.h.

◆ ADC_COR_OFF1

#define ADC_COR_OFF1 (0x1u << 1)

(ADC_COR) Offset for channel 1

Definition at line 432 of file component_adc.h.

◆ ADC_COR_OFF10

#define ADC_COR_OFF10 (0x1u << 10)

(ADC_COR) Offset for channel 10

Definition at line 441 of file component_adc.h.

◆ ADC_COR_OFF11

#define ADC_COR_OFF11 (0x1u << 11)

(ADC_COR) Offset for channel 11

Definition at line 442 of file component_adc.h.

◆ ADC_COR_OFF12

#define ADC_COR_OFF12 (0x1u << 12)

(ADC_COR) Offset for channel 12

Definition at line 443 of file component_adc.h.

◆ ADC_COR_OFF13

#define ADC_COR_OFF13 (0x1u << 13)

(ADC_COR) Offset for channel 13

Definition at line 444 of file component_adc.h.

◆ ADC_COR_OFF14

#define ADC_COR_OFF14 (0x1u << 14)

(ADC_COR) Offset for channel 14

Definition at line 445 of file component_adc.h.

◆ ADC_COR_OFF15

#define ADC_COR_OFF15 (0x1u << 15)

(ADC_COR) Offset for channel 15

Definition at line 446 of file component_adc.h.

◆ ADC_COR_OFF2

#define ADC_COR_OFF2 (0x1u << 2)

(ADC_COR) Offset for channel 2

Definition at line 433 of file component_adc.h.

◆ ADC_COR_OFF3

#define ADC_COR_OFF3 (0x1u << 3)

(ADC_COR) Offset for channel 3

Definition at line 434 of file component_adc.h.

◆ ADC_COR_OFF4

#define ADC_COR_OFF4 (0x1u << 4)

(ADC_COR) Offset for channel 4

Definition at line 435 of file component_adc.h.

◆ ADC_COR_OFF5

#define ADC_COR_OFF5 (0x1u << 5)

(ADC_COR) Offset for channel 5

Definition at line 436 of file component_adc.h.

◆ ADC_COR_OFF6

#define ADC_COR_OFF6 (0x1u << 6)

(ADC_COR) Offset for channel 6

Definition at line 437 of file component_adc.h.

◆ ADC_COR_OFF7

#define ADC_COR_OFF7 (0x1u << 7)

(ADC_COR) Offset for channel 7

Definition at line 438 of file component_adc.h.

◆ ADC_COR_OFF8

#define ADC_COR_OFF8 (0x1u << 8)

(ADC_COR) Offset for channel 8

Definition at line 439 of file component_adc.h.

◆ ADC_COR_OFF9

#define ADC_COR_OFF9 (0x1u << 9)

(ADC_COR) Offset for channel 9

Definition at line 440 of file component_adc.h.

◆ ADC_CR_AUTOCAL

#define ADC_CR_AUTOCAL (0x1u << 3)

(ADC_CR) Automatic Calibration of ADC

Definition at line 86 of file component_adc.h.

Referenced by adc_set_calibmode().

◆ ADC_CR_START

#define ADC_CR_START (0x1u << 1)

(ADC_CR) Start Conversion

Definition at line 85 of file component_adc.h.

Referenced by adc_start().

◆ ADC_CR_SWRST

#define ADC_CR_SWRST (0x1u << 0)

(ADC_CR) Software Reset

Definition at line 84 of file component_adc.h.

Referenced by adc_init(), and adc_reset().

◆ ADC_CWR_HIGHTHRES

#define ADC_CWR_HIGHTHRES ( value )

Value:

((ADC_CWR_HIGHTHRES_Msk & ((value) << ADC_CWR_HIGHTHRES_Pos)))

ADC_CWR_HIGHTHRES_Pos

#define ADC_CWR_HIGHTHRES_Pos

Definition component_adc.h:378

ADC_CWR_HIGHTHRES_Msk

#define ADC_CWR_HIGHTHRES_Msk

(ADC_CWR) High Threshold

Definition component_adc.h:379

Definition at line 380 of file component_adc.h.

Referenced by adc_set_comparison_window().

◆ ADC_CWR_HIGHTHRES_Msk

#define ADC_CWR_HIGHTHRES_Msk (0xfffu << ADC_CWR_HIGHTHRES_Pos)

(ADC_CWR) High Threshold

Definition at line 379 of file component_adc.h.

◆ ADC_CWR_HIGHTHRES_Pos

#define ADC_CWR_HIGHTHRES_Pos 16

Definition at line 378 of file component_adc.h.

◆ ADC_CWR_LOWTHRES

#define ADC_CWR_LOWTHRES ( value )

Value:

((ADC_CWR_LOWTHRES_Msk & ((value) << ADC_CWR_LOWTHRES_Pos)))

ADC_CWR_LOWTHRES_Pos

#define ADC_CWR_LOWTHRES_Pos

Definition component_adc.h:375

ADC_CWR_LOWTHRES_Msk

#define ADC_CWR_LOWTHRES_Msk

(ADC_CWR) Low Threshold

Definition component_adc.h:376

Definition at line 377 of file component_adc.h.

Referenced by adc_set_comparison_window().

◆ ADC_CWR_LOWTHRES_Msk

#define ADC_CWR_LOWTHRES_Msk (0xfffu << ADC_CWR_LOWTHRES_Pos)

(ADC_CWR) Low Threshold

Definition at line 376 of file component_adc.h.

◆ ADC_CWR_LOWTHRES_Pos

#define ADC_CWR_LOWTHRES_Pos 0

Definition at line 375 of file component_adc.h.

◆ ADC_EMR_CMPALL

#define ADC_EMR_CMPALL (0x1u << 9)

(ADC_EMR) Compare All Channels

Definition at line 372 of file component_adc.h.

Referenced by adc_set_comparison_channel().

◆ ADC_EMR_CMPMODE_HIGH

#define ADC_EMR_CMPMODE_HIGH (0x1u << 0)

(ADC_EMR) Generates an event when the converted data is higher than the high threshold of the window.

Definition at line 366 of file component_adc.h.

◆ ADC_EMR_CMPMODE_IN

#define ADC_EMR_CMPMODE_IN (0x2u << 0)

(ADC_EMR) Generates an event when the converted data is in the comparison window.

Definition at line 367 of file component_adc.h.

◆ ADC_EMR_CMPMODE_LOW

#define ADC_EMR_CMPMODE_LOW (0x0u << 0)

(ADC_EMR) Generates an event when the converted data is lower than the low threshold of the window.

Definition at line 365 of file component_adc.h.

◆ ADC_EMR_CMPMODE_Msk

#define ADC_EMR_CMPMODE_Msk (0x3u << ADC_EMR_CMPMODE_Pos)

(ADC_EMR) Comparison Mode

Definition at line 364 of file component_adc.h.

Referenced by adc_get_comparison_mode(), and adc_set_comparison_mode().

◆ ADC_EMR_CMPMODE_OUT

#define ADC_EMR_CMPMODE_OUT (0x3u << 0)

(ADC_EMR) Generates an event when the converted data is out of the comparison window.

Definition at line 368 of file component_adc.h.

◆ ADC_EMR_CMPMODE_Pos

#define ADC_EMR_CMPMODE_Pos 0

Definition at line 363 of file component_adc.h.

◆ ADC_EMR_CMPSEL

#define ADC_EMR_CMPSEL ( value )

Value:

((ADC_EMR_CMPSEL_Msk & ((value) << ADC_EMR_CMPSEL_Pos)))

ADC_EMR_CMPSEL_Pos

#define ADC_EMR_CMPSEL_Pos

Definition component_adc.h:369

ADC_EMR_CMPSEL_Msk

#define ADC_EMR_CMPSEL_Msk

(ADC_EMR) Comparison Selected Channel

Definition component_adc.h:370

Definition at line 371 of file component_adc.h.

◆ ADC_EMR_CMPSEL_Msk

#define ADC_EMR_CMPSEL_Msk (0xfu << ADC_EMR_CMPSEL_Pos)

(ADC_EMR) Comparison Selected Channel

Definition at line 370 of file component_adc.h.

Referenced by adc_set_comparison_channel().

◆ ADC_EMR_CMPSEL_Pos

#define ADC_EMR_CMPSEL_Pos 4

Definition at line 369 of file component_adc.h.

Referenced by adc_set_comparison_channel().

◆ ADC_EMR_TAG

#define ADC_EMR_TAG (0x1u << 24)

(ADC_EMR) TAG of the ADC_LDCR register

Definition at line 373 of file component_adc.h.

Referenced by adc_disable_tag(), and adc_enable_tag().

◆ ADC_IDR_COMPE

#define ADC_IDR_COMPE (0x1u << 26)

(ADC_IDR) Comparison Event Interrupt Disable

Definition at line 296 of file component_adc.h.

◆ ADC_IDR_DRDY

#define ADC_IDR_DRDY (0x1u << 24)

(ADC_IDR) Data Ready Interrupt Disable

Definition at line 294 of file component_adc.h.

◆ ADC_IDR_ENDRX

#define ADC_IDR_ENDRX (0x1u << 27)

(ADC_IDR) End of Receive Buffer Interrupt Disable

Definition at line 297 of file component_adc.h.

◆ ADC_IDR_EOC0

#define ADC_IDR_EOC0 (0x1u << 0)

(ADC_IDR) End of Conversion Interrupt Disable 0

Definition at line 277 of file component_adc.h.

◆ ADC_IDR_EOC1

#define ADC_IDR_EOC1 (0x1u << 1)

(ADC_IDR) End of Conversion Interrupt Disable 1

Definition at line 278 of file component_adc.h.

◆ ADC_IDR_EOC10

#define ADC_IDR_EOC10 (0x1u << 10)

(ADC_IDR) End of Conversion Interrupt Disable 10

Definition at line 287 of file component_adc.h.

◆ ADC_IDR_EOC11

#define ADC_IDR_EOC11 (0x1u << 11)

(ADC_IDR) End of Conversion Interrupt Disable 11

Definition at line 288 of file component_adc.h.

◆ ADC_IDR_EOC12

#define ADC_IDR_EOC12 (0x1u << 12)

(ADC_IDR) End of Conversion Interrupt Disable 12

Definition at line 289 of file component_adc.h.

◆ ADC_IDR_EOC13

#define ADC_IDR_EOC13 (0x1u << 13)

(ADC_IDR) End of Conversion Interrupt Disable 13

Definition at line 290 of file component_adc.h.

◆ ADC_IDR_EOC14

#define ADC_IDR_EOC14 (0x1u << 14)

(ADC_IDR) End of Conversion Interrupt Disable 14

Definition at line 291 of file component_adc.h.

◆ ADC_IDR_EOC15

#define ADC_IDR_EOC15 (0x1u << 15)

(ADC_IDR) End of Conversion Interrupt Disable 15

Definition at line 292 of file component_adc.h.

◆ ADC_IDR_EOC2

#define ADC_IDR_EOC2 (0x1u << 2)

(ADC_IDR) End of Conversion Interrupt Disable 2

Definition at line 279 of file component_adc.h.

◆ ADC_IDR_EOC3

#define ADC_IDR_EOC3 (0x1u << 3)

(ADC_IDR) End of Conversion Interrupt Disable 3

Definition at line 280 of file component_adc.h.

◆ ADC_IDR_EOC4

#define ADC_IDR_EOC4 (0x1u << 4)

(ADC_IDR) End of Conversion Interrupt Disable 4

Definition at line 281 of file component_adc.h.

◆ ADC_IDR_EOC5

#define ADC_IDR_EOC5 (0x1u << 5)

(ADC_IDR) End of Conversion Interrupt Disable 5

Definition at line 282 of file component_adc.h.

◆ ADC_IDR_EOC6

#define ADC_IDR_EOC6 (0x1u << 6)

(ADC_IDR) End of Conversion Interrupt Disable 6

Definition at line 283 of file component_adc.h.

◆ ADC_IDR_EOC7

#define ADC_IDR_EOC7 (0x1u << 7)

(ADC_IDR) End of Conversion Interrupt Disable 7

Definition at line 284 of file component_adc.h.

◆ ADC_IDR_EOC8

#define ADC_IDR_EOC8 (0x1u << 8)

(ADC_IDR) End of Conversion Interrupt Disable 8

Definition at line 285 of file component_adc.h.

◆ ADC_IDR_EOC9

#define ADC_IDR_EOC9 (0x1u << 9)

(ADC_IDR) End of Conversion Interrupt Disable 9

Definition at line 286 of file component_adc.h.

◆ ADC_IDR_EOCAL

#define ADC_IDR_EOCAL (0x1u << 23)

(ADC_IDR) End of Calibration Sequence

Definition at line 293 of file component_adc.h.

◆ ADC_IDR_GOVRE

#define ADC_IDR_GOVRE (0x1u << 25)

(ADC_IDR) General Overrun Error Interrupt Disable

Definition at line 295 of file component_adc.h.

◆ ADC_IDR_RXBUFF

#define ADC_IDR_RXBUFF (0x1u << 28)

(ADC_IDR) Receive Buffer Full Interrupt Disable

Definition at line 298 of file component_adc.h.

◆ ADC_IER_COMPE

#define ADC_IER_COMPE (0x1u << 26)

(ADC_IER) Comparison Event Interrupt Enable

Definition at line 273 of file component_adc.h.

◆ ADC_IER_DRDY

#define ADC_IER_DRDY (0x1u << 24)

(ADC_IER) Data Ready Interrupt Enable

Definition at line 271 of file component_adc.h.

◆ ADC_IER_ENDRX

#define ADC_IER_ENDRX (0x1u << 27)

(ADC_IER) End of Receive Buffer Interrupt Enable

Definition at line 274 of file component_adc.h.

◆ ADC_IER_EOC0

#define ADC_IER_EOC0 (0x1u << 0)

(ADC_IER) End of Conversion Interrupt Enable 0

Definition at line 254 of file component_adc.h.

◆ ADC_IER_EOC1

#define ADC_IER_EOC1 (0x1u << 1)

(ADC_IER) End of Conversion Interrupt Enable 1

Definition at line 255 of file component_adc.h.

◆ ADC_IER_EOC10

#define ADC_IER_EOC10 (0x1u << 10)

(ADC_IER) End of Conversion Interrupt Enable 10

Definition at line 264 of file component_adc.h.

◆ ADC_IER_EOC11

#define ADC_IER_EOC11 (0x1u << 11)

(ADC_IER) End of Conversion Interrupt Enable 11

Definition at line 265 of file component_adc.h.

◆ ADC_IER_EOC12

#define ADC_IER_EOC12 (0x1u << 12)

(ADC_IER) End of Conversion Interrupt Enable 12

Definition at line 266 of file component_adc.h.

◆ ADC_IER_EOC13

#define ADC_IER_EOC13 (0x1u << 13)

(ADC_IER) End of Conversion Interrupt Enable 13

Definition at line 267 of file component_adc.h.

◆ ADC_IER_EOC14

#define ADC_IER_EOC14 (0x1u << 14)

(ADC_IER) End of Conversion Interrupt Enable 14

Definition at line 268 of file component_adc.h.

◆ ADC_IER_EOC15

#define ADC_IER_EOC15 (0x1u << 15)

(ADC_IER) End of Conversion Interrupt Enable 15

Definition at line 269 of file component_adc.h.

◆ ADC_IER_EOC2

#define ADC_IER_EOC2 (0x1u << 2)

(ADC_IER) End of Conversion Interrupt Enable 2

Definition at line 256 of file component_adc.h.

◆ ADC_IER_EOC3

#define ADC_IER_EOC3 (0x1u << 3)

(ADC_IER) End of Conversion Interrupt Enable 3

Definition at line 257 of file component_adc.h.

◆ ADC_IER_EOC4

#define ADC_IER_EOC4 (0x1u << 4)

(ADC_IER) End of Conversion Interrupt Enable 4

Definition at line 258 of file component_adc.h.

◆ ADC_IER_EOC5

#define ADC_IER_EOC5 (0x1u << 5)

(ADC_IER) End of Conversion Interrupt Enable 5

Definition at line 259 of file component_adc.h.

◆ ADC_IER_EOC6

#define ADC_IER_EOC6 (0x1u << 6)

(ADC_IER) End of Conversion Interrupt Enable 6

Definition at line 260 of file component_adc.h.

◆ ADC_IER_EOC7

#define ADC_IER_EOC7 (0x1u << 7)

(ADC_IER) End of Conversion Interrupt Enable 7

Definition at line 261 of file component_adc.h.

◆ ADC_IER_EOC8

#define ADC_IER_EOC8 (0x1u << 8)

(ADC_IER) End of Conversion Interrupt Enable 8

Definition at line 262 of file component_adc.h.

◆ ADC_IER_EOC9

#define ADC_IER_EOC9 (0x1u << 9)

(ADC_IER) End of Conversion Interrupt Enable 9

Definition at line 263 of file component_adc.h.

◆ ADC_IER_EOCAL

#define ADC_IER_EOCAL (0x1u << 23)

(ADC_IER) End of Calibration Sequence

Definition at line 270 of file component_adc.h.

◆ ADC_IER_GOVRE

#define ADC_IER_GOVRE (0x1u << 25)

(ADC_IER) General Overrun Error Interrupt Enable

Definition at line 272 of file component_adc.h.

◆ ADC_IER_RXBUFF

#define ADC_IER_RXBUFF (0x1u << 28)

(ADC_IER) Receive Buffer Full Interrupt Enable

Definition at line 275 of file component_adc.h.

◆ ADC_IMR_COMPE

#define ADC_IMR_COMPE (0x1u << 26)

(ADC_IMR) Comparison Event Interrupt Mask

Definition at line 319 of file component_adc.h.

◆ ADC_IMR_DRDY

#define ADC_IMR_DRDY (0x1u << 24)

(ADC_IMR) Data Ready Interrupt Mask

Definition at line 317 of file component_adc.h.

◆ ADC_IMR_ENDRX

#define ADC_IMR_ENDRX (0x1u << 27)

(ADC_IMR) End of Receive Buffer Interrupt Mask

Definition at line 320 of file component_adc.h.

◆ ADC_IMR_EOC0

#define ADC_IMR_EOC0 (0x1u << 0)

(ADC_IMR) End of Conversion Interrupt Mask 0

Definition at line 300 of file component_adc.h.

◆ ADC_IMR_EOC1

#define ADC_IMR_EOC1 (0x1u << 1)

(ADC_IMR) End of Conversion Interrupt Mask 1

Definition at line 301 of file component_adc.h.

◆ ADC_IMR_EOC10

#define ADC_IMR_EOC10 (0x1u << 10)

(ADC_IMR) End of Conversion Interrupt Mask 10

Definition at line 310 of file component_adc.h.

◆ ADC_IMR_EOC11

#define ADC_IMR_EOC11 (0x1u << 11)

(ADC_IMR) End of Conversion Interrupt Mask 11

Definition at line 311 of file component_adc.h.

◆ ADC_IMR_EOC12

#define ADC_IMR_EOC12 (0x1u << 12)

(ADC_IMR) End of Conversion Interrupt Mask 12

Definition at line 312 of file component_adc.h.

◆ ADC_IMR_EOC13

#define ADC_IMR_EOC13 (0x1u << 13)

(ADC_IMR) End of Conversion Interrupt Mask 13

Definition at line 313 of file component_adc.h.

◆ ADC_IMR_EOC14

#define ADC_IMR_EOC14 (0x1u << 14)

(ADC_IMR) End of Conversion Interrupt Mask 14

Definition at line 314 of file component_adc.h.

◆ ADC_IMR_EOC15

#define ADC_IMR_EOC15 (0x1u << 15)

(ADC_IMR) End of Conversion Interrupt Mask 15

Definition at line 315 of file component_adc.h.

◆ ADC_IMR_EOC2

#define ADC_IMR_EOC2 (0x1u << 2)

(ADC_IMR) End of Conversion Interrupt Mask 2

Definition at line 302 of file component_adc.h.

◆ ADC_IMR_EOC3

#define ADC_IMR_EOC3 (0x1u << 3)

(ADC_IMR) End of Conversion Interrupt Mask 3

Definition at line 303 of file component_adc.h.

◆ ADC_IMR_EOC4

#define ADC_IMR_EOC4 (0x1u << 4)

(ADC_IMR) End of Conversion Interrupt Mask 4

Definition at line 304 of file component_adc.h.

◆ ADC_IMR_EOC5

#define ADC_IMR_EOC5 (0x1u << 5)

(ADC_IMR) End of Conversion Interrupt Mask 5

Definition at line 305 of file component_adc.h.

◆ ADC_IMR_EOC6

#define ADC_IMR_EOC6 (0x1u << 6)

(ADC_IMR) End of Conversion Interrupt Mask 6

Definition at line 306 of file component_adc.h.

◆ ADC_IMR_EOC7

#define ADC_IMR_EOC7 (0x1u << 7)

(ADC_IMR) End of Conversion Interrupt Mask 7

Definition at line 307 of file component_adc.h.

◆ ADC_IMR_EOC8

#define ADC_IMR_EOC8 (0x1u << 8)

(ADC_IMR) End of Conversion Interrupt Mask 8

Definition at line 308 of file component_adc.h.

◆ ADC_IMR_EOC9

#define ADC_IMR_EOC9 (0x1u << 9)

(ADC_IMR) End of Conversion Interrupt Mask 9

Definition at line 309 of file component_adc.h.

◆ ADC_IMR_EOCAL

#define ADC_IMR_EOCAL (0x1u << 23)

(ADC_IMR) End of Calibration Sequence

Definition at line 316 of file component_adc.h.

◆ ADC_IMR_GOVRE

#define ADC_IMR_GOVRE (0x1u << 25)

(ADC_IMR) General Overrun Error Interrupt Mask

Definition at line 318 of file component_adc.h.

◆ ADC_IMR_RXBUFF

#define ADC_IMR_RXBUFF (0x1u << 28)

(ADC_IMR) Receive Buffer Full Interrupt Mask

Definition at line 321 of file component_adc.h.

◆ ADC_ISR_COMPE

#define ADC_ISR_COMPE (0x1u << 26)

(ADC_ISR) Comparison Error

Definition at line 342 of file component_adc.h.

◆ ADC_ISR_DRDY

#define ADC_ISR_DRDY (0x1u << 24)

(ADC_ISR) Data Ready

Definition at line 340 of file component_adc.h.

◆ ADC_ISR_ENDRX

#define ADC_ISR_ENDRX (0x1u << 27)

(ADC_ISR) End of RX Buffer

Definition at line 343 of file component_adc.h.

◆ ADC_ISR_EOC0

#define ADC_ISR_EOC0 (0x1u << 0)

(ADC_ISR) End of Conversion 0

Definition at line 323 of file component_adc.h.

◆ ADC_ISR_EOC1

#define ADC_ISR_EOC1 (0x1u << 1)

(ADC_ISR) End of Conversion 1

Definition at line 324 of file component_adc.h.

◆ ADC_ISR_EOC10

#define ADC_ISR_EOC10 (0x1u << 10)

(ADC_ISR) End of Conversion 10

Definition at line 333 of file component_adc.h.

◆ ADC_ISR_EOC11

#define ADC_ISR_EOC11 (0x1u << 11)

(ADC_ISR) End of Conversion 11

Definition at line 334 of file component_adc.h.

◆ ADC_ISR_EOC12

#define ADC_ISR_EOC12 (0x1u << 12)

(ADC_ISR) End of Conversion 12

Definition at line 335 of file component_adc.h.

◆ ADC_ISR_EOC13

#define ADC_ISR_EOC13 (0x1u << 13)

(ADC_ISR) End of Conversion 13

Definition at line 336 of file component_adc.h.

◆ ADC_ISR_EOC14

#define ADC_ISR_EOC14 (0x1u << 14)

(ADC_ISR) End of Conversion 14

Definition at line 337 of file component_adc.h.

◆ ADC_ISR_EOC15

#define ADC_ISR_EOC15 (0x1u << 15)

(ADC_ISR) End of Conversion 15

Definition at line 338 of file component_adc.h.

◆ ADC_ISR_EOC2

#define ADC_ISR_EOC2 (0x1u << 2)

(ADC_ISR) End of Conversion 2

Definition at line 325 of file component_adc.h.

◆ ADC_ISR_EOC3

#define ADC_ISR_EOC3 (0x1u << 3)

(ADC_ISR) End of Conversion 3

Definition at line 326 of file component_adc.h.

◆ ADC_ISR_EOC4

#define ADC_ISR_EOC4 (0x1u << 4)

(ADC_ISR) End of Conversion 4

Definition at line 327 of file component_adc.h.

◆ ADC_ISR_EOC5

#define ADC_ISR_EOC5 (0x1u << 5)

(ADC_ISR) End of Conversion 5

Definition at line 328 of file component_adc.h.

◆ ADC_ISR_EOC6

#define ADC_ISR_EOC6 (0x1u << 6)

(ADC_ISR) End of Conversion 6

Definition at line 329 of file component_adc.h.

◆ ADC_ISR_EOC7

#define ADC_ISR_EOC7 (0x1u << 7)

(ADC_ISR) End of Conversion 7

Definition at line 330 of file component_adc.h.

◆ ADC_ISR_EOC8

#define ADC_ISR_EOC8 (0x1u << 8)

(ADC_ISR) End of Conversion 8

Definition at line 331 of file component_adc.h.

◆ ADC_ISR_EOC9

#define ADC_ISR_EOC9 (0x1u << 9)

(ADC_ISR) End of Conversion 9

Definition at line 332 of file component_adc.h.

◆ ADC_ISR_EOCAL

#define ADC_ISR_EOCAL (0x1u << 23)

(ADC_ISR) End of Calibration Sequence

Definition at line 339 of file component_adc.h.

◆ ADC_ISR_GOVRE

#define ADC_ISR_GOVRE (0x1u << 25)

(ADC_ISR) General Overrun Error

Definition at line 341 of file component_adc.h.

◆ ADC_ISR_RXBUFF

#define ADC_ISR_RXBUFF (0x1u << 28)

(ADC_ISR) RX Buffer Full

Definition at line 344 of file component_adc.h.

◆ ADC_LCDR_CHNB_Msk

#define ADC_LCDR_CHNB_Msk (0xfu << ADC_LCDR_CHNB_Pos)

(ADC_LCDR) Channel Number

Definition at line 252 of file component_adc.h.

Referenced by adc_get_tag().

◆ ADC_LCDR_CHNB_Pos

#define ADC_LCDR_CHNB_Pos 12

Definition at line 251 of file component_adc.h.

Referenced by adc_get_tag().

◆ ADC_LCDR_LDATA_Msk

#define ADC_LCDR_LDATA_Msk (0xfffu << ADC_LCDR_LDATA_Pos)

(ADC_LCDR) Last Data Converted

Definition at line 250 of file component_adc.h.

◆ ADC_LCDR_LDATA_Pos

#define ADC_LCDR_LDATA_Pos 0

Definition at line 249 of file component_adc.h.

◆ ADC_MR_ANACH

#define ADC_MR_ANACH (0x1u << 23)

(ADC_MR) Analog Change

Definition at line 138 of file component_adc.h.

Referenced by adc_disable_anch(), and adc_enable_anch().

◆ ADC_MR_ANACH_ALLOWED

#define ADC_MR_ANACH_ALLOWED (0x1u << 23)

(ADC_MR) Allows different analog settings for each channel.

See ADC_CGR and ADC_COR Registers

Definition at line 140 of file component_adc.h.

◆ ADC_MR_ANACH_NONE

#define ADC_MR_ANACH_NONE (0x0u << 23)

(ADC_MR) No analog change on channel switching: DIFF0, GAIN0 and OFF0 are used for all channels

Definition at line 139 of file component_adc.h.

◆ ADC_MR_FREERUN

#define ADC_MR_FREERUN (0x1u << 7)

(ADC_MR) Free Run Mode

Definition at line 108 of file component_adc.h.

Referenced by adc_configure_trigger().

◆ ADC_MR_FREERUN_OFF

#define ADC_MR_FREERUN_OFF (0x0u << 7)

(ADC_MR) Normal Mode

Definition at line 109 of file component_adc.h.

◆ ADC_MR_FREERUN_ON

#define ADC_MR_FREERUN_ON (0x1u << 7)

(ADC_MR) Free Run Mode: Never wait for any trigger.

Definition at line 110 of file component_adc.h.

Referenced by adc_check().

◆ ADC_MR_FWUP

#define ADC_MR_FWUP (0x1u << 6)

(ADC_MR) Fast Wake Up

Definition at line 105 of file component_adc.h.

Referenced by adc_configure_power_save().

◆ ADC_MR_FWUP_OFF

#define ADC_MR_FWUP_OFF (0x0u << 6)

(ADC_MR) If SLEEP is 1 then both ADC Core and reference voltage circuitry are OFF between conversions

Definition at line 106 of file component_adc.h.

◆ ADC_MR_FWUP_ON

#define ADC_MR_FWUP_ON (0x1u << 6)

(ADC_MR) If SLEEP is 1 then Fast Wake-up Sleep Mode: The Voltage reference is ON between conversions and ADC Core is OFF

Definition at line 107 of file component_adc.h.

Referenced by adc_check().

◆ ADC_MR_LOWRES

#define ADC_MR_LOWRES (0x1u << 4)

(ADC_MR) Resolution

Definition at line 99 of file component_adc.h.

Referenced by adc_set_resolution().

◆ ADC_MR_LOWRES_BITS_10

#define ADC_MR_LOWRES_BITS_10 (0x1u << 4)

(ADC_MR) 10-bit resolution

Definition at line 101 of file component_adc.h.

◆ ADC_MR_LOWRES_BITS_12

#define ADC_MR_LOWRES_BITS_12 (0x0u << 4)

(ADC_MR) 12-bit resolution

Definition at line 100 of file component_adc.h.

◆ ADC_MR_PRESCAL

#define ADC_MR_PRESCAL ( value )

Value:

((ADC_MR_PRESCAL_Msk & ((value) << ADC_MR_PRESCAL_Pos)))

ADC_MR_PRESCAL_Pos

#define ADC_MR_PRESCAL_Pos

Definition component_adc.h:111

ADC_MR_PRESCAL_Msk

#define ADC_MR_PRESCAL_Msk

(ADC_MR) Prescaler Rate Selection

Definition component_adc.h:112

Definition at line 113 of file component_adc.h.

Referenced by adc_init().

◆ ADC_MR_PRESCAL_Msk

#define ADC_MR_PRESCAL_Msk (0xffu << ADC_MR_PRESCAL_Pos)

(ADC_MR) Prescaler Rate Selection

Definition at line 112 of file component_adc.h.

Referenced by adc_check(), and adc_get_actual_adc_clock().

◆ ADC_MR_PRESCAL_Pos

#define ADC_MR_PRESCAL_Pos 8

Definition at line 111 of file component_adc.h.

Referenced by adc_check(), and adc_get_actual_adc_clock().

◆ ADC_MR_SETTLING_AST17

#define ADC_MR_SETTLING_AST17 (0x3u << 20)

(ADC_MR) 17 periods of ADCClock

Definition at line 137 of file component_adc.h.

◆ ADC_MR_SETTLING_AST3

#define ADC_MR_SETTLING_AST3 (0x0u << 20)

(ADC_MR) 3 periods of ADCClock

Definition at line 134 of file component_adc.h.

◆ ADC_MR_SETTLING_AST5

#define ADC_MR_SETTLING_AST5 (0x1u << 20)

(ADC_MR) 5 periods of ADCClock

Definition at line 135 of file component_adc.h.

◆ ADC_MR_SETTLING_AST9

#define ADC_MR_SETTLING_AST9 (0x2u << 20)

(ADC_MR) 9 periods of ADCClock

Definition at line 136 of file component_adc.h.

◆ ADC_MR_SETTLING_Msk

#define ADC_MR_SETTLING_Msk (0x3u << ADC_MR_SETTLING_Pos)

(ADC_MR) Analog Settling Time

Definition at line 133 of file component_adc.h.

◆ ADC_MR_SETTLING_Pos

#define ADC_MR_SETTLING_Pos 20

Definition at line 132 of file component_adc.h.

◆ ADC_MR_SLEEP

#define ADC_MR_SLEEP (0x1u << 5)

(ADC_MR) Sleep Mode

Definition at line 102 of file component_adc.h.

Referenced by adc_configure_power_save().

◆ ADC_MR_SLEEP_NORMAL

#define ADC_MR_SLEEP_NORMAL (0x0u << 5)

(ADC_MR) Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions

Definition at line 103 of file component_adc.h.

◆ ADC_MR_SLEEP_SLEEP

#define ADC_MR_SLEEP_SLEEP (0x1u << 5)

(ADC_MR) Sleep Mode: The wake-up time can be modified by programming FWUP bit

Definition at line 104 of file component_adc.h.

Referenced by adc_check().

◆ ADC_MR_STARTUP_Msk

#define ADC_MR_STARTUP_Msk (0xfu << ADC_MR_STARTUP_Pos)

(ADC_MR) Start Up Time

Definition at line 115 of file component_adc.h.

Referenced by adc_check().

◆ ADC_MR_STARTUP_Pos

#define ADC_MR_STARTUP_Pos 16

Definition at line 114 of file component_adc.h.

Referenced by adc_check().

◆ ADC_MR_STARTUP_SUT0

#define ADC_MR_STARTUP_SUT0 (0x0u << 16)

(ADC_MR) 0 periods of ADCClock

Definition at line 116 of file component_adc.h.

◆ ADC_MR_STARTUP_SUT112

#define ADC_MR_STARTUP_SUT112 (0x7u << 16)

(ADC_MR) 112 periods of ADCClock

Definition at line 123 of file component_adc.h.

◆ ADC_MR_STARTUP_SUT16

#define ADC_MR_STARTUP_SUT16 (0x2u << 16)

(ADC_MR) 16 periods of ADCClock

Definition at line 118 of file component_adc.h.

◆ ADC_MR_STARTUP_SUT24

#define ADC_MR_STARTUP_SUT24 (0x3u << 16)

(ADC_MR) 24 periods of ADCClock

Definition at line 119 of file component_adc.h.

◆ ADC_MR_STARTUP_SUT512

#define ADC_MR_STARTUP_SUT512 (0x8u << 16)

(ADC_MR) 512 periods of ADCClock

Definition at line 124 of file component_adc.h.

◆ ADC_MR_STARTUP_SUT576

#define ADC_MR_STARTUP_SUT576 (0x9u << 16)

(ADC_MR) 576 periods of ADCClock

Definition at line 125 of file component_adc.h.

◆ ADC_MR_STARTUP_SUT64

#define ADC_MR_STARTUP_SUT64 (0x4u << 16)

(ADC_MR) 64 periods of ADCClock

Definition at line 120 of file component_adc.h.

◆ ADC_MR_STARTUP_SUT640

#define ADC_MR_STARTUP_SUT640 (0xAu << 16)

(ADC_MR) 640 periods of ADCClock

Definition at line 126 of file component_adc.h.

◆ ADC_MR_STARTUP_SUT704

#define ADC_MR_STARTUP_SUT704 (0xBu << 16)

(ADC_MR) 704 periods of ADCClock

Definition at line 127 of file component_adc.h.

◆ ADC_MR_STARTUP_SUT768

#define ADC_MR_STARTUP_SUT768 (0xCu << 16)

(ADC_MR) 768 periods of ADCClock

Definition at line 128 of file component_adc.h.

◆ ADC_MR_STARTUP_SUT8

#define ADC_MR_STARTUP_SUT8 (0x1u << 16)

(ADC_MR) 8 periods of ADCClock

Definition at line 117 of file component_adc.h.

◆ ADC_MR_STARTUP_SUT80

#define ADC_MR_STARTUP_SUT80 (0x5u << 16)

(ADC_MR) 80 periods of ADCClock

Definition at line 121 of file component_adc.h.

◆ ADC_MR_STARTUP_SUT832

#define ADC_MR_STARTUP_SUT832 (0xDu << 16)

(ADC_MR) 832 periods of ADCClock

Definition at line 129 of file component_adc.h.

◆ ADC_MR_STARTUP_SUT896

#define ADC_MR_STARTUP_SUT896 (0xEu << 16)

(ADC_MR) 896 periods of ADCClock

Definition at line 130 of file component_adc.h.

◆ ADC_MR_STARTUP_SUT96

#define ADC_MR_STARTUP_SUT96 (0x6u << 16)

(ADC_MR) 96 periods of ADCClock

Definition at line 122 of file component_adc.h.

◆ ADC_MR_STARTUP_SUT960

#define ADC_MR_STARTUP_SUT960 (0xFu << 16)

(ADC_MR) 960 periods of ADCClock

Definition at line 131 of file component_adc.h.

◆ ADC_MR_TRACKTIM

#define ADC_MR_TRACKTIM ( value )

Value:

((ADC_MR_TRACKTIM_Msk & ((value) << ADC_MR_TRACKTIM_Pos)))

ADC_MR_TRACKTIM_Pos

#define ADC_MR_TRACKTIM_Pos

Definition component_adc.h:141

ADC_MR_TRACKTIM_Msk

#define ADC_MR_TRACKTIM_Msk

(ADC_MR) Tracking Time

Definition component_adc.h:142

Definition at line 143 of file component_adc.h.

Referenced by adc_configure_timing().

◆ ADC_MR_TRACKTIM_Msk

#define ADC_MR_TRACKTIM_Msk (0xfu << ADC_MR_TRACKTIM_Pos)

(ADC_MR) Tracking Time

Definition at line 142 of file component_adc.h.

◆ ADC_MR_TRACKTIM_Pos

#define ADC_MR_TRACKTIM_Pos 24

Definition at line 141 of file component_adc.h.

◆ ADC_MR_TRANSFER

#define ADC_MR_TRANSFER ( value )

Value:

((ADC_MR_TRANSFER_Msk & ((value) << ADC_MR_TRANSFER_Pos)))

ADC_MR_TRANSFER_Pos

#define ADC_MR_TRANSFER_Pos

Definition component_adc.h:144

ADC_MR_TRANSFER_Msk

#define ADC_MR_TRANSFER_Msk

(ADC_MR) Transfer Period

Definition component_adc.h:145

Definition at line 146 of file component_adc.h.

Referenced by adc_configure_timing().

◆ ADC_MR_TRANSFER_Msk

#define ADC_MR_TRANSFER_Msk (0x3u << ADC_MR_TRANSFER_Pos)

(ADC_MR) Transfer Period

Definition at line 145 of file component_adc.h.

◆ ADC_MR_TRANSFER_Pos

#define ADC_MR_TRANSFER_Pos 28

Definition at line 144 of file component_adc.h.

◆ ADC_MR_TRGEN

#define ADC_MR_TRGEN (0x1u << 0)

(ADC_MR) Trigger Enable

Definition at line 88 of file component_adc.h.

◆ ADC_MR_TRGEN_DIS

#define ADC_MR_TRGEN_DIS (0x0u << 0)

(ADC_MR) Hardware triggers are disabled.

Starting a conversion is only possible by software.

Definition at line 89 of file component_adc.h.

◆ ADC_MR_TRGEN_EN

#define ADC_MR_TRGEN_EN (0x1u << 0)

(ADC_MR) Hardware trigger selected by TRGSEL field is enabled.

Definition at line 90 of file component_adc.h.

◆ ADC_MR_TRGSEL_ADC_TRIG0

#define ADC_MR_TRGSEL_ADC_TRIG0 (0x0u << 1)

(ADC_MR) External trigger

Definition at line 93 of file component_adc.h.

◆ ADC_MR_TRGSEL_ADC_TRIG1

#define ADC_MR_TRGSEL_ADC_TRIG1 (0x1u << 1)

(ADC_MR) TIO Output of the Timer Counter Channel 0

Definition at line 94 of file component_adc.h.

◆ ADC_MR_TRGSEL_ADC_TRIG2

#define ADC_MR_TRGSEL_ADC_TRIG2 (0x2u << 1)

(ADC_MR) TIO Output of the Timer Counter Channel 1

Definition at line 95 of file component_adc.h.

◆ ADC_MR_TRGSEL_ADC_TRIG3

#define ADC_MR_TRGSEL_ADC_TRIG3 (0x3u << 1)

(ADC_MR) TIO Output of the Timer Counter Channel 2

Definition at line 96 of file component_adc.h.

◆ ADC_MR_TRGSEL_ADC_TRIG4

#define ADC_MR_TRGSEL_ADC_TRIG4 (0x4u << 1)

(ADC_MR) PWM Event Line 0

Definition at line 97 of file component_adc.h.

◆ ADC_MR_TRGSEL_ADC_TRIG5

#define ADC_MR_TRGSEL_ADC_TRIG5 (0x5u << 1)

(ADC_MR) PWM Event Line 1

Definition at line 98 of file component_adc.h.

◆ ADC_MR_TRGSEL_Msk

#define ADC_MR_TRGSEL_Msk (0x7u << ADC_MR_TRGSEL_Pos)

(ADC_MR) Trigger Selection

Definition at line 92 of file component_adc.h.

◆ ADC_MR_TRGSEL_Pos

#define ADC_MR_TRGSEL_Pos 1

Definition at line 91 of file component_adc.h.

◆ ADC_MR_USEQ

#define ADC_MR_USEQ (0x1u << 31)

(ADC_MR) Use Sequence Enable

Definition at line 147 of file component_adc.h.

Referenced by adc_start_sequencer(), and adc_stop_sequencer().

◆ ADC_MR_USEQ_NUM_ORDER

#define ADC_MR_USEQ_NUM_ORDER (0x0u << 31)

(ADC_MR) Normal Mode: The controller converts channels in a simple numeric order depending only on the channel index.

Definition at line 148 of file component_adc.h.

◆ ADC_MR_USEQ_REG_ORDER

#define ADC_MR_USEQ_REG_ORDER (0x1u << 31)

(ADC_MR) User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2 registers and can be used to convert several times the same channel.

Definition at line 149 of file component_adc.h.

◆ ADC_OVER_OVRE0

#define ADC_OVER_OVRE0 (0x1u << 0)

(ADC_OVER) Overrun Error 0

Definition at line 346 of file component_adc.h.

◆ ADC_OVER_OVRE1

#define ADC_OVER_OVRE1 (0x1u << 1)

(ADC_OVER) Overrun Error 1

Definition at line 347 of file component_adc.h.

◆ ADC_OVER_OVRE10

#define ADC_OVER_OVRE10 (0x1u << 10)

(ADC_OVER) Overrun Error 10

Definition at line 356 of file component_adc.h.

◆ ADC_OVER_OVRE11

#define ADC_OVER_OVRE11 (0x1u << 11)

(ADC_OVER) Overrun Error 11

Definition at line 357 of file component_adc.h.

◆ ADC_OVER_OVRE12

#define ADC_OVER_OVRE12 (0x1u << 12)

(ADC_OVER) Overrun Error 12

Definition at line 358 of file component_adc.h.

◆ ADC_OVER_OVRE13

#define ADC_OVER_OVRE13 (0x1u << 13)

(ADC_OVER) Overrun Error 13

Definition at line 359 of file component_adc.h.

◆ ADC_OVER_OVRE14

#define ADC_OVER_OVRE14 (0x1u << 14)

(ADC_OVER) Overrun Error 14

Definition at line 360 of file component_adc.h.

◆ ADC_OVER_OVRE15

#define ADC_OVER_OVRE15 (0x1u << 15)

(ADC_OVER) Overrun Error 15

Definition at line 361 of file component_adc.h.

◆ ADC_OVER_OVRE2

#define ADC_OVER_OVRE2 (0x1u << 2)

(ADC_OVER) Overrun Error 2

Definition at line 348 of file component_adc.h.

◆ ADC_OVER_OVRE3

#define ADC_OVER_OVRE3 (0x1u << 3)

(ADC_OVER) Overrun Error 3

Definition at line 349 of file component_adc.h.

◆ ADC_OVER_OVRE4

#define ADC_OVER_OVRE4 (0x1u << 4)

(ADC_OVER) Overrun Error 4

Definition at line 350 of file component_adc.h.

◆ ADC_OVER_OVRE5

#define ADC_OVER_OVRE5 (0x1u << 5)

(ADC_OVER) Overrun Error 5

Definition at line 351 of file component_adc.h.

◆ ADC_OVER_OVRE6

#define ADC_OVER_OVRE6 (0x1u << 6)

(ADC_OVER) Overrun Error 6

Definition at line 352 of file component_adc.h.

◆ ADC_OVER_OVRE7

#define ADC_OVER_OVRE7 (0x1u << 7)

(ADC_OVER) Overrun Error 7

Definition at line 353 of file component_adc.h.

◆ ADC_OVER_OVRE8

#define ADC_OVER_OVRE8 (0x1u << 8)

(ADC_OVER) Overrun Error 8

Definition at line 354 of file component_adc.h.

◆ ADC_OVER_OVRE9

#define ADC_OVER_OVRE9 (0x1u << 9)

(ADC_OVER) Overrun Error 9

Definition at line 355 of file component_adc.h.

◆ ADC_PTCR_RXTDIS

#define ADC_PTCR_RXTDIS (0x1u << 1)

(ADC_PTCR) Receiver Transfer Disable

Definition at line 498 of file component_adc.h.

Referenced by adc_init().

◆ ADC_PTCR_RXTEN

#define ADC_PTCR_RXTEN (0x1u << 0)

(ADC_PTCR) Receiver Transfer Enable

Definition at line 497 of file component_adc.h.

◆ ADC_PTCR_TXTDIS

#define ADC_PTCR_TXTDIS (0x1u << 9)

(ADC_PTCR) Transmitter Transfer Disable

Definition at line 500 of file component_adc.h.

Referenced by adc_init().

◆ ADC_PTCR_TXTEN

#define ADC_PTCR_TXTEN (0x1u << 8)

(ADC_PTCR) Transmitter Transfer Enable

Definition at line 499 of file component_adc.h.

◆ ADC_PTSR_RXTEN

#define ADC_PTSR_RXTEN (0x1u << 0)

(ADC_PTSR) Receiver Transfer Enable

Definition at line 502 of file component_adc.h.

◆ ADC_PTSR_TXTEN

#define ADC_PTSR_TXTEN (0x1u << 8)

(ADC_PTSR) Transmitter Transfer Enable

Definition at line 503 of file component_adc.h.

◆ ADC_RCR_RXCTR

#define ADC_RCR_RXCTR ( value )

Value:

((ADC_RCR_RXCTR_Msk & ((value) << ADC_RCR_RXCTR_Pos)))

ADC_RCR_RXCTR_Pos

#define ADC_RCR_RXCTR_Pos

Definition component_adc.h:485

ADC_RCR_RXCTR_Msk

#define ADC_RCR_RXCTR_Msk

(ADC_RCR) Receive Counter Register

Definition component_adc.h:486

Definition at line 487 of file component_adc.h.

◆ ADC_RCR_RXCTR_Msk

#define ADC_RCR_RXCTR_Msk (0xffffu << ADC_RCR_RXCTR_Pos)

(ADC_RCR) Receive Counter Register

Definition at line 486 of file component_adc.h.

◆ ADC_RCR_RXCTR_Pos

#define ADC_RCR_RXCTR_Pos 0

Definition at line 485 of file component_adc.h.

◆ ADC_RNCR_RXNCTR

#define ADC_RNCR_RXNCTR ( value )

Value:

((ADC_RNCR_RXNCTR_Msk & ((value) << ADC_RNCR_RXNCTR_Pos)))

ADC_RNCR_RXNCTR_Msk

#define ADC_RNCR_RXNCTR_Msk

(ADC_RNCR) Receive Next Counter

Definition component_adc.h:494

ADC_RNCR_RXNCTR_Pos

#define ADC_RNCR_RXNCTR_Pos

Definition component_adc.h:493

Definition at line 495 of file component_adc.h.

◆ ADC_RNCR_RXNCTR_Msk

#define ADC_RNCR_RXNCTR_Msk (0xffffu << ADC_RNCR_RXNCTR_Pos)

(ADC_RNCR) Receive Next Counter

Definition at line 494 of file component_adc.h.

◆ ADC_RNCR_RXNCTR_Pos

#define ADC_RNCR_RXNCTR_Pos 0

Definition at line 493 of file component_adc.h.

◆ ADC_RNPR_RXNPTR

#define ADC_RNPR_RXNPTR ( value )

Value:

((ADC_RNPR_RXNPTR_Msk & ((value) << ADC_RNPR_RXNPTR_Pos)))

ADC_RNPR_RXNPTR_Pos

#define ADC_RNPR_RXNPTR_Pos

Definition component_adc.h:489

ADC_RNPR_RXNPTR_Msk

#define ADC_RNPR_RXNPTR_Msk

(ADC_RNPR) Receive Next Pointer

Definition component_adc.h:490

Definition at line 491 of file component_adc.h.

◆ ADC_RNPR_RXNPTR_Msk

#define ADC_RNPR_RXNPTR_Msk (0xffffffffu << ADC_RNPR_RXNPTR_Pos)

(ADC_RNPR) Receive Next Pointer

Definition at line 490 of file component_adc.h.

◆ ADC_RNPR_RXNPTR_Pos

#define ADC_RNPR_RXNPTR_Pos 0

Definition at line 489 of file component_adc.h.

◆ ADC_RPR_RXPTR

#define ADC_RPR_RXPTR ( value )

Value:

((ADC_RPR_RXPTR_Msk & ((value) << ADC_RPR_RXPTR_Pos)))

ADC_RPR_RXPTR_Pos

#define ADC_RPR_RXPTR_Pos

Definition component_adc.h:481

ADC_RPR_RXPTR_Msk

#define ADC_RPR_RXPTR_Msk

(ADC_RPR) Receive Pointer Register

Definition component_adc.h:482

Definition at line 483 of file component_adc.h.

◆ ADC_RPR_RXPTR_Msk

#define ADC_RPR_RXPTR_Msk (0xffffffffu << ADC_RPR_RXPTR_Pos)

(ADC_RPR) Receive Pointer Register

Definition at line 482 of file component_adc.h.

◆ ADC_RPR_RXPTR_Pos

#define ADC_RPR_RXPTR_Pos 0

Definition at line 481 of file component_adc.h.

◆ ADC_SEQR1_USCH1

#define ADC_SEQR1_USCH1 ( value )

Value:

((ADC_SEQR1_USCH1_Msk & ((value) << ADC_SEQR1_USCH1_Pos)))

ADC_SEQR1_USCH1_Msk

#define ADC_SEQR1_USCH1_Msk

(ADC_SEQR1) User Sequence Number 1

Definition component_adc.h:152

ADC_SEQR1_USCH1_Pos

#define ADC_SEQR1_USCH1_Pos

Definition component_adc.h:151

Definition at line 153 of file component_adc.h.

◆ ADC_SEQR1_USCH1_Msk

#define ADC_SEQR1_USCH1_Msk (0xfu << ADC_SEQR1_USCH1_Pos)

(ADC_SEQR1) User Sequence Number 1

Definition at line 152 of file component_adc.h.

◆ ADC_SEQR1_USCH1_Pos

#define ADC_SEQR1_USCH1_Pos 0

Definition at line 151 of file component_adc.h.

◆ ADC_SEQR1_USCH2

#define ADC_SEQR1_USCH2 ( value )

Value:

((ADC_SEQR1_USCH2_Msk & ((value) << ADC_SEQR1_USCH2_Pos)))

ADC_SEQR1_USCH2_Pos

#define ADC_SEQR1_USCH2_Pos

Definition component_adc.h:154

ADC_SEQR1_USCH2_Msk

#define ADC_SEQR1_USCH2_Msk

(ADC_SEQR1) User Sequence Number 2

Definition component_adc.h:155

Definition at line 156 of file component_adc.h.

◆ ADC_SEQR1_USCH2_Msk

#define ADC_SEQR1_USCH2_Msk (0xfu << ADC_SEQR1_USCH2_Pos)

(ADC_SEQR1) User Sequence Number 2

Definition at line 155 of file component_adc.h.

◆ ADC_SEQR1_USCH2_Pos

#define ADC_SEQR1_USCH2_Pos 4

Definition at line 154 of file component_adc.h.

◆ ADC_SEQR1_USCH3

#define ADC_SEQR1_USCH3 ( value )

Value:

((ADC_SEQR1_USCH3_Msk & ((value) << ADC_SEQR1_USCH3_Pos)))

ADC_SEQR1_USCH3_Pos

#define ADC_SEQR1_USCH3_Pos

Definition component_adc.h:157

ADC_SEQR1_USCH3_Msk

#define ADC_SEQR1_USCH3_Msk

(ADC_SEQR1) User Sequence Number 3

Definition component_adc.h:158

Definition at line 159 of file component_adc.h.

◆ ADC_SEQR1_USCH3_Msk

#define ADC_SEQR1_USCH3_Msk (0xfu << ADC_SEQR1_USCH3_Pos)

(ADC_SEQR1) User Sequence Number 3

Definition at line 158 of file component_adc.h.

◆ ADC_SEQR1_USCH3_Pos

#define ADC_SEQR1_USCH3_Pos 8

Definition at line 157 of file component_adc.h.

◆ ADC_SEQR1_USCH4

#define ADC_SEQR1_USCH4 ( value )

Value:

((ADC_SEQR1_USCH4_Msk & ((value) << ADC_SEQR1_USCH4_Pos)))

ADC_SEQR1_USCH4_Msk

#define ADC_SEQR1_USCH4_Msk

(ADC_SEQR1) User Sequence Number 4

Definition component_adc.h:161

ADC_SEQR1_USCH4_Pos

#define ADC_SEQR1_USCH4_Pos

Definition component_adc.h:160

Definition at line 162 of file component_adc.h.

◆ ADC_SEQR1_USCH4_Msk

#define ADC_SEQR1_USCH4_Msk (0xfu << ADC_SEQR1_USCH4_Pos)

(ADC_SEQR1) User Sequence Number 4

Definition at line 161 of file component_adc.h.

◆ ADC_SEQR1_USCH4_Pos

#define ADC_SEQR1_USCH4_Pos 12

Definition at line 160 of file component_adc.h.

◆ ADC_SEQR1_USCH5

#define ADC_SEQR1_USCH5 ( value )

Value:

((ADC_SEQR1_USCH5_Msk & ((value) << ADC_SEQR1_USCH5_Pos)))

ADC_SEQR1_USCH5_Msk

#define ADC_SEQR1_USCH5_Msk

(ADC_SEQR1) User Sequence Number 5

Definition component_adc.h:164

ADC_SEQR1_USCH5_Pos

#define ADC_SEQR1_USCH5_Pos

Definition component_adc.h:163

Definition at line 165 of file component_adc.h.

◆ ADC_SEQR1_USCH5_Msk

#define ADC_SEQR1_USCH5_Msk (0xfu << ADC_SEQR1_USCH5_Pos)

(ADC_SEQR1) User Sequence Number 5

Definition at line 164 of file component_adc.h.

◆ ADC_SEQR1_USCH5_Pos

#define ADC_SEQR1_USCH5_Pos 16

Definition at line 163 of file component_adc.h.

◆ ADC_SEQR1_USCH6

#define ADC_SEQR1_USCH6 ( value )

Value:

((ADC_SEQR1_USCH6_Msk & ((value) << ADC_SEQR1_USCH6_Pos)))

ADC_SEQR1_USCH6_Msk

#define ADC_SEQR1_USCH6_Msk

(ADC_SEQR1) User Sequence Number 6

Definition component_adc.h:167

ADC_SEQR1_USCH6_Pos

#define ADC_SEQR1_USCH6_Pos

Definition component_adc.h:166

Definition at line 168 of file component_adc.h.

◆ ADC_SEQR1_USCH6_Msk

#define ADC_SEQR1_USCH6_Msk (0xfu << ADC_SEQR1_USCH6_Pos)

(ADC_SEQR1) User Sequence Number 6

Definition at line 167 of file component_adc.h.

◆ ADC_SEQR1_USCH6_Pos

#define ADC_SEQR1_USCH6_Pos 20

Definition at line 166 of file component_adc.h.

◆ ADC_SEQR1_USCH7

#define ADC_SEQR1_USCH7 ( value )

Value:

((ADC_SEQR1_USCH7_Msk & ((value) << ADC_SEQR1_USCH7_Pos)))

ADC_SEQR1_USCH7_Msk

#define ADC_SEQR1_USCH7_Msk

(ADC_SEQR1) User Sequence Number 7

Definition component_adc.h:170

ADC_SEQR1_USCH7_Pos

#define ADC_SEQR1_USCH7_Pos

Definition component_adc.h:169

Definition at line 171 of file component_adc.h.

◆ ADC_SEQR1_USCH7_Msk

#define ADC_SEQR1_USCH7_Msk (0xfu << ADC_SEQR1_USCH7_Pos)

(ADC_SEQR1) User Sequence Number 7

Definition at line 170 of file component_adc.h.

◆ ADC_SEQR1_USCH7_Pos

#define ADC_SEQR1_USCH7_Pos 24

Definition at line 169 of file component_adc.h.

◆ ADC_SEQR1_USCH8

#define ADC_SEQR1_USCH8 ( value )

Value:

((ADC_SEQR1_USCH8_Msk & ((value) << ADC_SEQR1_USCH8_Pos)))

ADC_SEQR1_USCH8_Pos

#define ADC_SEQR1_USCH8_Pos

Definition component_adc.h:172

ADC_SEQR1_USCH8_Msk

#define ADC_SEQR1_USCH8_Msk

(ADC_SEQR1) User Sequence Number 8

Definition component_adc.h:173

Definition at line 174 of file component_adc.h.

◆ ADC_SEQR1_USCH8_Msk

#define ADC_SEQR1_USCH8_Msk (0xfu << ADC_SEQR1_USCH8_Pos)

(ADC_SEQR1) User Sequence Number 8

Definition at line 173 of file component_adc.h.

◆ ADC_SEQR1_USCH8_Pos

#define ADC_SEQR1_USCH8_Pos 28

Definition at line 172 of file component_adc.h.

◆ ADC_SEQR2_USCH10

#define ADC_SEQR2_USCH10 ( value )

Value:

((ADC_SEQR2_USCH10_Msk & ((value) << ADC_SEQR2_USCH10_Pos)))

ADC_SEQR2_USCH10_Msk

#define ADC_SEQR2_USCH10_Msk

(ADC_SEQR2) User Sequence Number 10

Definition component_adc.h:180

ADC_SEQR2_USCH10_Pos

#define ADC_SEQR2_USCH10_Pos

Definition component_adc.h:179

Definition at line 181 of file component_adc.h.

◆ ADC_SEQR2_USCH10_Msk

#define ADC_SEQR2_USCH10_Msk (0xfu << ADC_SEQR2_USCH10_Pos)

(ADC_SEQR2) User Sequence Number 10

Definition at line 180 of file component_adc.h.

◆ ADC_SEQR2_USCH10_Pos

#define ADC_SEQR2_USCH10_Pos 4

Definition at line 179 of file component_adc.h.

◆ ADC_SEQR2_USCH11

#define ADC_SEQR2_USCH11 ( value )

Value:

((ADC_SEQR2_USCH11_Msk & ((value) << ADC_SEQR2_USCH11_Pos)))

ADC_SEQR2_USCH11_Pos

#define ADC_SEQR2_USCH11_Pos

Definition component_adc.h:182

ADC_SEQR2_USCH11_Msk

#define ADC_SEQR2_USCH11_Msk

(ADC_SEQR2) User Sequence Number 11

Definition component_adc.h:183

Definition at line 184 of file component_adc.h.

◆ ADC_SEQR2_USCH11_Msk

#define ADC_SEQR2_USCH11_Msk (0xfu << ADC_SEQR2_USCH11_Pos)

(ADC_SEQR2) User Sequence Number 11

Definition at line 183 of file component_adc.h.

◆ ADC_SEQR2_USCH11_Pos

#define ADC_SEQR2_USCH11_Pos 8

Definition at line 182 of file component_adc.h.

◆ ADC_SEQR2_USCH12

#define ADC_SEQR2_USCH12 ( value )

Value:

((ADC_SEQR2_USCH12_Msk & ((value) << ADC_SEQR2_USCH12_Pos)))

ADC_SEQR2_USCH12_Msk

#define ADC_SEQR2_USCH12_Msk

(ADC_SEQR2) User Sequence Number 12

Definition component_adc.h:186

ADC_SEQR2_USCH12_Pos

#define ADC_SEQR2_USCH12_Pos

Definition component_adc.h:185

Definition at line 187 of file component_adc.h.

◆ ADC_SEQR2_USCH12_Msk

#define ADC_SEQR2_USCH12_Msk (0xfu << ADC_SEQR2_USCH12_Pos)

(ADC_SEQR2) User Sequence Number 12

Definition at line 186 of file component_adc.h.

◆ ADC_SEQR2_USCH12_Pos

#define ADC_SEQR2_USCH12_Pos 12

Definition at line 185 of file component_adc.h.

◆ ADC_SEQR2_USCH13

#define ADC_SEQR2_USCH13 ( value )

Value:

((ADC_SEQR2_USCH13_Msk & ((value) << ADC_SEQR2_USCH13_Pos)))

ADC_SEQR2_USCH13_Msk

#define ADC_SEQR2_USCH13_Msk

(ADC_SEQR2) User Sequence Number 13

Definition component_adc.h:189

ADC_SEQR2_USCH13_Pos

#define ADC_SEQR2_USCH13_Pos

Definition component_adc.h:188

Definition at line 190 of file component_adc.h.

◆ ADC_SEQR2_USCH13_Msk

#define ADC_SEQR2_USCH13_Msk (0xfu << ADC_SEQR2_USCH13_Pos)

(ADC_SEQR2) User Sequence Number 13

Definition at line 189 of file component_adc.h.

◆ ADC_SEQR2_USCH13_Pos

#define ADC_SEQR2_USCH13_Pos 16

Definition at line 188 of file component_adc.h.

◆ ADC_SEQR2_USCH14

#define ADC_SEQR2_USCH14 ( value )

Value:

((ADC_SEQR2_USCH14_Msk & ((value) << ADC_SEQR2_USCH14_Pos)))

ADC_SEQR2_USCH14_Pos

#define ADC_SEQR2_USCH14_Pos

Definition component_adc.h:191

ADC_SEQR2_USCH14_Msk

#define ADC_SEQR2_USCH14_Msk

(ADC_SEQR2) User Sequence Number 14

Definition component_adc.h:192

Definition at line 193 of file component_adc.h.

◆ ADC_SEQR2_USCH14_Msk

#define ADC_SEQR2_USCH14_Msk (0xfu << ADC_SEQR2_USCH14_Pos)

(ADC_SEQR2) User Sequence Number 14

Definition at line 192 of file component_adc.h.

◆ ADC_SEQR2_USCH14_Pos

#define ADC_SEQR2_USCH14_Pos 20

Definition at line 191 of file component_adc.h.

◆ ADC_SEQR2_USCH15

#define ADC_SEQR2_USCH15 ( value )

Value:

((ADC_SEQR2_USCH15_Msk & ((value) << ADC_SEQR2_USCH15_Pos)))

ADC_SEQR2_USCH15_Msk

#define ADC_SEQR2_USCH15_Msk

(ADC_SEQR2) User Sequence Number 15

Definition component_adc.h:195

ADC_SEQR2_USCH15_Pos

#define ADC_SEQR2_USCH15_Pos

Definition component_adc.h:194

Definition at line 196 of file component_adc.h.

◆ ADC_SEQR2_USCH15_Msk

#define ADC_SEQR2_USCH15_Msk (0xfu << ADC_SEQR2_USCH15_Pos)

(ADC_SEQR2) User Sequence Number 15

Definition at line 195 of file component_adc.h.

◆ ADC_SEQR2_USCH15_Pos

#define ADC_SEQR2_USCH15_Pos 24

Definition at line 194 of file component_adc.h.

◆ ADC_SEQR2_USCH9

#define ADC_SEQR2_USCH9 ( value )

Value:

((ADC_SEQR2_USCH9_Msk & ((value) << ADC_SEQR2_USCH9_Pos)))

ADC_SEQR2_USCH9_Pos

#define ADC_SEQR2_USCH9_Pos

Definition component_adc.h:176

ADC_SEQR2_USCH9_Msk

#define ADC_SEQR2_USCH9_Msk

(ADC_SEQR2) User Sequence Number 9

Definition component_adc.h:177

Definition at line 178 of file component_adc.h.

◆ ADC_SEQR2_USCH9_Msk

#define ADC_SEQR2_USCH9_Msk (0xfu << ADC_SEQR2_USCH9_Pos)

(ADC_SEQR2) User Sequence Number 9

Definition at line 177 of file component_adc.h.

◆ ADC_SEQR2_USCH9_Pos

#define ADC_SEQR2_USCH9_Pos 0

Definition at line 176 of file component_adc.h.

◆ ADC_WPMR_WPEN

#define ADC_WPMR_WPEN (0x1u << 0)

(ADC_WPMR) Write Protect Enable

Definition at line 472 of file component_adc.h.

Referenced by adc_set_writeprotect().

◆ ADC_WPMR_WPKEY_Msk

#define ADC_WPMR_WPKEY_Msk (0xffffffu << ADC_WPMR_WPKEY_Pos)

(ADC_WPMR) Write Protect KEY

Definition at line 474 of file component_adc.h.

◆ ADC_WPMR_WPKEY_PASSWD

#define ADC_WPMR_WPKEY_PASSWD (0x414443u << 8)

(ADC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0

Definition at line 475 of file component_adc.h.

◆ ADC_WPMR_WPKEY_Pos

#define ADC_WPMR_WPKEY_Pos 8

Definition at line 473 of file component_adc.h.

◆ ADC_WPSR_WPVS

#define ADC_WPSR_WPVS (0x1u << 0)

(ADC_WPSR) Write Protect Violation Status

Definition at line 477 of file component_adc.h.

Referenced by adc_get_writeprotect_status().

◆ ADC_WPSR_WPVSRC_Msk

#define ADC_WPSR_WPVSRC_Msk (0xffffu << ADC_WPSR_WPVSRC_Pos)

(ADC_WPSR) Write Protect Violation Source

Definition at line 479 of file component_adc.h.

Referenced by adc_get_writeprotect_status().

◆ ADC_WPSR_WPVSRC_Pos

#define ADC_WPSR_WPVSRC_Pos 8

Definition at line 478 of file component_adc.h.

Referenced by adc_get_writeprotect_status().

Data Structures

Macros

Detailed Description

Macro Definition Documentation

◆ ADC_ACR_IBCTL

◆ ADC_ACR_IBCTL_Msk

◆ ADC_ACR_IBCTL_Pos

◆ ADC_ACR_TSON

◆ ADC_CDR_DATA_Msk

◆ ADC_CDR_DATA_Pos

◆ ADC_CGR_GAIN0

◆ ADC_CGR_GAIN0_Msk

◆ ADC_CGR_GAIN0_Pos

◆ ADC_CGR_GAIN1

◆ ADC_CGR_GAIN10

◆ ADC_CGR_GAIN10_Msk

◆ ADC_CGR_GAIN10_Pos

◆ ADC_CGR_GAIN11

◆ ADC_CGR_GAIN11_Msk

◆ ADC_CGR_GAIN11_Pos

◆ ADC_CGR_GAIN12

◆ ADC_CGR_GAIN12_Msk

◆ ADC_CGR_GAIN12_Pos

◆ ADC_CGR_GAIN13

◆ ADC_CGR_GAIN13_Msk

◆ ADC_CGR_GAIN13_Pos

◆ ADC_CGR_GAIN14

◆ ADC_CGR_GAIN14_Msk

◆ ADC_CGR_GAIN14_Pos

◆ ADC_CGR_GAIN15

◆ ADC_CGR_GAIN15_Msk

◆ ADC_CGR_GAIN15_Pos

◆ ADC_CGR_GAIN1_Msk

◆ ADC_CGR_GAIN1_Pos

◆ ADC_CGR_GAIN2

◆ ADC_CGR_GAIN2_Msk

◆ ADC_CGR_GAIN2_Pos

◆ ADC_CGR_GAIN3

◆ ADC_CGR_GAIN3_Msk

◆ ADC_CGR_GAIN3_Pos

◆ ADC_CGR_GAIN4

◆ ADC_CGR_GAIN4_Msk

◆ ADC_CGR_GAIN4_Pos

◆ ADC_CGR_GAIN5

◆ ADC_CGR_GAIN5_Msk

◆ ADC_CGR_GAIN5_Pos

◆ ADC_CGR_GAIN6

◆ ADC_CGR_GAIN6_Msk

◆ ADC_CGR_GAIN6_Pos

◆ ADC_CGR_GAIN7

◆ ADC_CGR_GAIN7_Msk

◆ ADC_CGR_GAIN7_Pos

◆ ADC_CGR_GAIN8

◆ ADC_CGR_GAIN8_Msk

◆ ADC_CGR_GAIN8_Pos

◆ ADC_CGR_GAIN9

◆ ADC_CGR_GAIN9_Msk

◆ ADC_CGR_GAIN9_Pos

◆ ADC_CHDR_CH0

◆ ADC_CHDR_CH1

◆ ADC_CHDR_CH10

◆ ADC_CHDR_CH11

◆ ADC_CHDR_CH12

◆ ADC_CHDR_CH13

◆ ADC_CHDR_CH14

◆ ADC_CHDR_CH15

◆ ADC_CHDR_CH2

◆ ADC_CHDR_CH3

◆ ADC_CHDR_CH4

◆ ADC_CHDR_CH5

◆ ADC_CHDR_CH6

◆ ADC_CHDR_CH7

◆ ADC_CHDR_CH8

◆ ADC_CHDR_CH9

◆ ADC_CHER_CH0

◆ ADC_CHER_CH1

◆ ADC_CHER_CH10

◆ ADC_CHER_CH11

◆ ADC_CHER_CH12

◆ ADC_CHER_CH13