Adc Struct Reference

Adc hardware registers. More...

#include <component_adc.h>

Data Fields
__IO uint32_t	ADC_ACR
	(Adc Offset: 0x94) Analog Control Register
__I uint32_t	ADC_CDR [16]
	(Adc Offset: 0x50) Channel Data Register
__IO uint32_t	ADC_CGR
	(Adc Offset: 0x48) Channel Gain Register
__O uint32_t	ADC_CHDR
	(Adc Offset: 0x14) Channel Disable Register
__O uint32_t	ADC_CHER
	(Adc Offset: 0x10) Channel Enable Register
__I uint32_t	ADC_CHSR
	(Adc Offset: 0x18) Channel Status Register
__IO uint32_t	ADC_COR
	(Adc Offset: 0x4C) Channel Offset Register
__O uint32_t	ADC_CR
	(Adc Offset: 0x00) Control Register
__IO uint32_t	ADC_CWR
	(Adc Offset: 0x44) Compare Window Register
__IO uint32_t	ADC_EMR
	(Adc Offset: 0x40) Extended Mode Register
__O uint32_t	ADC_IDR
	(Adc Offset: 0x28) Interrupt Disable Register
__O uint32_t	ADC_IER
	(Adc Offset: 0x24) Interrupt Enable Register
__I uint32_t	ADC_IMR
	(Adc Offset: 0x2C) Interrupt Mask Register
__I uint32_t	ADC_ISR
	(Adc Offset: 0x30) Interrupt Status Register
__I uint32_t	ADC_LCDR
	(Adc Offset: 0x20) Last Converted Data Register
__IO uint32_t	ADC_MR
	(Adc Offset: 0x04) Mode Register
__I uint32_t	ADC_OVER
	(Adc Offset: 0x3C) Overrun Status Register
__O uint32_t	ADC_PTCR
	(Adc Offset: 0x120) Transfer Control Register
__I uint32_t	ADC_PTSR
	(Adc Offset: 0x124) Transfer Status Register
__IO uint32_t	ADC_RCR
	(Adc Offset: 0x104) Receive Counter Register
__IO uint32_t	ADC_RNCR
	(Adc Offset: 0x114) Receive Next Counter Register
__IO uint32_t	ADC_RNPR
	(Adc Offset: 0x110) Receive Next Pointer Register
__IO uint32_t	ADC_RPR
	(Adc Offset: 0x100) Receive Pointer Register
__IO uint32_t	ADC_SEQR1
	(Adc Offset: 0x08) Channel Sequence Register 1
__IO uint32_t	ADC_SEQR2
	(Adc Offset: 0x0C) Channel Sequence Register 2
__IO uint32_t	ADC_WPMR
	(Adc Offset: 0xE4) Write Protect Mode Register
__I uint32_t	ADC_WPSR
	(Adc Offset: 0xE8) Write Protect Status Register
__I uint32_t	Reserved1 [1]
__I uint32_t	Reserved2 [2]
__I uint32_t	Reserved3 [1]
__I uint32_t	Reserved4 [19]
__I uint32_t	Reserved5 [5]
__I uint32_t	Reserved6 [2]
__I uint32_t	Reserved7 [2]

Detailed Description

Adc hardware registers.

Definition at line 46 of file component_adc.h.

Field Documentation

ADC_ACR

__IO uint32_t Adc::ADC_ACR

(Adc Offset: 0x94) Analog Control Register

Definition at line 68 of file component_adc.h.

Referenced by adc_disable_ts(), adc_enable_ts(), and adc_set_bias_current().

ADC_CDR

__I uint32_t Adc::ADC_CDR[16]

(Adc Offset: 0x50) Channel Data Register

Definition at line 66 of file component_adc.h.

Referenced by adc_get_channel_value().

ADC_CGR

__IO uint32_t Adc::ADC_CGR

(Adc Offset: 0x48) Channel Gain Register

Definition at line 64 of file component_adc.h.

Referenced by adc_set_channel_input_gain().

ADC_CHDR

__O uint32_t Adc::ADC_CHDR

(Adc Offset: 0x14) Channel Disable Register

Definition at line 52 of file component_adc.h.

Referenced by adc_disable_all_channel(), and adc_disable_channel().

ADC_CHER

__O uint32_t Adc::ADC_CHER

(Adc Offset: 0x10) Channel Enable Register

Definition at line 51 of file component_adc.h.

Referenced by adc_enable_all_channel(), and adc_enable_channel().

ADC_CHSR

__I uint32_t Adc::ADC_CHSR

(Adc Offset: 0x18) Channel Status Register

Definition at line 53 of file component_adc.h.

Referenced by adc_get_channel_status().

ADC_COR

__IO uint32_t Adc::ADC_COR

(Adc Offset: 0x4C) Channel Offset Register

Definition at line 65 of file component_adc.h.

Referenced by adc_disable_channel_differential_input(), adc_disable_channel_input_offset(), adc_enable_channel_differential_input(), and adc_enable_channel_input_offset().

ADC_CR

__O uint32_t Adc::ADC_CR

(Adc Offset: 0x00) Control Register

Definition at line 47 of file component_adc.h.

Referenced by adc_init(), adc_reset(), adc_set_calibmode(), and adc_start().

ADC_CWR

__IO uint32_t Adc::ADC_CWR

(Adc Offset: 0x44) Compare Window Register

Definition at line 63 of file component_adc.h.

Referenced by adc_set_comparison_window().

ADC_EMR

__IO uint32_t Adc::ADC_EMR

(Adc Offset: 0x40) Extended Mode Register

Definition at line 62 of file component_adc.h.

Referenced by adc_disable_tag(), adc_enable_tag(), adc_get_comparison_mode(), adc_set_comparison_channel(), adc_set_comparison_mode(), and adc_set_resolution().

ADC_IDR

__O uint32_t Adc::ADC_IDR

(Adc Offset: 0x28) Interrupt Disable Register

Definition at line 57 of file component_adc.h.

Referenced by adc_disable_interrupt().

ADC_IER

__O uint32_t Adc::ADC_IER

(Adc Offset: 0x24) Interrupt Enable Register

Definition at line 56 of file component_adc.h.

Referenced by adc_enable_interrupt().

ADC_IMR

__I uint32_t Adc::ADC_IMR

(Adc Offset: 0x2C) Interrupt Mask Register

Definition at line 58 of file component_adc.h.

Referenced by adc_get_interrupt_mask().

ADC_ISR

__I uint32_t Adc::ADC_ISR

(Adc Offset: 0x30) Interrupt Status Register

Definition at line 59 of file component_adc.h.

Referenced by adc_get_status().

ADC_LCDR

__I uint32_t Adc::ADC_LCDR

(Adc Offset: 0x20) Last Converted Data Register

Definition at line 55 of file component_adc.h.

Referenced by adc_get_latest_value(), and adc_get_tag().

ADC_MR

__IO uint32_t Adc::ADC_MR

(Adc Offset: 0x04) Mode Register

Definition at line 48 of file component_adc.h.

Referenced by adc_check(), adc_configure_power_save(), adc_configure_timing(), adc_configure_trigger(), adc_disable_anch(), adc_enable_anch(), adc_get_actual_adc_clock(), adc_init(), adc_set_resolution(), adc_start_sequencer(), and adc_stop_sequencer().

ADC_OVER

__I uint32_t Adc::ADC_OVER

(Adc Offset: 0x3C) Overrun Status Register

Definition at line 61 of file component_adc.h.

Referenced by adc_get_overrun_status().

ADC_PTCR

__O uint32_t Adc::ADC_PTCR

(Adc Offset: 0x120) Transfer Control Register

Definition at line 79 of file component_adc.h.

Referenced by adc_init().

ADC_PTSR

__I uint32_t Adc::ADC_PTSR

(Adc Offset: 0x124) Transfer Status Register

Definition at line 80 of file component_adc.h.

ADC_RCR

__IO uint32_t Adc::ADC_RCR

(Adc Offset: 0x104) Receive Counter Register

Definition at line 74 of file component_adc.h.

Referenced by adc_init().

ADC_RNCR

__IO uint32_t Adc::ADC_RNCR

(Adc Offset: 0x114) Receive Next Counter Register

Definition at line 77 of file component_adc.h.

Referenced by adc_init().

ADC_RNPR

__IO uint32_t Adc::ADC_RNPR

(Adc Offset: 0x110) Receive Next Pointer Register

Definition at line 76 of file component_adc.h.

ADC_RPR

__IO uint32_t Adc::ADC_RPR

(Adc Offset: 0x100) Receive Pointer Register

Definition at line 73 of file component_adc.h.

ADC_SEQR1

__IO uint32_t Adc::ADC_SEQR1

(Adc Offset: 0x08) Channel Sequence Register 1

Definition at line 49 of file component_adc.h.

Referenced by adc_configure_sequence().

ADC_SEQR2

__IO uint32_t Adc::ADC_SEQR2

(Adc Offset: 0x0C) Channel Sequence Register 2

Definition at line 50 of file component_adc.h.

ADC_WPMR

__IO uint32_t Adc::ADC_WPMR

(Adc Offset: 0xE4) Write Protect Mode Register

Definition at line 70 of file component_adc.h.

Referenced by adc_set_writeprotect().

ADC_WPSR

__I uint32_t Adc::ADC_WPSR

(Adc Offset: 0xE8) Write Protect Status Register

Definition at line 71 of file component_adc.h.

Referenced by adc_get_writeprotect_status().

Reserved1

__I uint32_t Adc::Reserved1[1]

Definition at line 54 of file component_adc.h.

Reserved2

__I uint32_t Adc::Reserved2[2]

Definition at line 60 of file component_adc.h.

Reserved3

__I uint32_t Adc::Reserved3[1]

Definition at line 67 of file component_adc.h.

Reserved4

__I uint32_t Adc::Reserved4[19]

Definition at line 69 of file component_adc.h.

Reserved5

__I uint32_t Adc::Reserved5[5]

Definition at line 72 of file component_adc.h.

Reserved6

__I uint32_t Adc::Reserved6[2]

Definition at line 75 of file component_adc.h.

Reserved7

__I uint32_t Adc::Reserved7[2]

Definition at line 78 of file component_adc.h.