component_twi.h

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/*
 * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
 */
 
#ifndef _SAM4S_TWI_COMPONENT_
#define _SAM4S_TWI_COMPONENT_
 
/* ============================================================================= */
/* ============================================================================= */
 
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
  __O  uint32_t TWI_CR;        
  __IO uint32_t TWI_MMR;       
  __IO uint32_t TWI_SMR;       
  __IO uint32_t TWI_IADR;      
  __IO uint32_t TWI_CWGR;      
  __I  uint32_t Reserved1[3];
  __I  uint32_t TWI_SR;        
  __O  uint32_t TWI_IER;       
  __O  uint32_t TWI_IDR;       
  __I  uint32_t TWI_IMR;       
  __I  uint32_t TWI_RHR;       
  __O  uint32_t TWI_THR;       
  __I  uint32_t Reserved2[50];
  __IO uint32_t TWI_RPR;       
  __IO uint32_t TWI_RCR;       
  __IO uint32_t TWI_TPR;       
  __IO uint32_t TWI_TCR;       
  __IO uint32_t TWI_RNPR;      
  __IO uint32_t TWI_RNCR;      
  __IO uint32_t TWI_TNPR;      
  __IO uint32_t TWI_TNCR;      
  __O  uint32_t TWI_PTCR;      
  __I  uint32_t TWI_PTSR;      
} Twi;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* -------- TWI_CR : (TWI Offset: 0x00) Control Register -------- */
#define TWI_CR_START (0x1u << 0) 
#define TWI_CR_STOP (0x1u << 1) 
#define TWI_CR_MSEN (0x1u << 2) 
#define TWI_CR_MSDIS (0x1u << 3) 
#define TWI_CR_SVEN (0x1u << 4) 
#define TWI_CR_SVDIS (0x1u << 5) 
#define TWI_CR_QUICK (0x1u << 6) 
#define TWI_CR_SWRST (0x1u << 7) 
/* -------- TWI_MMR : (TWI Offset: 0x04) Master Mode Register -------- */
#define TWI_MMR_IADRSZ_Pos 8
#define TWI_MMR_IADRSZ_Msk (0x3u << TWI_MMR_IADRSZ_Pos) 
#define   TWI_MMR_IADRSZ_NONE (0x0u << 8) 
#define   TWI_MMR_IADRSZ_1_BYTE (0x1u << 8) 
#define   TWI_MMR_IADRSZ_2_BYTE (0x2u << 8) 
#define   TWI_MMR_IADRSZ_3_BYTE (0x3u << 8) 
#define TWI_MMR_MREAD (0x1u << 12) 
#define TWI_MMR_DADR_Pos 16
#define TWI_MMR_DADR_Msk (0x7fu << TWI_MMR_DADR_Pos) 
#define TWI_MMR_DADR(value) ((TWI_MMR_DADR_Msk & ((value) << TWI_MMR_DADR_Pos)))
/* -------- TWI_SMR : (TWI Offset: 0x08) Slave Mode Register -------- */
#define TWI_SMR_SADR_Pos 16
#define TWI_SMR_SADR_Msk (0x7fu << TWI_SMR_SADR_Pos) 
#define TWI_SMR_SADR(value) ((TWI_SMR_SADR_Msk & ((value) << TWI_SMR_SADR_Pos)))
/* -------- TWI_IADR : (TWI Offset: 0x0C) Internal Address Register -------- */
#define TWI_IADR_IADR_Pos 0
#define TWI_IADR_IADR_Msk (0xffffffu << TWI_IADR_IADR_Pos) 
#define TWI_IADR_IADR(value) ((TWI_IADR_IADR_Msk & ((value) << TWI_IADR_IADR_Pos)))
/* -------- TWI_CWGR : (TWI Offset: 0x10) Clock Waveform Generator Register -------- */
#define TWI_CWGR_CLDIV_Pos 0
#define TWI_CWGR_CLDIV_Msk (0xffu << TWI_CWGR_CLDIV_Pos) 
#define TWI_CWGR_CLDIV(value) ((TWI_CWGR_CLDIV_Msk & ((value) << TWI_CWGR_CLDIV_Pos)))
#define TWI_CWGR_CHDIV_Pos 8
#define TWI_CWGR_CHDIV_Msk (0xffu << TWI_CWGR_CHDIV_Pos) 
#define TWI_CWGR_CHDIV(value) ((TWI_CWGR_CHDIV_Msk & ((value) << TWI_CWGR_CHDIV_Pos)))
#define TWI_CWGR_CKDIV_Pos 16
#define TWI_CWGR_CKDIV_Msk (0x7u << TWI_CWGR_CKDIV_Pos) 
#define TWI_CWGR_CKDIV(value) ((TWI_CWGR_CKDIV_Msk & ((value) << TWI_CWGR_CKDIV_Pos)))
/* -------- TWI_SR : (TWI Offset: 0x20) Status Register -------- */
#define TWI_SR_TXCOMP (0x1u << 0) 
#define TWI_SR_RXRDY (0x1u << 1) 
#define TWI_SR_TXRDY (0x1u << 2) 
#define TWI_SR_SVREAD (0x1u << 3) 
#define TWI_SR_SVACC (0x1u << 4) 
#define TWI_SR_GACC (0x1u << 5) 
#define TWI_SR_OVRE (0x1u << 6) 
#define TWI_SR_NACK (0x1u << 8) 
#define TWI_SR_ARBLST (0x1u << 9) 
#define TWI_SR_SCLWS (0x1u << 10) 
#define TWI_SR_EOSACC (0x1u << 11) 
#define TWI_SR_ENDRX (0x1u << 12) 
#define TWI_SR_ENDTX (0x1u << 13) 
#define TWI_SR_RXBUFF (0x1u << 14) 
#define TWI_SR_TXBUFE (0x1u << 15) 
/* -------- TWI_IER : (TWI Offset: 0x24) Interrupt Enable Register -------- */
#define TWI_IER_TXCOMP (0x1u << 0) 
#define TWI_IER_RXRDY (0x1u << 1) 
#define TWI_IER_TXRDY (0x1u << 2) 
#define TWI_IER_SVACC (0x1u << 4) 
#define TWI_IER_GACC (0x1u << 5) 
#define TWI_IER_OVRE (0x1u << 6) 
#define TWI_IER_NACK (0x1u << 8) 
#define TWI_IER_ARBLST (0x1u << 9) 
#define TWI_IER_SCL_WS (0x1u << 10) 
#define TWI_IER_EOSACC (0x1u << 11) 
#define TWI_IER_ENDRX (0x1u << 12) 
#define TWI_IER_ENDTX (0x1u << 13) 
#define TWI_IER_RXBUFF (0x1u << 14) 
#define TWI_IER_TXBUFE (0x1u << 15) 
/* -------- TWI_IDR : (TWI Offset: 0x28) Interrupt Disable Register -------- */
#define TWI_IDR_TXCOMP (0x1u << 0) 
#define TWI_IDR_RXRDY (0x1u << 1) 
#define TWI_IDR_TXRDY (0x1u << 2) 
#define TWI_IDR_SVACC (0x1u << 4) 
#define TWI_IDR_GACC (0x1u << 5) 
#define TWI_IDR_OVRE (0x1u << 6) 
#define TWI_IDR_NACK (0x1u << 8) 
#define TWI_IDR_ARBLST (0x1u << 9) 
#define TWI_IDR_SCL_WS (0x1u << 10) 
#define TWI_IDR_EOSACC (0x1u << 11) 
#define TWI_IDR_ENDRX (0x1u << 12) 
#define TWI_IDR_ENDTX (0x1u << 13) 
#define TWI_IDR_RXBUFF (0x1u << 14) 
#define TWI_IDR_TXBUFE (0x1u << 15) 
/* -------- TWI_IMR : (TWI Offset: 0x2C) Interrupt Mask Register -------- */
#define TWI_IMR_TXCOMP (0x1u << 0) 
#define TWI_IMR_RXRDY (0x1u << 1) 
#define TWI_IMR_TXRDY (0x1u << 2) 
#define TWI_IMR_SVACC (0x1u << 4) 
#define TWI_IMR_GACC (0x1u << 5) 
#define TWI_IMR_OVRE (0x1u << 6) 
#define TWI_IMR_NACK (0x1u << 8) 
#define TWI_IMR_ARBLST (0x1u << 9) 
#define TWI_IMR_SCL_WS (0x1u << 10) 
#define TWI_IMR_EOSACC (0x1u << 11) 
#define TWI_IMR_ENDRX (0x1u << 12) 
#define TWI_IMR_ENDTX (0x1u << 13) 
#define TWI_IMR_RXBUFF (0x1u << 14) 
#define TWI_IMR_TXBUFE (0x1u << 15) 
/* -------- TWI_RHR : (TWI Offset: 0x30) Receive Holding Register -------- */
#define TWI_RHR_RXDATA_Pos 0
#define TWI_RHR_RXDATA_Msk (0xffu << TWI_RHR_RXDATA_Pos) 
/* -------- TWI_THR : (TWI Offset: 0x34) Transmit Holding Register -------- */
#define TWI_THR_TXDATA_Pos 0
#define TWI_THR_TXDATA_Msk (0xffu << TWI_THR_TXDATA_Pos) 
#define TWI_THR_TXDATA(value) ((TWI_THR_TXDATA_Msk & ((value) << TWI_THR_TXDATA_Pos)))
/* -------- TWI_RPR : (TWI Offset: 0x100) Receive Pointer Register -------- */
#define TWI_RPR_RXPTR_Pos 0
#define TWI_RPR_RXPTR_Msk (0xffffffffu << TWI_RPR_RXPTR_Pos) 
#define TWI_RPR_RXPTR(value) ((TWI_RPR_RXPTR_Msk & ((value) << TWI_RPR_RXPTR_Pos)))
/* -------- TWI_RCR : (TWI Offset: 0x104) Receive Counter Register -------- */
#define TWI_RCR_RXCTR_Pos 0
#define TWI_RCR_RXCTR_Msk (0xffffu << TWI_RCR_RXCTR_Pos) 
#define TWI_RCR_RXCTR(value) ((TWI_RCR_RXCTR_Msk & ((value) << TWI_RCR_RXCTR_Pos)))
/* -------- TWI_TPR : (TWI Offset: 0x108) Transmit Pointer Register -------- */
#define TWI_TPR_TXPTR_Pos 0
#define TWI_TPR_TXPTR_Msk (0xffffffffu << TWI_TPR_TXPTR_Pos) 
#define TWI_TPR_TXPTR(value) ((TWI_TPR_TXPTR_Msk & ((value) << TWI_TPR_TXPTR_Pos)))
/* -------- TWI_TCR : (TWI Offset: 0x10C) Transmit Counter Register -------- */
#define TWI_TCR_TXCTR_Pos 0
#define TWI_TCR_TXCTR_Msk (0xffffu << TWI_TCR_TXCTR_Pos) 
#define TWI_TCR_TXCTR(value) ((TWI_TCR_TXCTR_Msk & ((value) << TWI_TCR_TXCTR_Pos)))
/* -------- TWI_RNPR : (TWI Offset: 0x110) Receive Next Pointer Register -------- */
#define TWI_RNPR_RXNPTR_Pos 0
#define TWI_RNPR_RXNPTR_Msk (0xffffffffu << TWI_RNPR_RXNPTR_Pos) 
#define TWI_RNPR_RXNPTR(value) ((TWI_RNPR_RXNPTR_Msk & ((value) << TWI_RNPR_RXNPTR_Pos)))
/* -------- TWI_RNCR : (TWI Offset: 0x114) Receive Next Counter Register -------- */
#define TWI_RNCR_RXNCTR_Pos 0
#define TWI_RNCR_RXNCTR_Msk (0xffffu << TWI_RNCR_RXNCTR_Pos) 
#define TWI_RNCR_RXNCTR(value) ((TWI_RNCR_RXNCTR_Msk & ((value) << TWI_RNCR_RXNCTR_Pos)))
/* -------- TWI_TNPR : (TWI Offset: 0x118) Transmit Next Pointer Register -------- */
#define TWI_TNPR_TXNPTR_Pos 0
#define TWI_TNPR_TXNPTR_Msk (0xffffffffu << TWI_TNPR_TXNPTR_Pos) 
#define TWI_TNPR_TXNPTR(value) ((TWI_TNPR_TXNPTR_Msk & ((value) << TWI_TNPR_TXNPTR_Pos)))
/* -------- TWI_TNCR : (TWI Offset: 0x11C) Transmit Next Counter Register -------- */
#define TWI_TNCR_TXNCTR_Pos 0
#define TWI_TNCR_TXNCTR_Msk (0xffffu << TWI_TNCR_TXNCTR_Pos) 
#define TWI_TNCR_TXNCTR(value) ((TWI_TNCR_TXNCTR_Msk & ((value) << TWI_TNCR_TXNCTR_Pos)))
/* -------- TWI_PTCR : (TWI Offset: 0x120) Transfer Control Register -------- */
#define TWI_PTCR_RXTEN (0x1u << 0) 
#define TWI_PTCR_RXTDIS (0x1u << 1) 
#define TWI_PTCR_TXTEN (0x1u << 8) 
#define TWI_PTCR_TXTDIS (0x1u << 9) 
/* -------- TWI_PTSR : (TWI Offset: 0x124) Transfer Status Register -------- */
#define TWI_PTSR_RXTEN (0x1u << 0) 
#define TWI_PTSR_TXTEN (0x1u << 8) 

 
 
#endif /* _SAM4S_TWI_COMPONENT_ */