Data Structures
struct	Twi
	Twi hardware registers. More...

Macros
#define	TWI_CR_MSDIS (0x1u << 3)
	(TWI_CR) TWI Master Mode Disabled
#define	TWI_CR_MSEN (0x1u << 2)
	(TWI_CR) TWI Master Mode Enabled
#define	TWI_CR_QUICK (0x1u << 6)
	(TWI_CR) SMBUS Quick Command
#define	TWI_CR_START (0x1u << 0)
	(TWI_CR) Send a START Condition
#define	TWI_CR_STOP (0x1u << 1)
	(TWI_CR) Send a STOP Condition
#define	TWI_CR_SVDIS (0x1u << 5)
	(TWI_CR) TWI Slave Mode Disabled
#define	TWI_CR_SVEN (0x1u << 4)
	(TWI_CR) TWI Slave Mode Enabled
#define	TWI_CR_SWRST (0x1u << 7)
	(TWI_CR) Software Reset
#define	TWI_CWGR_CHDIV(value)
#define	TWI_CWGR_CHDIV_Msk (0xffu << TWI_CWGR_CHDIV_Pos)
	(TWI_CWGR) Clock High Divider
#define	TWI_CWGR_CHDIV_Pos 8
#define	TWI_CWGR_CKDIV(value)
#define	TWI_CWGR_CKDIV_Msk (0x7u << TWI_CWGR_CKDIV_Pos)
	(TWI_CWGR) Clock Divider
#define	TWI_CWGR_CKDIV_Pos 16
#define	TWI_CWGR_CLDIV(value)
#define	TWI_CWGR_CLDIV_Msk (0xffu << TWI_CWGR_CLDIV_Pos)
	(TWI_CWGR) Clock Low Divider
#define	TWI_CWGR_CLDIV_Pos 0
#define	TWI_IADR_IADR(value)
#define	TWI_IADR_IADR_Msk (0xffffffu << TWI_IADR_IADR_Pos)
	(TWI_IADR) Internal Address
#define	TWI_IADR_IADR_Pos 0
#define	TWI_IDR_ARBLST (0x1u << 9)
	(TWI_IDR) Arbitration Lost Interrupt Disable
#define	TWI_IDR_ENDRX (0x1u << 12)
	(TWI_IDR) End of Receive Buffer Interrupt Disable
#define	TWI_IDR_ENDTX (0x1u << 13)
	(TWI_IDR) End of Transmit Buffer Interrupt Disable
#define	TWI_IDR_EOSACC (0x1u << 11)
	(TWI_IDR) End Of Slave Access Interrupt Disable
#define	TWI_IDR_GACC (0x1u << 5)
	(TWI_IDR) General Call Access Interrupt Disable
#define	TWI_IDR_NACK (0x1u << 8)
	(TWI_IDR) Not Acknowledge Interrupt Disable
#define	TWI_IDR_OVRE (0x1u << 6)
	(TWI_IDR) Overrun Error Interrupt Disable
#define	TWI_IDR_RXBUFF (0x1u << 14)
	(TWI_IDR) Receive Buffer Full Interrupt Disable
#define	TWI_IDR_RXRDY (0x1u << 1)
	(TWI_IDR) Receive Holding Register Ready Interrupt Disable
#define	TWI_IDR_SCL_WS (0x1u << 10)
	(TWI_IDR) Clock Wait State Interrupt Disable
#define	TWI_IDR_SVACC (0x1u << 4)
	(TWI_IDR) Slave Access Interrupt Disable
#define	TWI_IDR_TXBUFE (0x1u << 15)
	(TWI_IDR) Transmit Buffer Empty Interrupt Disable
#define	TWI_IDR_TXCOMP (0x1u << 0)
	(TWI_IDR) Transmission Completed Interrupt Disable
#define	TWI_IDR_TXRDY (0x1u << 2)
	(TWI_IDR) Transmit Holding Register Ready Interrupt Disable
#define	TWI_IER_ARBLST (0x1u << 9)
	(TWI_IER) Arbitration Lost Interrupt Enable
#define	TWI_IER_ENDRX (0x1u << 12)
	(TWI_IER) End of Receive Buffer Interrupt Enable
#define	TWI_IER_ENDTX (0x1u << 13)
	(TWI_IER) End of Transmit Buffer Interrupt Enable
#define	TWI_IER_EOSACC (0x1u << 11)
	(TWI_IER) End Of Slave Access Interrupt Enable
#define	TWI_IER_GACC (0x1u << 5)
	(TWI_IER) General Call Access Interrupt Enable
#define	TWI_IER_NACK (0x1u << 8)
	(TWI_IER) Not Acknowledge Interrupt Enable
#define	TWI_IER_OVRE (0x1u << 6)
	(TWI_IER) Overrun Error Interrupt Enable
#define	TWI_IER_RXBUFF (0x1u << 14)
	(TWI_IER) Receive Buffer Full Interrupt Enable
#define	TWI_IER_RXRDY (0x1u << 1)
	(TWI_IER) Receive Holding Register Ready Interrupt Enable
#define	TWI_IER_SCL_WS (0x1u << 10)
	(TWI_IER) Clock Wait State Interrupt Enable
#define	TWI_IER_SVACC (0x1u << 4)
	(TWI_IER) Slave Access Interrupt Enable
#define	TWI_IER_TXBUFE (0x1u << 15)
	(TWI_IER) Transmit Buffer Empty Interrupt Enable
#define	TWI_IER_TXCOMP (0x1u << 0)
	(TWI_IER) Transmission Completed Interrupt Enable
#define	TWI_IER_TXRDY (0x1u << 2)
	(TWI_IER) Transmit Holding Register Ready Interrupt Enable
#define	TWI_IMR_ARBLST (0x1u << 9)
	(TWI_IMR) Arbitration Lost Interrupt Mask
#define	TWI_IMR_ENDRX (0x1u << 12)
	(TWI_IMR) End of Receive Buffer Interrupt Mask
#define	TWI_IMR_ENDTX (0x1u << 13)
	(TWI_IMR) End of Transmit Buffer Interrupt Mask
#define	TWI_IMR_EOSACC (0x1u << 11)
	(TWI_IMR) End Of Slave Access Interrupt Mask
#define	TWI_IMR_GACC (0x1u << 5)
	(TWI_IMR) General Call Access Interrupt Mask
#define	TWI_IMR_NACK (0x1u << 8)
	(TWI_IMR) Not Acknowledge Interrupt Mask
#define	TWI_IMR_OVRE (0x1u << 6)
	(TWI_IMR) Overrun Error Interrupt Mask
#define	TWI_IMR_RXBUFF (0x1u << 14)
	(TWI_IMR) Receive Buffer Full Interrupt Mask
#define	TWI_IMR_RXRDY (0x1u << 1)
	(TWI_IMR) Receive Holding Register Ready Interrupt Mask
#define	TWI_IMR_SCL_WS (0x1u << 10)
	(TWI_IMR) Clock Wait State Interrupt Mask
#define	TWI_IMR_SVACC (0x1u << 4)
	(TWI_IMR) Slave Access Interrupt Mask
#define	TWI_IMR_TXBUFE (0x1u << 15)
	(TWI_IMR) Transmit Buffer Empty Interrupt Mask
#define	TWI_IMR_TXCOMP (0x1u << 0)
	(TWI_IMR) Transmission Completed Interrupt Mask
#define	TWI_IMR_TXRDY (0x1u << 2)
	(TWI_IMR) Transmit Holding Register Ready Interrupt Mask
#define	TWI_MMR_DADR(value)
#define	TWI_MMR_DADR_Msk (0x7fu << TWI_MMR_DADR_Pos)
	(TWI_MMR) Device Address
#define	TWI_MMR_DADR_Pos 16
#define	TWI_MMR_IADRSZ_1_BYTE (0x1u << 8)
	(TWI_MMR) One-byte internal device address
#define	TWI_MMR_IADRSZ_2_BYTE (0x2u << 8)
	(TWI_MMR) Two-byte internal device address
#define	TWI_MMR_IADRSZ_3_BYTE (0x3u << 8)
	(TWI_MMR) Three-byte internal device address
#define	TWI_MMR_IADRSZ_Msk (0x3u << TWI_MMR_IADRSZ_Pos)
	(TWI_MMR) Internal Device Address Size
#define	TWI_MMR_IADRSZ_NONE (0x0u << 8)
	(TWI_MMR) No internal device address
#define	TWI_MMR_IADRSZ_Pos 8
#define	TWI_MMR_MREAD (0x1u << 12)
	(TWI_MMR) Master Read Direction
#define	TWI_PTCR_RXTDIS (0x1u << 1)
	(TWI_PTCR) Receiver Transfer Disable
#define	TWI_PTCR_RXTEN (0x1u << 0)
	(TWI_PTCR) Receiver Transfer Enable
#define	TWI_PTCR_TXTDIS (0x1u << 9)
	(TWI_PTCR) Transmitter Transfer Disable
#define	TWI_PTCR_TXTEN (0x1u << 8)
	(TWI_PTCR) Transmitter Transfer Enable
#define	TWI_PTSR_RXTEN (0x1u << 0)
	(TWI_PTSR) Receiver Transfer Enable
#define	TWI_PTSR_TXTEN (0x1u << 8)
	(TWI_PTSR) Transmitter Transfer Enable
#define	TWI_RCR_RXCTR(value)
#define	TWI_RCR_RXCTR_Msk (0xffffu << TWI_RCR_RXCTR_Pos)
	(TWI_RCR) Receive Counter Register
#define	TWI_RCR_RXCTR_Pos 0
#define	TWI_RHR_RXDATA_Msk (0xffu << TWI_RHR_RXDATA_Pos)
	(TWI_RHR) Master or Slave Receive Holding Data
#define	TWI_RHR_RXDATA_Pos 0
#define	TWI_RNCR_RXNCTR(value)
#define	TWI_RNCR_RXNCTR_Msk (0xffffu << TWI_RNCR_RXNCTR_Pos)
	(TWI_RNCR) Receive Next Counter
#define	TWI_RNCR_RXNCTR_Pos 0
#define	TWI_RNPR_RXNPTR(value)
#define	TWI_RNPR_RXNPTR_Msk (0xffffffffu << TWI_RNPR_RXNPTR_Pos)
	(TWI_RNPR) Receive Next Pointer
#define	TWI_RNPR_RXNPTR_Pos 0
#define	TWI_RPR_RXPTR(value)
#define	TWI_RPR_RXPTR_Msk (0xffffffffu << TWI_RPR_RXPTR_Pos)
	(TWI_RPR) Receive Pointer Register
#define	TWI_RPR_RXPTR_Pos 0
#define	TWI_SMR_SADR(value)
#define	TWI_SMR_SADR_Msk (0x7fu << TWI_SMR_SADR_Pos)
	(TWI_SMR) Slave Address
#define	TWI_SMR_SADR_Pos 16
#define	TWI_SR_ARBLST (0x1u << 9)
	(TWI_SR) Arbitration Lost (clear on read)
#define	TWI_SR_ENDRX (0x1u << 12)
	(TWI_SR) End of RX buffer
#define	TWI_SR_ENDTX (0x1u << 13)
	(TWI_SR) End of TX buffer
#define	TWI_SR_EOSACC (0x1u << 11)
	(TWI_SR) End Of Slave Access (clear on read)
#define	TWI_SR_GACC (0x1u << 5)
	(TWI_SR) General Call Access (clear on read)
#define	TWI_SR_NACK (0x1u << 8)
	(TWI_SR) Not Acknowledged (clear on read)
#define	TWI_SR_OVRE (0x1u << 6)
	(TWI_SR) Overrun Error (clear on read)
#define	TWI_SR_RXBUFF (0x1u << 14)
	(TWI_SR) RX Buffer Full
#define	TWI_SR_RXRDY (0x1u << 1)
	(TWI_SR) Receive Holding Register Ready (automatically set / reset)
#define	TWI_SR_SCLWS (0x1u << 10)
	(TWI_SR) Clock Wait State (automatically set / reset)
#define	TWI_SR_SVACC (0x1u << 4)
	(TWI_SR) Slave Access (automatically set / reset)
#define	TWI_SR_SVREAD (0x1u << 3)
	(TWI_SR) Slave Read (automatically set / reset)
#define	TWI_SR_TXBUFE (0x1u << 15)
	(TWI_SR) TX Buffer Empty
#define	TWI_SR_TXCOMP (0x1u << 0)
	(TWI_SR) Transmission Completed (automatically set / reset)
#define	TWI_SR_TXRDY (0x1u << 2)
	(TWI_SR) Transmit Holding Register Ready (automatically set / reset)
#define	TWI_TCR_TXCTR(value)
#define	TWI_TCR_TXCTR_Msk (0xffffu << TWI_TCR_TXCTR_Pos)
	(TWI_TCR) Transmit Counter Register
#define	TWI_TCR_TXCTR_Pos 0
#define	TWI_THR_TXDATA(value)
#define	TWI_THR_TXDATA_Msk (0xffu << TWI_THR_TXDATA_Pos)
	(TWI_THR) Master or Slave Transmit Holding Data
#define	TWI_THR_TXDATA_Pos 0
#define	TWI_TNCR_TXNCTR(value)
#define	TWI_TNCR_TXNCTR_Msk (0xffffu << TWI_TNCR_TXNCTR_Pos)
	(TWI_TNCR) Transmit Counter Next
#define	TWI_TNCR_TXNCTR_Pos 0
#define	TWI_TNPR_TXNPTR(value)
#define	TWI_TNPR_TXNPTR_Msk (0xffffffffu << TWI_TNPR_TXNPTR_Pos)
	(TWI_TNPR) Transmit Next Pointer
#define	TWI_TNPR_TXNPTR_Pos 0
#define	TWI_TPR_TXPTR(value)
#define	TWI_TPR_TXPTR_Msk (0xffffffffu << TWI_TPR_TXPTR_Pos)
	(TWI_TPR) Transmit Counter Register
#define	TWI_TPR_TXPTR_Pos 0

Detailed Description

and its subsidiaries.

\cond ASF_LICENSE

Definition in file component_twi.h.

Macro Definition Documentation

◆ TWI_CR_MSDIS

#define TWI_CR_MSDIS (0x1u << 3)

(TWI_CR) TWI Master Mode Disabled

Definition at line 76 of file component_twi.h.

Referenced by twi_disable_master_mode(), twi_enable_master_mode(), and twi_enable_slave_mode().

◆ TWI_CR_MSEN

#define TWI_CR_MSEN (0x1u << 2)

(TWI_CR) TWI Master Mode Enabled

Definition at line 75 of file component_twi.h.

Referenced by twi_enable_master_mode().

◆ TWI_CR_QUICK

#define TWI_CR_QUICK (0x1u << 6)

(TWI_CR) SMBUS Quick Command

Definition at line 79 of file component_twi.h.

Referenced by twi_master_init().

◆ TWI_CR_START

#define TWI_CR_START (0x1u << 0)

(TWI_CR) Send a START Condition

Definition at line 73 of file component_twi.h.

Referenced by twi_master_read().

◆ TWI_CR_STOP

#define TWI_CR_STOP (0x1u << 1)

(TWI_CR) Send a STOP Condition

Definition at line 74 of file component_twi.h.

Referenced by twi_master_read(), and twi_master_write().

◆ TWI_CR_SVDIS

#define TWI_CR_SVDIS (0x1u << 5)

(TWI_CR) TWI Slave Mode Disabled

Definition at line 78 of file component_twi.h.

Referenced by twi_disable_slave_mode(), twi_enable_master_mode(), and twi_enable_slave_mode().

◆ TWI_CR_SVEN

#define TWI_CR_SVEN (0x1u << 4)

(TWI_CR) TWI Slave Mode Enabled

Definition at line 77 of file component_twi.h.

Referenced by twi_enable_slave_mode().

◆ TWI_CR_SWRST

#define TWI_CR_SWRST (0x1u << 7)

(TWI_CR) Software Reset

Definition at line 80 of file component_twi.h.

Referenced by twi_reset().

◆ TWI_CWGR_CHDIV

#define TWI_CWGR_CHDIV ( value )

Value:

((TWI_CWGR_CHDIV_Msk & ((value) << TWI_CWGR_CHDIV_Pos)))

TWI_CWGR_CHDIV_Pos

#define TWI_CWGR_CHDIV_Pos

Definition component_twi.h:104

TWI_CWGR_CHDIV_Msk

#define TWI_CWGR_CHDIV_Msk

(TWI_CWGR) Clock High Divider

Definition component_twi.h:105

Definition at line 106 of file component_twi.h.

Referenced by twi_set_speed().

◆ TWI_CWGR_CHDIV_Msk

#define TWI_CWGR_CHDIV_Msk (0xffu << TWI_CWGR_CHDIV_Pos)

(TWI_CWGR) Clock High Divider

Definition at line 105 of file component_twi.h.

◆ TWI_CWGR_CHDIV_Pos

#define TWI_CWGR_CHDIV_Pos 8

Definition at line 104 of file component_twi.h.

◆ TWI_CWGR_CKDIV

#define TWI_CWGR_CKDIV ( value )

Value:

((TWI_CWGR_CKDIV_Msk & ((value) << TWI_CWGR_CKDIV_Pos)))

TWI_CWGR_CKDIV_Msk

#define TWI_CWGR_CKDIV_Msk

(TWI_CWGR) Clock Divider

Definition component_twi.h:108

TWI_CWGR_CKDIV_Pos

#define TWI_CWGR_CKDIV_Pos

Definition component_twi.h:107

Definition at line 109 of file component_twi.h.

Referenced by twi_set_speed().

◆ TWI_CWGR_CKDIV_Msk

#define TWI_CWGR_CKDIV_Msk (0x7u << TWI_CWGR_CKDIV_Pos)

(TWI_CWGR) Clock Divider

Definition at line 108 of file component_twi.h.

◆ TWI_CWGR_CKDIV_Pos

#define TWI_CWGR_CKDIV_Pos 16

Definition at line 107 of file component_twi.h.

◆ TWI_CWGR_CLDIV

#define TWI_CWGR_CLDIV ( value )

Value:

((TWI_CWGR_CLDIV_Msk & ((value) << TWI_CWGR_CLDIV_Pos)))

TWI_CWGR_CLDIV_Msk

#define TWI_CWGR_CLDIV_Msk

(TWI_CWGR) Clock Low Divider

Definition component_twi.h:102

TWI_CWGR_CLDIV_Pos

#define TWI_CWGR_CLDIV_Pos

Definition component_twi.h:101

Definition at line 103 of file component_twi.h.

Referenced by twi_set_speed().

◆ TWI_CWGR_CLDIV_Msk

#define TWI_CWGR_CLDIV_Msk (0xffu << TWI_CWGR_CLDIV_Pos)

(TWI_CWGR) Clock Low Divider

Definition at line 102 of file component_twi.h.

◆ TWI_CWGR_CLDIV_Pos

#define TWI_CWGR_CLDIV_Pos 0

Definition at line 101 of file component_twi.h.

◆ TWI_IADR_IADR

#define TWI_IADR_IADR ( value )

Value:

((TWI_IADR_IADR_Msk & ((value) << TWI_IADR_IADR_Pos)))

TWI_IADR_IADR_Pos

#define TWI_IADR_IADR_Pos

Definition component_twi.h:97

TWI_IADR_IADR_Msk

#define TWI_IADR_IADR_Msk

(TWI_IADR) Internal Address

Definition component_twi.h:98

Definition at line 99 of file component_twi.h.

◆ TWI_IADR_IADR_Msk

#define TWI_IADR_IADR_Msk (0xffffffu << TWI_IADR_IADR_Pos)

(TWI_IADR) Internal Address

Definition at line 98 of file component_twi.h.

◆ TWI_IADR_IADR_Pos

#define TWI_IADR_IADR_Pos 0

Definition at line 97 of file component_twi.h.

◆ TWI_IDR_ARBLST

#define TWI_IDR_ARBLST (0x1u << 9)

(TWI_IDR) Arbitration Lost Interrupt Disable

Definition at line 149 of file component_twi.h.

◆ TWI_IDR_ENDRX

#define TWI_IDR_ENDRX (0x1u << 12)

(TWI_IDR) End of Receive Buffer Interrupt Disable

Definition at line 152 of file component_twi.h.

◆ TWI_IDR_ENDTX

#define TWI_IDR_ENDTX (0x1u << 13)

(TWI_IDR) End of Transmit Buffer Interrupt Disable

Definition at line 153 of file component_twi.h.

◆ TWI_IDR_EOSACC

#define TWI_IDR_EOSACC (0x1u << 11)

(TWI_IDR) End Of Slave Access Interrupt Disable

Definition at line 151 of file component_twi.h.

◆ TWI_IDR_GACC

#define TWI_IDR_GACC (0x1u << 5)

(TWI_IDR) General Call Access Interrupt Disable

Definition at line 146 of file component_twi.h.

◆ TWI_IDR_NACK

#define TWI_IDR_NACK (0x1u << 8)

(TWI_IDR) Not Acknowledge Interrupt Disable

Definition at line 148 of file component_twi.h.

◆ TWI_IDR_OVRE

#define TWI_IDR_OVRE (0x1u << 6)

(TWI_IDR) Overrun Error Interrupt Disable

Definition at line 147 of file component_twi.h.

◆ TWI_IDR_RXBUFF

#define TWI_IDR_RXBUFF (0x1u << 14)

(TWI_IDR) Receive Buffer Full Interrupt Disable

Definition at line 154 of file component_twi.h.

◆ TWI_IDR_RXRDY

#define TWI_IDR_RXRDY (0x1u << 1)

(TWI_IDR) Receive Holding Register Ready Interrupt Disable

Definition at line 143 of file component_twi.h.

◆ TWI_IDR_SCL_WS

#define TWI_IDR_SCL_WS (0x1u << 10)

(TWI_IDR) Clock Wait State Interrupt Disable

Definition at line 150 of file component_twi.h.

◆ TWI_IDR_SVACC

#define TWI_IDR_SVACC (0x1u << 4)

(TWI_IDR) Slave Access Interrupt Disable

Definition at line 145 of file component_twi.h.

◆ TWI_IDR_TXBUFE

#define TWI_IDR_TXBUFE (0x1u << 15)

(TWI_IDR) Transmit Buffer Empty Interrupt Disable

Definition at line 155 of file component_twi.h.

◆ TWI_IDR_TXCOMP

#define TWI_IDR_TXCOMP (0x1u << 0)

(TWI_IDR) Transmission Completed Interrupt Disable

Definition at line 142 of file component_twi.h.

◆ TWI_IDR_TXRDY

#define TWI_IDR_TXRDY (0x1u << 2)

(TWI_IDR) Transmit Holding Register Ready Interrupt Disable

Definition at line 144 of file component_twi.h.

◆ TWI_IER_ARBLST

#define TWI_IER_ARBLST (0x1u << 9)

(TWI_IER) Arbitration Lost Interrupt Enable

Definition at line 134 of file component_twi.h.

◆ TWI_IER_ENDRX

#define TWI_IER_ENDRX (0x1u << 12)

(TWI_IER) End of Receive Buffer Interrupt Enable

Definition at line 137 of file component_twi.h.

◆ TWI_IER_ENDTX

#define TWI_IER_ENDTX (0x1u << 13)

(TWI_IER) End of Transmit Buffer Interrupt Enable

Definition at line 138 of file component_twi.h.

◆ TWI_IER_EOSACC

#define TWI_IER_EOSACC (0x1u << 11)

(TWI_IER) End Of Slave Access Interrupt Enable

Definition at line 136 of file component_twi.h.

◆ TWI_IER_GACC

#define TWI_IER_GACC (0x1u << 5)

(TWI_IER) General Call Access Interrupt Enable

Definition at line 131 of file component_twi.h.

◆ TWI_IER_NACK

#define TWI_IER_NACK (0x1u << 8)

(TWI_IER) Not Acknowledge Interrupt Enable

Definition at line 133 of file component_twi.h.

◆ TWI_IER_OVRE

#define TWI_IER_OVRE (0x1u << 6)

(TWI_IER) Overrun Error Interrupt Enable

Definition at line 132 of file component_twi.h.

◆ TWI_IER_RXBUFF

#define TWI_IER_RXBUFF (0x1u << 14)

(TWI_IER) Receive Buffer Full Interrupt Enable

Definition at line 139 of file component_twi.h.

◆ TWI_IER_RXRDY

#define TWI_IER_RXRDY (0x1u << 1)

(TWI_IER) Receive Holding Register Ready Interrupt Enable

Definition at line 128 of file component_twi.h.

◆ TWI_IER_SCL_WS

#define TWI_IER_SCL_WS (0x1u << 10)

(TWI_IER) Clock Wait State Interrupt Enable

Definition at line 135 of file component_twi.h.

◆ TWI_IER_SVACC

#define TWI_IER_SVACC (0x1u << 4)

(TWI_IER) Slave Access Interrupt Enable

Definition at line 130 of file component_twi.h.

◆ TWI_IER_TXBUFE

#define TWI_IER_TXBUFE (0x1u << 15)

(TWI_IER) Transmit Buffer Empty Interrupt Enable

Definition at line 140 of file component_twi.h.

◆ TWI_IER_TXCOMP

#define TWI_IER_TXCOMP (0x1u << 0)

(TWI_IER) Transmission Completed Interrupt Enable

Definition at line 127 of file component_twi.h.

◆ TWI_IER_TXRDY

#define TWI_IER_TXRDY (0x1u << 2)

(TWI_IER) Transmit Holding Register Ready Interrupt Enable

Definition at line 129 of file component_twi.h.

◆ TWI_IMR_ARBLST

#define TWI_IMR_ARBLST (0x1u << 9)

(TWI_IMR) Arbitration Lost Interrupt Mask

Definition at line 164 of file component_twi.h.

◆ TWI_IMR_ENDRX

#define TWI_IMR_ENDRX (0x1u << 12)

(TWI_IMR) End of Receive Buffer Interrupt Mask

Definition at line 167 of file component_twi.h.

◆ TWI_IMR_ENDTX

#define TWI_IMR_ENDTX (0x1u << 13)

(TWI_IMR) End of Transmit Buffer Interrupt Mask

Definition at line 168 of file component_twi.h.

◆ TWI_IMR_EOSACC

#define TWI_IMR_EOSACC (0x1u << 11)

(TWI_IMR) End Of Slave Access Interrupt Mask

Definition at line 166 of file component_twi.h.

◆ TWI_IMR_GACC

#define TWI_IMR_GACC (0x1u << 5)

(TWI_IMR) General Call Access Interrupt Mask

Definition at line 161 of file component_twi.h.

◆ TWI_IMR_NACK

#define TWI_IMR_NACK (0x1u << 8)

(TWI_IMR) Not Acknowledge Interrupt Mask

Definition at line 163 of file component_twi.h.

◆ TWI_IMR_OVRE

#define TWI_IMR_OVRE (0x1u << 6)

(TWI_IMR) Overrun Error Interrupt Mask

Definition at line 162 of file component_twi.h.

◆ TWI_IMR_RXBUFF

#define TWI_IMR_RXBUFF (0x1u << 14)

(TWI_IMR) Receive Buffer Full Interrupt Mask

Definition at line 169 of file component_twi.h.

◆ TWI_IMR_RXRDY

#define TWI_IMR_RXRDY (0x1u << 1)

(TWI_IMR) Receive Holding Register Ready Interrupt Mask

Definition at line 158 of file component_twi.h.

◆ TWI_IMR_SCL_WS

#define TWI_IMR_SCL_WS (0x1u << 10)

(TWI_IMR) Clock Wait State Interrupt Mask

Definition at line 165 of file component_twi.h.

◆ TWI_IMR_SVACC

#define TWI_IMR_SVACC (0x1u << 4)

(TWI_IMR) Slave Access Interrupt Mask

Definition at line 160 of file component_twi.h.

◆ TWI_IMR_TXBUFE

#define TWI_IMR_TXBUFE (0x1u << 15)

(TWI_IMR) Transmit Buffer Empty Interrupt Mask

Definition at line 170 of file component_twi.h.

◆ TWI_IMR_TXCOMP

#define TWI_IMR_TXCOMP (0x1u << 0)

(TWI_IMR) Transmission Completed Interrupt Mask

Definition at line 157 of file component_twi.h.

◆ TWI_IMR_TXRDY

#define TWI_IMR_TXRDY (0x1u << 2)

(TWI_IMR) Transmit Holding Register Ready Interrupt Mask

Definition at line 159 of file component_twi.h.

◆ TWI_MMR_DADR

#define TWI_MMR_DADR ( value )

Value:

((TWI_MMR_DADR_Msk & ((value) << TWI_MMR_DADR_Pos)))

TWI_MMR_DADR_Pos

#define TWI_MMR_DADR_Pos

Definition component_twi.h:89

TWI_MMR_DADR_Msk

#define TWI_MMR_DADR_Msk

(TWI_MMR) Device Address

Definition component_twi.h:90

Definition at line 91 of file component_twi.h.

Referenced by twi_master_read(), and twi_master_write().

◆ TWI_MMR_DADR_Msk

#define TWI_MMR_DADR_Msk (0x7fu << TWI_MMR_DADR_Pos)

(TWI_MMR) Device Address

Definition at line 90 of file component_twi.h.

◆ TWI_MMR_DADR_Pos

#define TWI_MMR_DADR_Pos 16

Definition at line 89 of file component_twi.h.

◆ TWI_MMR_IADRSZ_1_BYTE

#define TWI_MMR_IADRSZ_1_BYTE (0x1u << 8)

(TWI_MMR) One-byte internal device address

Definition at line 85 of file component_twi.h.

◆ TWI_MMR_IADRSZ_2_BYTE

#define TWI_MMR_IADRSZ_2_BYTE (0x2u << 8)

(TWI_MMR) Two-byte internal device address

Definition at line 86 of file component_twi.h.

◆ TWI_MMR_IADRSZ_3_BYTE

#define TWI_MMR_IADRSZ_3_BYTE (0x3u << 8)

(TWI_MMR) Three-byte internal device address

Definition at line 87 of file component_twi.h.

◆ TWI_MMR_IADRSZ_Msk

#define TWI_MMR_IADRSZ_Msk (0x3u << TWI_MMR_IADRSZ_Pos)

(TWI_MMR) Internal Device Address Size

Definition at line 83 of file component_twi.h.

Referenced by twi_master_read(), and twi_master_write().

◆ TWI_MMR_IADRSZ_NONE

#define TWI_MMR_IADRSZ_NONE (0x0u << 8)

(TWI_MMR) No internal device address

Definition at line 84 of file component_twi.h.

◆ TWI_MMR_IADRSZ_Pos

#define TWI_MMR_IADRSZ_Pos 8

Definition at line 82 of file component_twi.h.

Referenced by twi_master_read(), and twi_master_write().

◆ TWI_MMR_MREAD

#define TWI_MMR_MREAD (0x1u << 12)

(TWI_MMR) Master Read Direction

Definition at line 88 of file component_twi.h.

Referenced by twi_master_read().

◆ TWI_PTCR_RXTDIS

#define TWI_PTCR_RXTDIS (0x1u << 1)

(TWI_PTCR) Receiver Transfer Disable

Definition at line 212 of file component_twi.h.

◆ TWI_PTCR_RXTEN

#define TWI_PTCR_RXTEN (0x1u << 0)

(TWI_PTCR) Receiver Transfer Enable

Definition at line 211 of file component_twi.h.

◆ TWI_PTCR_TXTDIS

#define TWI_PTCR_TXTDIS (0x1u << 9)

(TWI_PTCR) Transmitter Transfer Disable

Definition at line 214 of file component_twi.h.

◆ TWI_PTCR_TXTEN

#define TWI_PTCR_TXTEN (0x1u << 8)

(TWI_PTCR) Transmitter Transfer Enable

Definition at line 213 of file component_twi.h.

◆ TWI_PTSR_RXTEN

#define TWI_PTSR_RXTEN (0x1u << 0)

(TWI_PTSR) Receiver Transfer Enable

Definition at line 216 of file component_twi.h.

◆ TWI_PTSR_TXTEN

#define TWI_PTSR_TXTEN (0x1u << 8)

(TWI_PTSR) Transmitter Transfer Enable

Definition at line 217 of file component_twi.h.

◆ TWI_RCR_RXCTR

#define TWI_RCR_RXCTR ( value )

Value:

((TWI_RCR_RXCTR_Msk & ((value) << TWI_RCR_RXCTR_Pos)))

TWI_RCR_RXCTR_Msk

#define TWI_RCR_RXCTR_Msk

(TWI_RCR) Receive Counter Register

Definition component_twi.h:184

TWI_RCR_RXCTR_Pos

#define TWI_RCR_RXCTR_Pos

Definition component_twi.h:183

Definition at line 185 of file component_twi.h.

◆ TWI_RCR_RXCTR_Msk

#define TWI_RCR_RXCTR_Msk (0xffffu << TWI_RCR_RXCTR_Pos)

(TWI_RCR) Receive Counter Register

Definition at line 184 of file component_twi.h.

◆ TWI_RCR_RXCTR_Pos

#define TWI_RCR_RXCTR_Pos 0

Definition at line 183 of file component_twi.h.

◆ TWI_RHR_RXDATA_Msk

#define TWI_RHR_RXDATA_Msk (0xffu << TWI_RHR_RXDATA_Pos)

(TWI_RHR) Master or Slave Receive Holding Data

Definition at line 173 of file component_twi.h.

◆ TWI_RHR_RXDATA_Pos

#define TWI_RHR_RXDATA_Pos 0

Definition at line 172 of file component_twi.h.

◆ TWI_RNCR_RXNCTR

#define TWI_RNCR_RXNCTR ( value )

Value:

((TWI_RNCR_RXNCTR_Msk & ((value) << TWI_RNCR_RXNCTR_Pos)))

TWI_RNCR_RXNCTR_Msk

#define TWI_RNCR_RXNCTR_Msk

(TWI_RNCR) Receive Next Counter

Definition component_twi.h:200

TWI_RNCR_RXNCTR_Pos

#define TWI_RNCR_RXNCTR_Pos

Definition component_twi.h:199

Definition at line 201 of file component_twi.h.

◆ TWI_RNCR_RXNCTR_Msk

#define TWI_RNCR_RXNCTR_Msk (0xffffu << TWI_RNCR_RXNCTR_Pos)

(TWI_RNCR) Receive Next Counter

Definition at line 200 of file component_twi.h.

◆ TWI_RNCR_RXNCTR_Pos

#define TWI_RNCR_RXNCTR_Pos 0

Definition at line 199 of file component_twi.h.

◆ TWI_RNPR_RXNPTR

#define TWI_RNPR_RXNPTR ( value )

Value:

((TWI_RNPR_RXNPTR_Msk & ((value) << TWI_RNPR_RXNPTR_Pos)))

TWI_RNPR_RXNPTR_Pos

#define TWI_RNPR_RXNPTR_Pos

Definition component_twi.h:195

TWI_RNPR_RXNPTR_Msk

#define TWI_RNPR_RXNPTR_Msk

(TWI_RNPR) Receive Next Pointer

Definition component_twi.h:196

Definition at line 197 of file component_twi.h.

◆ TWI_RNPR_RXNPTR_Msk

#define TWI_RNPR_RXNPTR_Msk (0xffffffffu << TWI_RNPR_RXNPTR_Pos)

(TWI_RNPR) Receive Next Pointer

Definition at line 196 of file component_twi.h.

◆ TWI_RNPR_RXNPTR_Pos

#define TWI_RNPR_RXNPTR_Pos 0

Definition at line 195 of file component_twi.h.

◆ TWI_RPR_RXPTR

#define TWI_RPR_RXPTR ( value )

Value:

((TWI_RPR_RXPTR_Msk & ((value) << TWI_RPR_RXPTR_Pos)))

TWI_RPR_RXPTR_Pos

#define TWI_RPR_RXPTR_Pos

Definition component_twi.h:179

TWI_RPR_RXPTR_Msk

#define TWI_RPR_RXPTR_Msk

(TWI_RPR) Receive Pointer Register

Definition component_twi.h:180

Definition at line 181 of file component_twi.h.

◆ TWI_RPR_RXPTR_Msk

#define TWI_RPR_RXPTR_Msk (0xffffffffu << TWI_RPR_RXPTR_Pos)

(TWI_RPR) Receive Pointer Register

Definition at line 180 of file component_twi.h.

◆ TWI_RPR_RXPTR_Pos

#define TWI_RPR_RXPTR_Pos 0

Definition at line 179 of file component_twi.h.

◆ TWI_SMR_SADR

#define TWI_SMR_SADR ( value )

Value:

((TWI_SMR_SADR_Msk & ((value) << TWI_SMR_SADR_Pos)))

TWI_SMR_SADR_Pos

#define TWI_SMR_SADR_Pos

Definition component_twi.h:93

TWI_SMR_SADR_Msk

#define TWI_SMR_SADR_Msk

(TWI_SMR) Slave Address

Definition component_twi.h:94

Definition at line 95 of file component_twi.h.

Referenced by twi_set_slave_addr(), and twi_slave_init().

◆ TWI_SMR_SADR_Msk

#define TWI_SMR_SADR_Msk (0x7fu << TWI_SMR_SADR_Pos)

(TWI_SMR) Slave Address

Definition at line 94 of file component_twi.h.

◆ TWI_SMR_SADR_Pos

#define TWI_SMR_SADR_Pos 16

Definition at line 93 of file component_twi.h.

◆ TWI_SR_ARBLST

#define TWI_SR_ARBLST (0x1u << 9)

(TWI_SR) Arbitration Lost (clear on read)

Definition at line 119 of file component_twi.h.

◆ TWI_SR_ENDRX

#define TWI_SR_ENDRX (0x1u << 12)

(TWI_SR) End of RX buffer

Definition at line 122 of file component_twi.h.

◆ TWI_SR_ENDTX

#define TWI_SR_ENDTX (0x1u << 13)

(TWI_SR) End of TX buffer

Definition at line 123 of file component_twi.h.

◆ TWI_SR_EOSACC

#define TWI_SR_EOSACC (0x1u << 11)

(TWI_SR) End Of Slave Access (clear on read)

Definition at line 121 of file component_twi.h.

Referenced by twi_slave_read(), and twi_slave_write().

◆ TWI_SR_GACC

#define TWI_SR_GACC (0x1u << 5)

(TWI_SR) General Call Access (clear on read)

Definition at line 116 of file component_twi.h.

Referenced by twi_slave_read(), and twi_slave_write().

◆ TWI_SR_NACK

#define TWI_SR_NACK (0x1u << 8)

(TWI_SR) Not Acknowledged (clear on read)

Definition at line 118 of file component_twi.h.

Referenced by twi_master_read(), and twi_master_write().

◆ TWI_SR_OVRE

#define TWI_SR_OVRE (0x1u << 6)

(TWI_SR) Overrun Error (clear on read)

Definition at line 117 of file component_twi.h.

◆ TWI_SR_RXBUFF

#define TWI_SR_RXBUFF (0x1u << 14)

(TWI_SR) RX Buffer Full

Definition at line 124 of file component_twi.h.

◆ TWI_SR_RXRDY

#define TWI_SR_RXRDY (0x1u << 1)

(TWI_SR) Receive Holding Register Ready (automatically set / reset)

Definition at line 112 of file component_twi.h.

Referenced by twi_master_read(), and twi_slave_read().

◆ TWI_SR_SCLWS

#define TWI_SR_SCLWS (0x1u << 10)

(TWI_SR) Clock Wait State (automatically set / reset)

Definition at line 120 of file component_twi.h.

◆ TWI_SR_SVACC

#define TWI_SR_SVACC (0x1u << 4)

(TWI_SR) Slave Access (automatically set / reset)

Definition at line 115 of file component_twi.h.

Referenced by twi_slave_read(), and twi_slave_write().

◆ TWI_SR_SVREAD

#define TWI_SR_SVREAD (0x1u << 3)

(TWI_SR) Slave Read (automatically set / reset)

Definition at line 114 of file component_twi.h.

Referenced by twi_slave_read(), and twi_slave_write().

◆ TWI_SR_TXBUFE

#define TWI_SR_TXBUFE (0x1u << 15)

(TWI_SR) TX Buffer Empty

Definition at line 125 of file component_twi.h.

◆ TWI_SR_TXCOMP

#define TWI_SR_TXCOMP (0x1u << 0)

(TWI_SR) Transmission Completed (automatically set / reset)

Definition at line 111 of file component_twi.h.

Referenced by twi_master_read(), twi_master_write(), twi_slave_read(), and twi_slave_write().

◆ TWI_SR_TXRDY

#define TWI_SR_TXRDY (0x1u << 2)

(TWI_SR) Transmit Holding Register Ready (automatically set / reset)

Definition at line 113 of file component_twi.h.

Referenced by twi_master_write(), and twi_slave_write().

◆ TWI_TCR_TXCTR

#define TWI_TCR_TXCTR ( value )

Value:

((TWI_TCR_TXCTR_Msk & ((value) << TWI_TCR_TXCTR_Pos)))

TWI_TCR_TXCTR_Pos

#define TWI_TCR_TXCTR_Pos

Definition component_twi.h:191

TWI_TCR_TXCTR_Msk

#define TWI_TCR_TXCTR_Msk

(TWI_TCR) Transmit Counter Register

Definition component_twi.h:192

Definition at line 193 of file component_twi.h.

◆ TWI_TCR_TXCTR_Msk

#define TWI_TCR_TXCTR_Msk (0xffffu << TWI_TCR_TXCTR_Pos)

(TWI_TCR) Transmit Counter Register

Definition at line 192 of file component_twi.h.

◆ TWI_TCR_TXCTR_Pos

#define TWI_TCR_TXCTR_Pos 0

Definition at line 191 of file component_twi.h.

◆ TWI_THR_TXDATA

#define TWI_THR_TXDATA ( value )

Value:

((TWI_THR_TXDATA_Msk & ((value) << TWI_THR_TXDATA_Pos)))

TWI_THR_TXDATA_Pos

#define TWI_THR_TXDATA_Pos

Definition component_twi.h:175

TWI_THR_TXDATA_Msk

#define TWI_THR_TXDATA_Msk

(TWI_THR) Master or Slave Transmit Holding Data

Definition component_twi.h:176

Definition at line 177 of file component_twi.h.

◆ TWI_THR_TXDATA_Msk

#define TWI_THR_TXDATA_Msk (0xffu << TWI_THR_TXDATA_Pos)

(TWI_THR) Master or Slave Transmit Holding Data

Definition at line 176 of file component_twi.h.

◆ TWI_THR_TXDATA_Pos

#define TWI_THR_TXDATA_Pos 0

Definition at line 175 of file component_twi.h.

◆ TWI_TNCR_TXNCTR

#define TWI_TNCR_TXNCTR ( value )

Value:

((TWI_TNCR_TXNCTR_Msk & ((value) << TWI_TNCR_TXNCTR_Pos)))

TWI_TNCR_TXNCTR_Msk

#define TWI_TNCR_TXNCTR_Msk

(TWI_TNCR) Transmit Counter Next

Definition component_twi.h:208

TWI_TNCR_TXNCTR_Pos

#define TWI_TNCR_TXNCTR_Pos

Definition component_twi.h:207

Definition at line 209 of file component_twi.h.

◆ TWI_TNCR_TXNCTR_Msk

#define TWI_TNCR_TXNCTR_Msk (0xffffu << TWI_TNCR_TXNCTR_Pos)

(TWI_TNCR) Transmit Counter Next

Definition at line 208 of file component_twi.h.

◆ TWI_TNCR_TXNCTR_Pos

#define TWI_TNCR_TXNCTR_Pos 0

Definition at line 207 of file component_twi.h.

◆ TWI_TNPR_TXNPTR

#define TWI_TNPR_TXNPTR ( value )

Value:

((TWI_TNPR_TXNPTR_Msk & ((value) << TWI_TNPR_TXNPTR_Pos)))

TWI_TNPR_TXNPTR_Msk

#define TWI_TNPR_TXNPTR_Msk

(TWI_TNPR) Transmit Next Pointer

Definition component_twi.h:204

TWI_TNPR_TXNPTR_Pos

#define TWI_TNPR_TXNPTR_Pos

Definition component_twi.h:203

Definition at line 205 of file component_twi.h.

◆ TWI_TNPR_TXNPTR_Msk

#define TWI_TNPR_TXNPTR_Msk (0xffffffffu << TWI_TNPR_TXNPTR_Pos)

(TWI_TNPR) Transmit Next Pointer

Definition at line 204 of file component_twi.h.

◆ TWI_TNPR_TXNPTR_Pos

#define TWI_TNPR_TXNPTR_Pos 0

Definition at line 203 of file component_twi.h.

◆ TWI_TPR_TXPTR

#define TWI_TPR_TXPTR ( value )

Value:

((TWI_TPR_TXPTR_Msk & ((value) << TWI_TPR_TXPTR_Pos)))

TWI_TPR_TXPTR_Msk

#define TWI_TPR_TXPTR_Msk

(TWI_TPR) Transmit Counter Register

Definition component_twi.h:188

TWI_TPR_TXPTR_Pos

#define TWI_TPR_TXPTR_Pos

Definition component_twi.h:187

Definition at line 189 of file component_twi.h.

◆ TWI_TPR_TXPTR_Msk

#define TWI_TPR_TXPTR_Msk (0xffffffffu << TWI_TPR_TXPTR_Pos)

(TWI_TPR) Transmit Counter Register

Definition at line 188 of file component_twi.h.

◆ TWI_TPR_TXPTR_Pos

#define TWI_TPR_TXPTR_Pos 0

Definition at line 187 of file component_twi.h.

Data Structures

Macros

Detailed Description

Macro Definition Documentation

◆ TWI_CR_MSDIS

◆ TWI_CR_MSEN

◆ TWI_CR_QUICK

◆ TWI_CR_START

◆ TWI_CR_STOP

◆ TWI_CR_SVDIS

◆ TWI_CR_SVEN

◆ TWI_CR_SWRST

◆ TWI_CWGR_CHDIV

◆ TWI_CWGR_CHDIV_Msk

◆ TWI_CWGR_CHDIV_Pos

◆ TWI_CWGR_CKDIV

◆ TWI_CWGR_CKDIV_Msk

◆ TWI_CWGR_CKDIV_Pos

◆ TWI_CWGR_CLDIV

◆ TWI_CWGR_CLDIV_Msk

◆ TWI_CWGR_CLDIV_Pos

◆ TWI_IADR_IADR

◆ TWI_IADR_IADR_Msk

◆ TWI_IADR_IADR_Pos

◆ TWI_IDR_ARBLST

◆ TWI_IDR_ENDRX

◆ TWI_IDR_ENDTX

◆ TWI_IDR_EOSACC

◆ TWI_IDR_GACC

◆ TWI_IDR_NACK

◆ TWI_IDR_OVRE

◆ TWI_IDR_RXBUFF

◆ TWI_IDR_RXRDY

◆ TWI_IDR_SCL_WS

◆ TWI_IDR_SVACC

◆ TWI_IDR_TXBUFE

◆ TWI_IDR_TXCOMP

◆ TWI_IDR_TXRDY

◆ TWI_IER_ARBLST

◆ TWI_IER_ENDRX

◆ TWI_IER_ENDTX

◆ TWI_IER_EOSACC

◆ TWI_IER_GACC

◆ TWI_IER_NACK

◆ TWI_IER_OVRE

◆ TWI_IER_RXBUFF

◆ TWI_IER_RXRDY

◆ TWI_IER_SCL_WS

◆ TWI_IER_SVACC

◆ TWI_IER_TXBUFE

◆ TWI_IER_TXCOMP

◆ TWI_IER_TXRDY

◆ TWI_IMR_ARBLST

◆ TWI_IMR_ENDRX

◆ TWI_IMR_ENDTX

◆ TWI_IMR_EOSACC

◆ TWI_IMR_GACC

◆ TWI_IMR_NACK

◆ TWI_IMR_OVRE

◆ TWI_IMR_RXBUFF

◆ TWI_IMR_RXRDY

◆ TWI_IMR_SCL_WS

◆ TWI_IMR_SVACC

◆ TWI_IMR_TXBUFE

◆ TWI_IMR_TXCOMP

◆ TWI_IMR_TXRDY

◆ TWI_MMR_DADR

◆ TWI_MMR_DADR_Msk

◆ TWI_MMR_DADR_Pos

◆ TWI_MMR_IADRSZ_1_BYTE

◆ TWI_MMR_IADRSZ_2_BYTE

◆ TWI_MMR_IADRSZ_3_BYTE

◆ TWI_MMR_IADRSZ_Msk

◆ TWI_MMR_IADRSZ_NONE

◆ TWI_MMR_IADRSZ_Pos

◆ TWI_MMR_MREAD

◆ TWI_PTCR_RXTDIS

◆ TWI_PTCR_RXTEN

◆ TWI_PTCR_TXTDIS

◆ TWI_PTCR_TXTEN