component_usart.h File Reference

Copyright (c) 2012-2018 Microchip Technology Inc. More...

Go to the source code of this file.

Data Structures
struct	Usart
	Usart hardware registers. More...

Macros
#define	US_BRGR_CD(value)
#define	US_BRGR_CD_Msk   (0xffffu << US_BRGR_CD_Pos)
	(US_BRGR) Clock Divider
#define	US_BRGR_CD_Pos   0
#define	US_BRGR_FP(value)
#define	US_BRGR_FP_Msk   (0x7u << US_BRGR_FP_Pos)
	(US_BRGR) Fractional Part
#define	US_BRGR_FP_Pos   16
#define	US_CR_DTRDIS   (0x1u << 17)
	(US_CR) Data Terminal Ready Disable
#define	US_CR_DTREN   (0x1u << 16)
	(US_CR) Data Terminal Ready Enable
#define	US_CR_FCS   (0x1u << 18)
	(US_CR) Force SPI Chip Select
#define	US_CR_RCS   (0x1u << 19)
	(US_CR) Release SPI Chip Select
#define	US_CR_RETTO   (0x1u << 15)
	(US_CR) Rearm Time-out
#define	US_CR_RSTIT   (0x1u << 13)
	(US_CR) Reset Iterations
#define	US_CR_RSTNACK   (0x1u << 14)
	(US_CR) Reset Non Acknowledge
#define	US_CR_RSTRX   (0x1u << 2)
	(US_CR) Reset Receiver
#define	US_CR_RSTSTA   (0x1u << 8)
	(US_CR) Reset Status Bits
#define	US_CR_RSTTX   (0x1u << 3)
	(US_CR) Reset Transmitter
#define	US_CR_RTSDIS   (0x1u << 19)
	(US_CR) Request to Send Disable
#define	US_CR_RTSEN   (0x1u << 18)
	(US_CR) Request to Send Enable
#define	US_CR_RXDIS   (0x1u << 5)
	(US_CR) Receiver Disable
#define	US_CR_RXEN   (0x1u << 4)
	(US_CR) Receiver Enable
#define	US_CR_SENDA   (0x1u << 12)
	(US_CR) Send Address
#define	US_CR_STPBRK   (0x1u << 10)
	(US_CR) Stop Break
#define	US_CR_STTBRK   (0x1u << 9)
	(US_CR) Start Break
#define	US_CR_STTTO   (0x1u << 11)
	(US_CR) Start Time-out
#define	US_CR_TXDIS   (0x1u << 7)
	(US_CR) Transmitter Disable
#define	US_CR_TXEN   (0x1u << 6)
	(US_CR) Transmitter Enable
#define	US_CSR_CTS   (0x1u << 23)
	(US_CSR) Image of CTS Input
#define	US_CSR_CTSIC   (0x1u << 19)
	(US_CSR) Clear to Send Input Change Flag
#define	US_CSR_DCD   (0x1u << 22)
	(US_CSR) Image of DCD Input
#define	US_CSR_DCDIC   (0x1u << 18)
	(US_CSR) Data Carrier Detect Input Change Flag
#define	US_CSR_DSR   (0x1u << 21)
	(US_CSR) Image of DSR Input
#define	US_CSR_DSRIC   (0x1u << 17)
	(US_CSR) Data Set Ready Input Change Flag
#define	US_CSR_ENDRX   (0x1u << 3)
	(US_CSR) End of Receiver Transfer
#define	US_CSR_ENDTX   (0x1u << 4)
	(US_CSR) End of Transmitter Transfer
#define	US_CSR_FRAME   (0x1u << 6)
	(US_CSR) Framing Error
#define	US_CSR_ITER   (0x1u << 10)
	(US_CSR) Max Number of Repetitions Reached
#define	US_CSR_MANERR   (0x1u << 24)
	(US_CSR) Manchester Error
#define	US_CSR_NACK   (0x1u << 13)
	(US_CSR) Non AcknowledgeInterrupt
#define	US_CSR_OVRE   (0x1u << 5)
	(US_CSR) Overrun Error
#define	US_CSR_PARE   (0x1u << 7)
	(US_CSR) Parity Error
#define	US_CSR_RI   (0x1u << 20)
	(US_CSR) Image of RI Input
#define	US_CSR_RIIC   (0x1u << 16)
	(US_CSR) Ring Indicator Input Change Flag
#define	US_CSR_RXBRK   (0x1u << 2)
	(US_CSR) Break Received/End of Break
#define	US_CSR_RXBUFF   (0x1u << 12)
	(US_CSR) Reception Buffer Full
#define	US_CSR_RXRDY   (0x1u << 0)
	(US_CSR) Receiver Ready
#define	US_CSR_TIMEOUT   (0x1u << 8)
	(US_CSR) Receiver Time-out
#define	US_CSR_TXBUFE   (0x1u << 11)
	(US_CSR) Transmission Buffer Empty
#define	US_CSR_TXEMPTY   (0x1u << 9)
	(US_CSR) Transmitter Empty
#define	US_CSR_TXRDY   (0x1u << 1)
	(US_CSR) Transmitter Ready
#define	US_CSR_UNRE   (0x1u << 10)
	(US_CSR) Underrun Error
#define	US_FIDI_FI_DI_RATIO(value)
#define	US_FIDI_FI_DI_RATIO_Msk   (0xffffu << US_FIDI_FI_DI_RATIO_Pos)
	(US_FIDI) FI Over DI Ratio Value
#define	US_FIDI_FI_DI_RATIO_Pos   0
#define	US_IDR_CTSIC   (0x1u << 19)
	(US_IDR) Clear to Send Input Change Interrupt Disable
#define	US_IDR_DCDIC   (0x1u << 18)
	(US_IDR) Data Carrier Detect Input Change Interrupt Disable
#define	US_IDR_DSRIC   (0x1u << 17)
	(US_IDR) Data Set Ready Input Change Disable
#define	US_IDR_ENDRX   (0x1u << 3)
	(US_IDR) End of Receive Transfer Interrupt Disable (available in all USART modes of operation)
#define	US_IDR_ENDTX   (0x1u << 4)
	(US_IDR) End of Transmit Interrupt Disable (available in all USART modes of operation)
#define	US_IDR_FRAME   (0x1u << 6)
	(US_IDR) Framing Error Interrupt Disable
#define	US_IDR_ITER   (0x1u << 10)
	(US_IDR) Max Number of Repetitions Reached Interrupt Disable
#define	US_IDR_MANE   (0x1u << 24)
	(US_IDR) Manchester Error Interrupt Disable
#define	US_IDR_NACK   (0x1u << 13)
	(US_IDR) Non AcknowledgeInterrupt Disable
#define	US_IDR_OVRE   (0x1u << 5)
	(US_IDR) Overrun Error Interrupt Enable
#define	US_IDR_PARE   (0x1u << 7)
	(US_IDR) Parity Error Interrupt Disable
#define	US_IDR_RIIC   (0x1u << 16)
	(US_IDR) Ring Indicator Input Change Disable
#define	US_IDR_RXBRK   (0x1u << 2)
	(US_IDR) Receiver Break Interrupt Disable
#define	US_IDR_RXBUFF   (0x1u << 12)
	(US_IDR) Buffer Full Interrupt Disable (available in all USART modes of operation)
#define	US_IDR_RXRDY   (0x1u << 0)
	(US_IDR) RXRDY Interrupt Disable
#define	US_IDR_TIMEOUT   (0x1u << 8)
	(US_IDR) Time-out Interrupt Disable
#define	US_IDR_TXBUFE   (0x1u << 11)
	(US_IDR) Buffer Empty Interrupt Disable (available in all USART modes of operation)
#define	US_IDR_TXEMPTY   (0x1u << 9)
	(US_IDR) TXEMPTY Interrupt Disable
#define	US_IDR_TXRDY   (0x1u << 1)
	(US_IDR) TXRDY Interrupt Disable
#define	US_IDR_UNRE   (0x1u << 10)
	(US_IDR) SPI Underrun Error Interrupt Disable
#define	US_IER_CTSIC   (0x1u << 19)
	(US_IER) Clear to Send Input Change Interrupt Enable
#define	US_IER_DCDIC   (0x1u << 18)
	(US_IER) Data Carrier Detect Input Change Interrupt Enable
#define	US_IER_DSRIC   (0x1u << 17)
	(US_IER) Data Set Ready Input Change Enable
#define	US_IER_ENDRX   (0x1u << 3)
	(US_IER) End of Receive Transfer Interrupt Enable (available in all USART modes of operation)
#define	US_IER_ENDTX   (0x1u << 4)
	(US_IER) End of Transmit Interrupt Enable (available in all USART modes of operation)
#define	US_IER_FRAME   (0x1u << 6)
	(US_IER) Framing Error Interrupt Enable
#define	US_IER_ITER   (0x1u << 10)
	(US_IER) Max number of Repetitions Reached Interrupt Enable
#define	US_IER_MANE   (0x1u << 24)
	(US_IER) Manchester Error Interrupt Enable
#define	US_IER_NACK   (0x1u << 13)
	(US_IER) Non AcknowledgeInterrupt Enable
#define	US_IER_OVRE   (0x1u << 5)
	(US_IER) Overrun Error Interrupt Enable
#define	US_IER_PARE   (0x1u << 7)
	(US_IER) Parity Error Interrupt Enable
#define	US_IER_RIIC   (0x1u << 16)
	(US_IER) Ring Indicator Input Change Enable
#define	US_IER_RXBRK   (0x1u << 2)
	(US_IER) Receiver Break Interrupt Enable
#define	US_IER_RXBUFF   (0x1u << 12)
	(US_IER) Buffer Full Interrupt Enable (available in all USART modes of operation)
#define	US_IER_RXRDY   (0x1u << 0)
	(US_IER) RXRDY Interrupt Enable
#define	US_IER_TIMEOUT   (0x1u << 8)
	(US_IER) Time-out Interrupt Enable
#define	US_IER_TXBUFE   (0x1u << 11)
	(US_IER) Buffer Empty Interrupt Enable (available in all USART modes of operation)
#define	US_IER_TXEMPTY   (0x1u << 9)
	(US_IER) TXEMPTY Interrupt Enable
#define	US_IER_TXRDY   (0x1u << 1)
	(US_IER) TXRDY Interrupt Enable
#define	US_IER_UNRE   (0x1u << 10)
	(US_IER) SPI Underrun Error Interrupt Enable
#define	US_IF_IRDA_FILTER(value)
#define	US_IF_IRDA_FILTER_Msk   (0xffu << US_IF_IRDA_FILTER_Pos)
	(US_IF) IrDA Filter
#define	US_IF_IRDA_FILTER_Pos   0
#define	US_IMR_CTSIC   (0x1u << 19)
	(US_IMR) Clear to Send Input Change Interrupt Mask
#define	US_IMR_DCDIC   (0x1u << 18)
	(US_IMR) Data Carrier Detect Input Change Interrupt Mask
#define	US_IMR_DSRIC   (0x1u << 17)
	(US_IMR) Data Set Ready Input Change Mask
#define	US_IMR_ENDRX   (0x1u << 3)
	(US_IMR) End of Receive Transfer Interrupt Mask (available in all USART modes of operation)
#define	US_IMR_ENDTX   (0x1u << 4)
	(US_IMR) End of Transmit Interrupt Mask (available in all USART modes of operation)
#define	US_IMR_FRAME   (0x1u << 6)
	(US_IMR) Framing Error Interrupt Mask
#define	US_IMR_ITER   (0x1u << 10)
	(US_IMR) Max Number of Repetitions Reached Interrupt Mask
#define	US_IMR_MANE   (0x1u << 24)
	(US_IMR) Manchester Error Interrupt Mask
#define	US_IMR_NACK   (0x1u << 13)
	(US_IMR) Non AcknowledgeInterrupt Mask
#define	US_IMR_OVRE   (0x1u << 5)
	(US_IMR) Overrun Error Interrupt Mask
#define	US_IMR_PARE   (0x1u << 7)
	(US_IMR) Parity Error Interrupt Mask
#define	US_IMR_RIIC   (0x1u << 16)
	(US_IMR) Ring Indicator Input Change Mask
#define	US_IMR_RXBRK   (0x1u << 2)
	(US_IMR) Receiver Break Interrupt Mask
#define	US_IMR_RXBUFF   (0x1u << 12)
	(US_IMR) Buffer Full Interrupt Mask (available in all USART modes of operation)
#define	US_IMR_RXRDY   (0x1u << 0)
	(US_IMR) RXRDY Interrupt Mask
#define	US_IMR_TIMEOUT   (0x1u << 8)
	(US_IMR) Time-out Interrupt Mask
#define	US_IMR_TXBUFE   (0x1u << 11)
	(US_IMR) Buffer Empty Interrupt Mask (available in all USART modes of operation)
#define	US_IMR_TXEMPTY   (0x1u << 9)
	(US_IMR) TXEMPTY Interrupt Mask
#define	US_IMR_TXRDY   (0x1u << 1)
	(US_IMR) TXRDY Interrupt Mask
#define	US_IMR_UNRE   (0x1u << 10)
	(US_IMR) SPI Underrun Error Interrupt Mask
#define	US_MAN_DRIFT   (0x1u << 30)
	(US_MAN) Drift Compensation
#define	US_MAN_ONE   (0x1u << 29)
	(US_MAN) Must Be Set to 1
#define	US_MAN_RX_MPOL   (0x1u << 28)
	(US_MAN) Receiver Manchester Polarity
#define	US_MAN_RX_PL(value)
#define	US_MAN_RX_PL_Msk   (0xfu << US_MAN_RX_PL_Pos)
	(US_MAN) Receiver Preamble Length
#define	US_MAN_RX_PL_Pos   16
#define	US_MAN_RX_PP_ALL_ONE   (0x0u << 24)
	(US_MAN) The preamble is composed of '1's
#define	US_MAN_RX_PP_ALL_ZERO   (0x1u << 24)
	(US_MAN) The preamble is composed of '0's
#define	US_MAN_RX_PP_Msk   (0x3u << US_MAN_RX_PP_Pos)
	(US_MAN) Receiver Preamble Pattern detected
#define	US_MAN_RX_PP_ONE_ZERO   (0x3u << 24)
	(US_MAN) The preamble is composed of '10's
#define	US_MAN_RX_PP_Pos   24
#define	US_MAN_RX_PP_ZERO_ONE   (0x2u << 24)
	(US_MAN) The preamble is composed of '01's
#define	US_MAN_TX_MPOL   (0x1u << 12)
	(US_MAN) Transmitter Manchester Polarity
#define	US_MAN_TX_PL(value)
#define	US_MAN_TX_PL_Msk   (0xfu << US_MAN_TX_PL_Pos)
	(US_MAN) Transmitter Preamble Length
#define	US_MAN_TX_PL_Pos   0
#define	US_MAN_TX_PP_ALL_ONE   (0x0u << 8)
	(US_MAN) The preamble is composed of '1's
#define	US_MAN_TX_PP_ALL_ZERO   (0x1u << 8)
	(US_MAN) The preamble is composed of '0's
#define	US_MAN_TX_PP_Msk   (0x3u << US_MAN_TX_PP_Pos)
	(US_MAN) Transmitter Preamble Pattern
#define	US_MAN_TX_PP_ONE_ZERO   (0x3u << 8)
	(US_MAN) The preamble is composed of '10's
#define	US_MAN_TX_PP_Pos   8
#define	US_MAN_TX_PP_ZERO_ONE   (0x2u << 8)
	(US_MAN) The preamble is composed of '01's
#define	US_MR_CHMODE_AUTOMATIC   (0x1u << 14)
	(US_MR) Automatic Echo.
#define	US_MR_CHMODE_LOCAL_LOOPBACK   (0x2u << 14)
	(US_MR) Local Loopback.
#define	US_MR_CHMODE_Msk   (0x3u << US_MR_CHMODE_Pos)
	(US_MR) Channel Mode
#define	US_MR_CHMODE_NORMAL   (0x0u << 14)
	(US_MR) Normal Mode
#define	US_MR_CHMODE_Pos   14
#define	US_MR_CHMODE_REMOTE_LOOPBACK   (0x3u << 14)
	(US_MR) Remote Loopback.
#define	US_MR_CHRL_5_BIT   (0x0u << 6)
	(US_MR) Character length is 5 bits
#define	US_MR_CHRL_6_BIT   (0x1u << 6)
	(US_MR) Character length is 6 bits
#define	US_MR_CHRL_7_BIT   (0x2u << 6)
	(US_MR) Character length is 7 bits
#define	US_MR_CHRL_8_BIT   (0x3u << 6)
	(US_MR) Character length is 8 bits
#define	US_MR_CHRL_Msk   (0x3u << US_MR_CHRL_Pos)
	(US_MR) Character Length
#define	US_MR_CHRL_Pos   6
#define	US_MR_CLKO   (0x1u << 18)
	(US_MR) Clock Output Select
#define	US_MR_CPHA   (0x1u << 8)
	(US_MR) SPI Clock Phase
#define	US_MR_CPOL   (0x1u << 16)
	(US_MR) SPI Clock Polarity
#define	US_MR_DSNACK   (0x1u << 21)
	(US_MR) Disable Successive NACK
#define	US_MR_FILTER   (0x1u << 28)
	(US_MR) Infrared Receive Line Filter
#define	US_MR_INACK   (0x1u << 20)
	(US_MR) Inhibit Non Acknowledge
#define	US_MR_INVDATA   (0x1u << 23)
	(US_MR) Inverted Data
#define	US_MR_MAN   (0x1u << 29)
	(US_MR) Manchester Encoder/Decoder Enable
#define	US_MR_MAX_ITERATION(value)
#define	US_MR_MAX_ITERATION_Msk   (0x7u << US_MR_MAX_ITERATION_Pos)
	(US_MR) Maximum Number of Automatic Iteration
#define	US_MR_MAX_ITERATION_Pos   24
#define	US_MR_MODE9   (0x1u << 17)
	(US_MR) 9-bit Character Length
#define	US_MR_MODSYNC   (0x1u << 30)
	(US_MR) Manchester Synchronization Mode
#define	US_MR_MSBF   (0x1u << 16)
	(US_MR) Bit Order
#define	US_MR_NBSTOP_1_5_BIT   (0x1u << 12)
	(US_MR) 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1)
#define	US_MR_NBSTOP_1_BIT   (0x0u << 12)
	(US_MR) 1 stop bit
#define	US_MR_NBSTOP_2_BIT   (0x2u << 12)
	(US_MR) 2 stop bits
#define	US_MR_NBSTOP_Msk   (0x3u << US_MR_NBSTOP_Pos)
	(US_MR) Number of Stop Bits
#define	US_MR_NBSTOP_Pos   12
#define	US_MR_ONEBIT   (0x1u << 31)
	(US_MR) Start Frame Delimiter Selector
#define	US_MR_OVER   (0x1u << 19)
	(US_MR) Oversampling Mode
#define	US_MR_PAR_EVEN   (0x0u << 9)
	(US_MR) Even parity
#define	US_MR_PAR_MARK   (0x3u << 9)
	(US_MR) Parity forced to 1 (Mark)
#define	US_MR_PAR_Msk   (0x7u << US_MR_PAR_Pos)
	(US_MR) Parity Type
#define	US_MR_PAR_MULTIDROP   (0x6u << 9)
	(US_MR) Multidrop mode
#define	US_MR_PAR_NO   (0x4u << 9)
	(US_MR) No parity
#define	US_MR_PAR_ODD   (0x1u << 9)
	(US_MR) Odd parity
#define	US_MR_PAR_Pos   9
#define	US_MR_PAR_SPACE   (0x2u << 9)
	(US_MR) Parity forced to 0 (Space)
#define	US_MR_SYNC   (0x1u << 8)
	(US_MR) Synchronous Mode Select
#define	US_MR_USART_MODE_HW_HANDSHAKING   (0x2u << 0)
	(US_MR) Hardware Handshaking
#define	US_MR_USART_MODE_IRDA   (0x8u << 0)
	(US_MR) IrDA
#define	US_MR_USART_MODE_IS07816_T_0   (0x4u << 0)
	(US_MR) IS07816 Protocol: T = 0
#define	US_MR_USART_MODE_IS07816_T_1   (0x6u << 0)
	(US_MR) IS07816 Protocol: T = 1
#define	US_MR_USART_MODE_MODEM   (0x3u << 0)
	(US_MR) Modem
#define	US_MR_USART_MODE_Msk   (0xfu << US_MR_USART_MODE_Pos)
	(US_MR) USART Mode of Operation
#define	US_MR_USART_MODE_NORMAL   (0x0u << 0)
	(US_MR) Normal mode
#define	US_MR_USART_MODE_Pos   0
#define	US_MR_USART_MODE_RS485   (0x1u << 0)
	(US_MR) RS485
#define	US_MR_USART_MODE_SPI_MASTER   (0xEu << 0)
	(US_MR) SPI Master
#define	US_MR_USART_MODE_SPI_SLAVE   (0xFu << 0)
	(US_MR) SPI Slave
#define	US_MR_USCLKS_DIV   (0x1u << 4)
	(US_MR) Internal Clock Divided MCK/DIV (DIV=8) is selected
#define	US_MR_USCLKS_MCK   (0x0u << 4)
	(US_MR) Master Clock MCK is selected
#define	US_MR_USCLKS_Msk   (0x3u << US_MR_USCLKS_Pos)
	(US_MR) Clock Selection
#define	US_MR_USCLKS_Pos   4
#define	US_MR_USCLKS_SCK   (0x3u << 4)
	(US_MR) Serial Clock SLK is selected
#define	US_MR_VAR_SYNC   (0x1u << 22)
	(US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter
#define	US_MR_WRDBT   (0x1u << 20)
	(US_MR) Wait Read Data Before Transfer
#define	US_NER_NB_ERRORS_Msk   (0xffu << US_NER_NB_ERRORS_Pos)
	(US_NER) Number of Errors
#define	US_NER_NB_ERRORS_Pos   0
#define	US_PTCR_RXTDIS   (0x1u << 1)
	(US_PTCR) Receiver Transfer Disable
#define	US_PTCR_RXTEN   (0x1u << 0)
	(US_PTCR) Receiver Transfer Enable
#define	US_PTCR_TXTDIS   (0x1u << 9)
	(US_PTCR) Transmitter Transfer Disable
#define	US_PTCR_TXTEN   (0x1u << 8)
	(US_PTCR) Transmitter Transfer Enable
#define	US_PTSR_RXTEN   (0x1u << 0)
	(US_PTSR) Receiver Transfer Enable
#define	US_PTSR_TXTEN   (0x1u << 8)
	(US_PTSR) Transmitter Transfer Enable
#define	US_RCR_RXCTR(value)
#define	US_RCR_RXCTR_Msk   (0xffffu << US_RCR_RXCTR_Pos)
	(US_RCR) Receive Counter Register
#define	US_RCR_RXCTR_Pos   0
#define	US_RHR_RXCHR_Msk   (0x1ffu << US_RHR_RXCHR_Pos)
	(US_RHR) Received Character
#define	US_RHR_RXCHR_Pos   0
#define	US_RHR_RXSYNH   (0x1u << 15)
	(US_RHR) Received Sync
#define	US_RNCR_RXNCTR(value)
#define	US_RNCR_RXNCTR_Msk   (0xffffu << US_RNCR_RXNCTR_Pos)
	(US_RNCR) Receive Next Counter
#define	US_RNCR_RXNCTR_Pos   0
#define	US_RNPR_RXNPTR(value)
#define	US_RNPR_RXNPTR_Msk   (0xffffffffu << US_RNPR_RXNPTR_Pos)
	(US_RNPR) Receive Next Pointer
#define	US_RNPR_RXNPTR_Pos   0
#define	US_RPR_RXPTR(value)
#define	US_RPR_RXPTR_Msk   (0xffffffffu << US_RPR_RXPTR_Pos)
	(US_RPR) Receive Pointer Register
#define	US_RPR_RXPTR_Pos   0
#define	US_RTOR_TO(value)
#define	US_RTOR_TO_Msk   (0xffffu << US_RTOR_TO_Pos)
	(US_RTOR) Time-out Value
#define	US_RTOR_TO_Pos   0
#define	US_TCR_TXCTR(value)
#define	US_TCR_TXCTR_Msk   (0xffffu << US_TCR_TXCTR_Pos)
	(US_TCR) Transmit Counter Register
#define	US_TCR_TXCTR_Pos   0
#define	US_THR_TXCHR(value)
#define	US_THR_TXCHR_Msk   (0x1ffu << US_THR_TXCHR_Pos)
	(US_THR) Character to be Transmitted
#define	US_THR_TXCHR_Pos   0
#define	US_THR_TXSYNH   (0x1u << 15)
	(US_THR) Sync Field to be Transmitted
#define	US_TNCR_TXNCTR(value)
#define	US_TNCR_TXNCTR_Msk   (0xffffu << US_TNCR_TXNCTR_Pos)
	(US_TNCR) Transmit Counter Next
#define	US_TNCR_TXNCTR_Pos   0
#define	US_TNPR_TXNPTR(value)
#define	US_TNPR_TXNPTR_Msk   (0xffffffffu << US_TNPR_TXNPTR_Pos)
	(US_TNPR) Transmit Next Pointer
#define	US_TNPR_TXNPTR_Pos   0
#define	US_TPR_TXPTR(value)
#define	US_TPR_TXPTR_Msk   (0xffffffffu << US_TPR_TXPTR_Pos)
	(US_TPR) Transmit Counter Register
#define	US_TPR_TXPTR_Pos   0
#define	US_TTGR_TG(value)
#define	US_TTGR_TG_Msk   (0xffu << US_TTGR_TG_Pos)
	(US_TTGR) Timeguard Value
#define	US_TTGR_TG_Pos   0
#define	US_VERSION_MFN_Msk   (0x7u << US_VERSION_MFN_Pos)
	(US_VERSION) Metal Fix Number
#define	US_VERSION_MFN_Pos   16
#define	US_VERSION_VERSION_Msk   (0xfffu << US_VERSION_VERSION_Pos)
	(US_VERSION) Hardware Module Version
#define	US_VERSION_VERSION_Pos   0
#define	US_WPMR_WPEN   (0x1u << 0)
	(US_WPMR) Write Protect Enable
#define	US_WPMR_WPKEY_Msk   (0xffffffu << US_WPMR_WPKEY_Pos)
	(US_WPMR) Write Protect KEY
#define	US_WPMR_WPKEY_PASSWD   (0x555341u << 8)
	(US_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.
#define	US_WPMR_WPKEY_Pos   8
#define	US_WPSR_WPVS   (0x1u << 0)
	(US_WPSR) Write Protect Violation Status
#define	US_WPSR_WPVSRC_Msk   (0xffffu << US_WPSR_WPVSRC_Pos)
	(US_WPSR) Write Protect Violation Source
#define	US_WPSR_WPVSRC_Pos   8

Detailed Description

Copyright (c) 2012-2018 Microchip Technology Inc.

and its subsidiaries.

\cond ASF_LICENSE

Definition in file component_usart.h.

Macro Definition Documentation

US_BRGR_CD

#define US_BRGR_CD

(

value

)

Value:

((US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos)))

Definition at line 263 of file component_usart.h.

US_BRGR_CD_Msk

#define US_BRGR_CD_Msk   (0xffffu << US_BRGR_CD_Pos)

(US_BRGR) Clock Divider

Definition at line 262 of file component_usart.h.

US_BRGR_CD_Pos

#define US_BRGR_CD_Pos   0

Definition at line 261 of file component_usart.h.

Referenced by usart_set_async_baudrate(), usart_set_iso7816_clock(), usart_set_spi_master_baudrate(), and usart_set_sync_master_baudrate().

US_BRGR_FP

#define US_BRGR_FP

(

value

)

Value:

((US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos)))

Definition at line 266 of file component_usart.h.

US_BRGR_FP_Msk

#define US_BRGR_FP_Msk   (0x7u << US_BRGR_FP_Pos)

(US_BRGR) Fractional Part

Definition at line 265 of file component_usart.h.

US_BRGR_FP_Pos

#define US_BRGR_FP_Pos   16

Definition at line 264 of file component_usart.h.

Referenced by usart_set_async_baudrate().

US_CR_DTRDIS

#define US_CR_DTRDIS   (0x1u << 17)

(US_CR) Data Terminal Ready Disable

Definition at line 97 of file component_usart.h.

Referenced by usart_drive_DTR_pin_high().

US_CR_DTREN

#define US_CR_DTREN   (0x1u << 16)

(US_CR) Data Terminal Ready Enable

Definition at line 96 of file component_usart.h.

Referenced by usart_drive_DTR_pin_low().

US_CR_FCS

#define US_CR_FCS   (0x1u << 18)

(US_CR) Force SPI Chip Select

Definition at line 100 of file component_usart.h.

Referenced by usart_spi_force_chip_select().

US_CR_RCS

#define US_CR_RCS   (0x1u << 19)

(US_CR) Release SPI Chip Select

Definition at line 101 of file component_usart.h.

Referenced by usart_spi_release_chip_select().

US_CR_RETTO

#define US_CR_RETTO   (0x1u << 15)

(US_CR) Rearm Time-out

Definition at line 95 of file component_usart.h.

Referenced by usart_restart_rx_timeout().

US_CR_RSTIT

#define US_CR_RSTIT   (0x1u << 13)

(US_CR) Reset Iterations

Definition at line 93 of file component_usart.h.

Referenced by usart_reset_iterations().

US_CR_RSTNACK

#define US_CR_RSTNACK   (0x1u << 14)

(US_CR) Reset Non Acknowledge

Definition at line 94 of file component_usart.h.

Referenced by usart_reset_nack().

US_CR_RSTRX

#define US_CR_RSTRX   (0x1u << 2)

(US_CR) Reset Receiver

Definition at line 82 of file component_usart.h.

Referenced by usart_reset_rx().

US_CR_RSTSTA

#define US_CR_RSTSTA   (0x1u << 8)

(US_CR) Reset Status Bits

Definition at line 88 of file component_usart.h.

Referenced by usart_reset_status().

US_CR_RSTTX

#define US_CR_RSTTX   (0x1u << 3)

(US_CR) Reset Transmitter

Definition at line 83 of file component_usart.h.

Referenced by usart_reset_tx().

US_CR_RTSDIS

#define US_CR_RTSDIS   (0x1u << 19)

(US_CR) Request to Send Disable

Definition at line 99 of file component_usart.h.

Referenced by usart_drive_RTS_pin_high().

US_CR_RTSEN

#define US_CR_RTSEN   (0x1u << 18)

(US_CR) Request to Send Enable

Definition at line 98 of file component_usart.h.

Referenced by usart_drive_RTS_pin_low().

US_CR_RXDIS

#define US_CR_RXDIS   (0x1u << 5)

(US_CR) Receiver Disable

Definition at line 85 of file component_usart.h.

Referenced by usart_disable_rx(), and usart_reset_rx().

US_CR_RXEN

#define US_CR_RXEN   (0x1u << 4)

(US_CR) Receiver Enable

Definition at line 84 of file component_usart.h.

Referenced by usart_enable_rx().

US_CR_SENDA

#define US_CR_SENDA   (0x1u << 12)

(US_CR) Send Address

Definition at line 92 of file component_usart.h.

Referenced by usart_send_address().

US_CR_STPBRK

#define US_CR_STPBRK   (0x1u << 10)

(US_CR) Stop Break

Definition at line 90 of file component_usart.h.

Referenced by usart_stop_tx_break().

US_CR_STTBRK

#define US_CR_STTBRK   (0x1u << 9)

(US_CR) Start Break

Definition at line 89 of file component_usart.h.

Referenced by usart_start_tx_break().

US_CR_STTTO

#define US_CR_STTTO   (0x1u << 11)

(US_CR) Start Time-out

Definition at line 91 of file component_usart.h.

Referenced by usart_start_rx_timeout().

US_CR_TXDIS

#define US_CR_TXDIS   (0x1u << 7)

(US_CR) Transmitter Disable

Definition at line 87 of file component_usart.h.

Referenced by usart_disable_tx(), and usart_reset_tx().

US_CR_TXEN

#define US_CR_TXEN   (0x1u << 6)

(US_CR) Transmitter Enable

Definition at line 86 of file component_usart.h.

Referenced by usart_enable_tx().

US_CSR_CTS

#define US_CSR_CTS   (0x1u << 23)

(US_CSR) Image of CTS Input

Definition at line 248 of file component_usart.h.

US_CSR_CTSIC

#define US_CSR_CTSIC   (0x1u << 19)

(US_CSR) Clear to Send Input Change Flag

Definition at line 244 of file component_usart.h.

US_CSR_DCD

#define US_CSR_DCD   (0x1u << 22)

(US_CSR) Image of DCD Input

Definition at line 247 of file component_usart.h.

US_CSR_DCDIC

#define US_CSR_DCDIC   (0x1u << 18)

(US_CSR) Data Carrier Detect Input Change Flag

Definition at line 243 of file component_usart.h.

US_CSR_DSR

#define US_CSR_DSR   (0x1u << 21)

(US_CSR) Image of DSR Input

Definition at line 246 of file component_usart.h.

US_CSR_DSRIC

#define US_CSR_DSRIC   (0x1u << 17)

(US_CSR) Data Set Ready Input Change Flag

Definition at line 242 of file component_usart.h.

US_CSR_ENDRX

#define US_CSR_ENDRX   (0x1u << 3)

(US_CSR) End of Receiver Transfer

Definition at line 230 of file component_usart.h.

Referenced by usart_is_rx_buf_end().

US_CSR_ENDTX

#define US_CSR_ENDTX   (0x1u << 4)

(US_CSR) End of Transmitter Transfer

Definition at line 231 of file component_usart.h.

Referenced by usart_is_tx_buf_end().

US_CSR_FRAME

#define US_CSR_FRAME   (0x1u << 6)

(US_CSR) Framing Error

Definition at line 233 of file component_usart.h.

US_CSR_ITER

#define US_CSR_ITER   (0x1u << 10)

(US_CSR) Max Number of Repetitions Reached

Definition at line 237 of file component_usart.h.

US_CSR_MANERR

#define US_CSR_MANERR   (0x1u << 24)

(US_CSR) Manchester Error

Definition at line 249 of file component_usart.h.

US_CSR_NACK

#define US_CSR_NACK   (0x1u << 13)

(US_CSR) Non AcknowledgeInterrupt

Definition at line 240 of file component_usart.h.

US_CSR_OVRE

#define US_CSR_OVRE   (0x1u << 5)

(US_CSR) Overrun Error

Definition at line 232 of file component_usart.h.

US_CSR_PARE

#define US_CSR_PARE   (0x1u << 7)

(US_CSR) Parity Error

Definition at line 234 of file component_usart.h.

US_CSR_RI

#define US_CSR_RI   (0x1u << 20)

(US_CSR) Image of RI Input

Definition at line 245 of file component_usart.h.

US_CSR_RIIC

#define US_CSR_RIIC   (0x1u << 16)

(US_CSR) Ring Indicator Input Change Flag

Definition at line 241 of file component_usart.h.

US_CSR_RXBRK

#define US_CSR_RXBRK   (0x1u << 2)

(US_CSR) Break Received/End of Break

Definition at line 229 of file component_usart.h.

US_CSR_RXBUFF

#define US_CSR_RXBUFF   (0x1u << 12)

(US_CSR) Reception Buffer Full

Definition at line 239 of file component_usart.h.

Referenced by usart_is_rx_buf_full().

US_CSR_RXRDY

#define US_CSR_RXRDY   (0x1u << 0)

(US_CSR) Receiver Ready

Definition at line 227 of file component_usart.h.

Referenced by usart_getchar(), usart_is_rx_ready(), and usart_read().

US_CSR_TIMEOUT

#define US_CSR_TIMEOUT   (0x1u << 8)

(US_CSR) Receiver Time-out

Definition at line 235 of file component_usart.h.

US_CSR_TXBUFE

#define US_CSR_TXBUFE   (0x1u << 11)

(US_CSR) Transmission Buffer Empty

Definition at line 238 of file component_usart.h.

Referenced by usart_is_tx_buf_empty().

US_CSR_TXEMPTY

#define US_CSR_TXEMPTY   (0x1u << 9)

(US_CSR) Transmitter Empty

Definition at line 236 of file component_usart.h.

Referenced by usart_is_tx_empty().

US_CSR_TXRDY

#define US_CSR_TXRDY   (0x1u << 1)

(US_CSR) Transmitter Ready

Definition at line 228 of file component_usart.h.

Referenced by usart_is_tx_ready(), usart_putchar(), and usart_write().

US_CSR_UNRE

#define US_CSR_UNRE   (0x1u << 10)

(US_CSR) Underrun Error

Definition at line 250 of file component_usart.h.

US_FIDI_FI_DI_RATIO

#define US_FIDI_FI_DI_RATIO

(

value

)

Value:

((US_FIDI_FI_DI_RATIO_Msk & ((value) << US_FIDI_FI_DI_RATIO_Pos)))

Definition at line 278 of file component_usart.h.

US_FIDI_FI_DI_RATIO_Msk

#define US_FIDI_FI_DI_RATIO_Msk   (0xffffu << US_FIDI_FI_DI_RATIO_Pos)

(US_FIDI) FI Over DI Ratio Value

Definition at line 277 of file component_usart.h.

US_FIDI_FI_DI_RATIO_Pos

#define US_FIDI_FI_DI_RATIO_Pos   0

Definition at line 276 of file component_usart.h.

US_IDR_CTSIC

#define US_IDR_CTSIC   (0x1u << 19)

(US_IDR) Clear to Send Input Change Interrupt Disable

Definition at line 202 of file component_usart.h.

US_IDR_DCDIC

#define US_IDR_DCDIC   (0x1u << 18)

(US_IDR) Data Carrier Detect Input Change Interrupt Disable

Definition at line 201 of file component_usart.h.

US_IDR_DSRIC

#define US_IDR_DSRIC   (0x1u << 17)

(US_IDR) Data Set Ready Input Change Disable

Definition at line 200 of file component_usart.h.

US_IDR_ENDRX

#define US_IDR_ENDRX   (0x1u << 3)

(US_IDR) End of Receive Transfer Interrupt Disable (available in all USART modes of operation)

Definition at line 188 of file component_usart.h.

US_IDR_ENDTX

#define US_IDR_ENDTX   (0x1u << 4)

(US_IDR) End of Transmit Interrupt Disable (available in all USART modes of operation)

Definition at line 189 of file component_usart.h.

US_IDR_FRAME

#define US_IDR_FRAME   (0x1u << 6)

(US_IDR) Framing Error Interrupt Disable

Definition at line 191 of file component_usart.h.

US_IDR_ITER

#define US_IDR_ITER   (0x1u << 10)

(US_IDR) Max Number of Repetitions Reached Interrupt Disable

Definition at line 195 of file component_usart.h.

US_IDR_MANE

#define US_IDR_MANE   (0x1u << 24)

(US_IDR) Manchester Error Interrupt Disable

Definition at line 203 of file component_usart.h.

US_IDR_NACK

#define US_IDR_NACK   (0x1u << 13)

(US_IDR) Non AcknowledgeInterrupt Disable

Definition at line 198 of file component_usart.h.

US_IDR_OVRE

#define US_IDR_OVRE   (0x1u << 5)

(US_IDR) Overrun Error Interrupt Enable

Definition at line 190 of file component_usart.h.

US_IDR_PARE

#define US_IDR_PARE   (0x1u << 7)

(US_IDR) Parity Error Interrupt Disable

Definition at line 192 of file component_usart.h.

US_IDR_RIIC

#define US_IDR_RIIC   (0x1u << 16)

(US_IDR) Ring Indicator Input Change Disable

Definition at line 199 of file component_usart.h.

US_IDR_RXBRK

#define US_IDR_RXBRK   (0x1u << 2)

(US_IDR) Receiver Break Interrupt Disable

Definition at line 187 of file component_usart.h.

US_IDR_RXBUFF

#define US_IDR_RXBUFF   (0x1u << 12)

(US_IDR) Buffer Full Interrupt Disable (available in all USART modes of operation)

Definition at line 197 of file component_usart.h.

US_IDR_RXRDY

#define US_IDR_RXRDY   (0x1u << 0)

(US_IDR) RXRDY Interrupt Disable

Definition at line 185 of file component_usart.h.

US_IDR_TIMEOUT

#define US_IDR_TIMEOUT   (0x1u << 8)

(US_IDR) Time-out Interrupt Disable

Definition at line 193 of file component_usart.h.

US_IDR_TXBUFE

#define US_IDR_TXBUFE   (0x1u << 11)

(US_IDR) Buffer Empty Interrupt Disable (available in all USART modes of operation)

Definition at line 196 of file component_usart.h.

US_IDR_TXEMPTY

#define US_IDR_TXEMPTY   (0x1u << 9)

(US_IDR) TXEMPTY Interrupt Disable

Definition at line 194 of file component_usart.h.

US_IDR_TXRDY

#define US_IDR_TXRDY   (0x1u << 1)

(US_IDR) TXRDY Interrupt Disable

Definition at line 186 of file component_usart.h.

US_IDR_UNRE

#define US_IDR_UNRE   (0x1u << 10)

(US_IDR) SPI Underrun Error Interrupt Disable

Definition at line 204 of file component_usart.h.

US_IER_CTSIC

#define US_IER_CTSIC   (0x1u << 19)

(US_IER) Clear to Send Input Change Interrupt Enable

Definition at line 181 of file component_usart.h.

US_IER_DCDIC

#define US_IER_DCDIC   (0x1u << 18)

(US_IER) Data Carrier Detect Input Change Interrupt Enable

Definition at line 180 of file component_usart.h.

US_IER_DSRIC

#define US_IER_DSRIC   (0x1u << 17)

(US_IER) Data Set Ready Input Change Enable

Definition at line 179 of file component_usart.h.

US_IER_ENDRX

#define US_IER_ENDRX   (0x1u << 3)

(US_IER) End of Receive Transfer Interrupt Enable (available in all USART modes of operation)

Definition at line 167 of file component_usart.h.

US_IER_ENDTX

#define US_IER_ENDTX   (0x1u << 4)

(US_IER) End of Transmit Interrupt Enable (available in all USART modes of operation)

Definition at line 168 of file component_usart.h.

US_IER_FRAME

#define US_IER_FRAME   (0x1u << 6)

(US_IER) Framing Error Interrupt Enable

Definition at line 170 of file component_usart.h.

US_IER_ITER

#define US_IER_ITER   (0x1u << 10)

(US_IER) Max number of Repetitions Reached Interrupt Enable

Definition at line 174 of file component_usart.h.

US_IER_MANE

#define US_IER_MANE   (0x1u << 24)

(US_IER) Manchester Error Interrupt Enable

Definition at line 182 of file component_usart.h.

US_IER_NACK

#define US_IER_NACK   (0x1u << 13)

(US_IER) Non AcknowledgeInterrupt Enable

Definition at line 177 of file component_usart.h.

US_IER_OVRE

#define US_IER_OVRE   (0x1u << 5)

(US_IER) Overrun Error Interrupt Enable

Definition at line 169 of file component_usart.h.

US_IER_PARE

#define US_IER_PARE   (0x1u << 7)

(US_IER) Parity Error Interrupt Enable

Definition at line 171 of file component_usart.h.

US_IER_RIIC

#define US_IER_RIIC   (0x1u << 16)

(US_IER) Ring Indicator Input Change Enable

Definition at line 178 of file component_usart.h.

US_IER_RXBRK

#define US_IER_RXBRK   (0x1u << 2)

(US_IER) Receiver Break Interrupt Enable

Definition at line 166 of file component_usart.h.

US_IER_RXBUFF

#define US_IER_RXBUFF   (0x1u << 12)

(US_IER) Buffer Full Interrupt Enable (available in all USART modes of operation)

Definition at line 176 of file component_usart.h.

US_IER_RXRDY

#define US_IER_RXRDY   (0x1u << 0)

(US_IER) RXRDY Interrupt Enable

Definition at line 164 of file component_usart.h.

US_IER_TIMEOUT

#define US_IER_TIMEOUT   (0x1u << 8)

(US_IER) Time-out Interrupt Enable

Definition at line 172 of file component_usart.h.

US_IER_TXBUFE

#define US_IER_TXBUFE   (0x1u << 11)

(US_IER) Buffer Empty Interrupt Enable (available in all USART modes of operation)

Definition at line 175 of file component_usart.h.

US_IER_TXEMPTY

#define US_IER_TXEMPTY   (0x1u << 9)

(US_IER) TXEMPTY Interrupt Enable

Definition at line 173 of file component_usart.h.

US_IER_TXRDY

#define US_IER_TXRDY   (0x1u << 1)

(US_IER) TXRDY Interrupt Enable

Definition at line 165 of file component_usart.h.

US_IER_UNRE

#define US_IER_UNRE   (0x1u << 10)

(US_IER) SPI Underrun Error Interrupt Enable

Definition at line 183 of file component_usart.h.

US_IF_IRDA_FILTER

#define US_IF_IRDA_FILTER

(

value

)

Value:

((US_IF_IRDA_FILTER_Msk & ((value) << US_IF_IRDA_FILTER_Pos)))

Definition at line 285 of file component_usart.h.

US_IF_IRDA_FILTER_Msk

#define US_IF_IRDA_FILTER_Msk   (0xffu << US_IF_IRDA_FILTER_Pos)

(US_IF) IrDA Filter

Definition at line 284 of file component_usart.h.

US_IF_IRDA_FILTER_Pos

#define US_IF_IRDA_FILTER_Pos   0

Definition at line 283 of file component_usart.h.

US_IMR_CTSIC

#define US_IMR_CTSIC   (0x1u << 19)

(US_IMR) Clear to Send Input Change Interrupt Mask

Definition at line 223 of file component_usart.h.

US_IMR_DCDIC

#define US_IMR_DCDIC   (0x1u << 18)

(US_IMR) Data Carrier Detect Input Change Interrupt Mask

Definition at line 222 of file component_usart.h.

US_IMR_DSRIC

#define US_IMR_DSRIC   (0x1u << 17)

(US_IMR) Data Set Ready Input Change Mask

Definition at line 221 of file component_usart.h.

US_IMR_ENDRX

#define US_IMR_ENDRX   (0x1u << 3)

(US_IMR) End of Receive Transfer Interrupt Mask (available in all USART modes of operation)

Definition at line 209 of file component_usart.h.

US_IMR_ENDTX

#define US_IMR_ENDTX   (0x1u << 4)

(US_IMR) End of Transmit Interrupt Mask (available in all USART modes of operation)

Definition at line 210 of file component_usart.h.

US_IMR_FRAME

#define US_IMR_FRAME   (0x1u << 6)

(US_IMR) Framing Error Interrupt Mask

Definition at line 212 of file component_usart.h.

US_IMR_ITER

#define US_IMR_ITER   (0x1u << 10)

(US_IMR) Max Number of Repetitions Reached Interrupt Mask

Definition at line 216 of file component_usart.h.

US_IMR_MANE

#define US_IMR_MANE   (0x1u << 24)

(US_IMR) Manchester Error Interrupt Mask

Definition at line 224 of file component_usart.h.

US_IMR_NACK

#define US_IMR_NACK   (0x1u << 13)

(US_IMR) Non AcknowledgeInterrupt Mask

Definition at line 219 of file component_usart.h.

US_IMR_OVRE

#define US_IMR_OVRE   (0x1u << 5)

(US_IMR) Overrun Error Interrupt Mask

Definition at line 211 of file component_usart.h.

US_IMR_PARE

#define US_IMR_PARE   (0x1u << 7)

(US_IMR) Parity Error Interrupt Mask

Definition at line 213 of file component_usart.h.

US_IMR_RIIC

#define US_IMR_RIIC   (0x1u << 16)

(US_IMR) Ring Indicator Input Change Mask

Definition at line 220 of file component_usart.h.

US_IMR_RXBRK

#define US_IMR_RXBRK   (0x1u << 2)

(US_IMR) Receiver Break Interrupt Mask

Definition at line 208 of file component_usart.h.

US_IMR_RXBUFF

#define US_IMR_RXBUFF   (0x1u << 12)

(US_IMR) Buffer Full Interrupt Mask (available in all USART modes of operation)

Definition at line 218 of file component_usart.h.

US_IMR_RXRDY

#define US_IMR_RXRDY   (0x1u << 0)

(US_IMR) RXRDY Interrupt Mask

Definition at line 206 of file component_usart.h.

US_IMR_TIMEOUT

#define US_IMR_TIMEOUT   (0x1u << 8)

(US_IMR) Time-out Interrupt Mask

Definition at line 214 of file component_usart.h.

US_IMR_TXBUFE

#define US_IMR_TXBUFE   (0x1u << 11)

(US_IMR) Buffer Empty Interrupt Mask (available in all USART modes of operation)

Definition at line 217 of file component_usart.h.

US_IMR_TXEMPTY

#define US_IMR_TXEMPTY   (0x1u << 9)

(US_IMR) TXEMPTY Interrupt Mask

Definition at line 215 of file component_usart.h.

US_IMR_TXRDY

#define US_IMR_TXRDY   (0x1u << 1)

(US_IMR) TXRDY Interrupt Mask

Definition at line 207 of file component_usart.h.

US_IMR_UNRE

#define US_IMR_UNRE   (0x1u << 10)

(US_IMR) SPI Underrun Error Interrupt Mask

Definition at line 225 of file component_usart.h.

US_MAN_DRIFT

#define US_MAN_DRIFT   (0x1u << 30)

(US_MAN) Drift Compensation

Definition at line 308 of file component_usart.h.

Referenced by usart_man_disable_drift_compensation(), and usart_man_enable_drift_compensation().

US_MAN_ONE

#define US_MAN_ONE   (0x1u << 29)

(US_MAN) Must Be Set to 1

Definition at line 307 of file component_usart.h.

US_MAN_RX_MPOL

#define US_MAN_RX_MPOL   (0x1u << 28)

(US_MAN) Receiver Manchester Polarity

Definition at line 306 of file component_usart.h.

Referenced by usart_man_set_rx_polarity().

US_MAN_RX_PL

#define US_MAN_RX_PL

(

value

)

Value:

((US_MAN_RX_PL_Msk & ((value) << US_MAN_RX_PL_Pos)))

Definition at line 299 of file component_usart.h.

Referenced by usart_man_set_rx_pre_len().

US_MAN_RX_PL_Msk

#define US_MAN_RX_PL_Msk   (0xfu << US_MAN_RX_PL_Pos)

(US_MAN) Receiver Preamble Length

Definition at line 298 of file component_usart.h.

Referenced by usart_man_set_rx_pre_len().

US_MAN_RX_PL_Pos

#define US_MAN_RX_PL_Pos   16

Definition at line 297 of file component_usart.h.

US_MAN_RX_PP_ALL_ONE

#define US_MAN_RX_PP_ALL_ONE   (0x0u << 24)

(US_MAN) The preamble is composed of '1's

Definition at line 302 of file component_usart.h.

US_MAN_RX_PP_ALL_ZERO

#define US_MAN_RX_PP_ALL_ZERO   (0x1u << 24)

(US_MAN) The preamble is composed of '0's

Definition at line 303 of file component_usart.h.

US_MAN_RX_PP_Msk

#define US_MAN_RX_PP_Msk   (0x3u << US_MAN_RX_PP_Pos)

(US_MAN) Receiver Preamble Pattern detected

Definition at line 301 of file component_usart.h.

Referenced by usart_man_set_rx_pre_pattern().

US_MAN_RX_PP_ONE_ZERO

#define US_MAN_RX_PP_ONE_ZERO   (0x3u << 24)

(US_MAN) The preamble is composed of '10's

Definition at line 305 of file component_usart.h.

US_MAN_RX_PP_Pos

#define US_MAN_RX_PP_Pos   24

Definition at line 300 of file component_usart.h.

Referenced by usart_man_set_rx_pre_pattern().

US_MAN_RX_PP_ZERO_ONE

#define US_MAN_RX_PP_ZERO_ONE   (0x2u << 24)

(US_MAN) The preamble is composed of '01's

Definition at line 304 of file component_usart.h.

US_MAN_TX_MPOL

#define US_MAN_TX_MPOL   (0x1u << 12)

(US_MAN) Transmitter Manchester Polarity

Definition at line 296 of file component_usart.h.

Referenced by usart_man_set_tx_polarity().

US_MAN_TX_PL

#define US_MAN_TX_PL

(

value

)

Value:

((US_MAN_TX_PL_Msk & ((value) << US_MAN_TX_PL_Pos)))

Definition at line 289 of file component_usart.h.

Referenced by usart_man_set_tx_pre_len().

US_MAN_TX_PL_Msk

#define US_MAN_TX_PL_Msk   (0xfu << US_MAN_TX_PL_Pos)

(US_MAN) Transmitter Preamble Length

Definition at line 288 of file component_usart.h.

Referenced by usart_man_set_tx_pre_len().

US_MAN_TX_PL_Pos

#define US_MAN_TX_PL_Pos   0

Definition at line 287 of file component_usart.h.

US_MAN_TX_PP_ALL_ONE

#define US_MAN_TX_PP_ALL_ONE   (0x0u << 8)

(US_MAN) The preamble is composed of '1's

Definition at line 292 of file component_usart.h.

US_MAN_TX_PP_ALL_ZERO

#define US_MAN_TX_PP_ALL_ZERO   (0x1u << 8)

(US_MAN) The preamble is composed of '0's

Definition at line 293 of file component_usart.h.

US_MAN_TX_PP_Msk

#define US_MAN_TX_PP_Msk   (0x3u << US_MAN_TX_PP_Pos)

(US_MAN) Transmitter Preamble Pattern

Definition at line 291 of file component_usart.h.

Referenced by usart_man_set_tx_pre_pattern().

US_MAN_TX_PP_ONE_ZERO

#define US_MAN_TX_PP_ONE_ZERO   (0x3u << 8)

(US_MAN) The preamble is composed of '10's

Definition at line 295 of file component_usart.h.

US_MAN_TX_PP_Pos

#define US_MAN_TX_PP_Pos   8

Definition at line 290 of file component_usart.h.

Referenced by usart_man_set_tx_pre_pattern().

US_MAN_TX_PP_ZERO_ONE

#define US_MAN_TX_PP_ZERO_ONE   (0x2u << 8)

(US_MAN) The preamble is composed of '01's

Definition at line 294 of file component_usart.h.

US_MR_CHMODE_AUTOMATIC

#define US_MR_CHMODE_AUTOMATIC   (0x1u << 14)

(US_MR) Automatic Echo.

Receiver input is connected to the TXD pin.

Definition at line 142 of file component_usart.h.

US_MR_CHMODE_LOCAL_LOOPBACK

#define US_MR_CHMODE_LOCAL_LOOPBACK   (0x2u << 14)

(US_MR) Local Loopback.

Transmitter output is connected to the Receiver Input.

Definition at line 143 of file component_usart.h.

US_MR_CHMODE_Msk

#define US_MR_CHMODE_Msk   (0x3u << US_MR_CHMODE_Pos)

(US_MR) Channel Mode

Definition at line 140 of file component_usart.h.

US_MR_CHMODE_NORMAL

#define US_MR_CHMODE_NORMAL   (0x0u << 14)

(US_MR) Normal Mode

Definition at line 141 of file component_usart.h.

Referenced by usart_serial_init().

US_MR_CHMODE_Pos

#define US_MR_CHMODE_Pos   14

Definition at line 139 of file component_usart.h.

US_MR_CHMODE_REMOTE_LOOPBACK

#define US_MR_CHMODE_REMOTE_LOOPBACK   (0x3u << 14)

(US_MR) Remote Loopback.

RXD pin is internally connected to the TXD pin.

Definition at line 144 of file component_usart.h.

US_MR_CHRL_5_BIT

#define US_MR_CHRL_5_BIT   (0x0u << 6)

(US_MR) Character length is 5 bits

Definition at line 121 of file component_usart.h.

US_MR_CHRL_6_BIT

#define US_MR_CHRL_6_BIT   (0x1u << 6)

(US_MR) Character length is 6 bits

Definition at line 122 of file component_usart.h.

US_MR_CHRL_7_BIT

#define US_MR_CHRL_7_BIT   (0x2u << 6)

(US_MR) Character length is 7 bits

Definition at line 123 of file component_usart.h.

US_MR_CHRL_8_BIT

#define US_MR_CHRL_8_BIT   (0x3u << 6)

(US_MR) Character length is 8 bits

Definition at line 124 of file component_usart.h.

US_MR_CHRL_Msk

#define US_MR_CHRL_Msk   (0x3u << US_MR_CHRL_Pos)

(US_MR) Character Length

Definition at line 120 of file component_usart.h.

US_MR_CHRL_Pos

#define US_MR_CHRL_Pos   6

Definition at line 119 of file component_usart.h.

US_MR_CLKO

#define US_MR_CLKO   (0x1u << 18)

(US_MR) Clock Output Select

Definition at line 147 of file component_usart.h.

Referenced by usart_init_spi_master(), usart_init_sync_master(), and usart_set_iso7816_clock().

US_MR_CPHA

#define US_MR_CPHA   (0x1u << 8)

(US_MR) SPI Clock Phase

Definition at line 160 of file component_usart.h.

Referenced by usart_init_spi_master(), and usart_init_spi_slave().

US_MR_CPOL

#define US_MR_CPOL   (0x1u << 16)

(US_MR) SPI Clock Polarity

Definition at line 161 of file component_usart.h.

Referenced by usart_init_spi_master(), and usart_init_spi_slave().

US_MR_DSNACK

#define US_MR_DSNACK   (0x1u << 21)

(US_MR) Disable Successive NACK

Definition at line 150 of file component_usart.h.

Referenced by usart_init_iso7816().

US_MR_FILTER

#define US_MR_FILTER   (0x1u << 28)

(US_MR) Infrared Receive Line Filter

Definition at line 156 of file component_usart.h.

US_MR_INACK

#define US_MR_INACK   (0x1u << 20)

(US_MR) Inhibit Non Acknowledge

Definition at line 149 of file component_usart.h.

Referenced by usart_init_iso7816().

US_MR_INVDATA

#define US_MR_INVDATA   (0x1u << 23)

(US_MR) Inverted Data

Definition at line 152 of file component_usart.h.

US_MR_MAN

#define US_MR_MAN   (0x1u << 29)

(US_MR) Manchester Encoder/Decoder Enable

Definition at line 157 of file component_usart.h.

US_MR_MAX_ITERATION

#define US_MR_MAX_ITERATION

(

value

)

Value:

((US_MR_MAX_ITERATION_Msk & ((value) << US_MR_MAX_ITERATION_Pos)))

Definition at line 155 of file component_usart.h.

US_MR_MAX_ITERATION_Msk

#define US_MR_MAX_ITERATION_Msk   (0x7u << US_MR_MAX_ITERATION_Pos)

(US_MR) Maximum Number of Automatic Iteration

Definition at line 154 of file component_usart.h.

US_MR_MAX_ITERATION_Pos

#define US_MR_MAX_ITERATION_Pos   24

Definition at line 153 of file component_usart.h.

Referenced by usart_init_iso7816().

US_MR_MODE9

#define US_MR_MODE9   (0x1u << 17)

(US_MR) 9-bit Character Length

Definition at line 146 of file component_usart.h.

US_MR_MODSYNC

#define US_MR_MODSYNC   (0x1u << 30)

(US_MR) Manchester Synchronization Mode

Definition at line 158 of file component_usart.h.

US_MR_MSBF

#define US_MR_MSBF   (0x1u << 16)

(US_MR) Bit Order

Definition at line 145 of file component_usart.h.

Referenced by usart_init_iso7816().

US_MR_NBSTOP_1_5_BIT

#define US_MR_NBSTOP_1_5_BIT   (0x1u << 12)

(US_MR) 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1)

Definition at line 137 of file component_usart.h.

US_MR_NBSTOP_1_BIT

#define US_MR_NBSTOP_1_BIT   (0x0u << 12)

(US_MR) 1 stop bit

Definition at line 136 of file component_usart.h.

Referenced by usart_init_iso7816().

US_MR_NBSTOP_2_BIT

#define US_MR_NBSTOP_2_BIT   (0x2u << 12)

(US_MR) 2 stop bits

Definition at line 138 of file component_usart.h.

Referenced by usart_init_iso7816().

US_MR_NBSTOP_Msk

#define US_MR_NBSTOP_Msk   (0x3u << US_MR_NBSTOP_Pos)

(US_MR) Number of Stop Bits

Definition at line 135 of file component_usart.h.

US_MR_NBSTOP_Pos

#define US_MR_NBSTOP_Pos   12

Definition at line 134 of file component_usart.h.

US_MR_ONEBIT

#define US_MR_ONEBIT   (0x1u << 31)

(US_MR) Start Frame Delimiter Selector

Definition at line 159 of file component_usart.h.

US_MR_OVER

#define US_MR_OVER   (0x1u << 19)

(US_MR) Oversampling Mode

Definition at line 148 of file component_usart.h.

Referenced by usart_set_async_baudrate(), and usart_set_iso7816_clock().

US_MR_PAR_EVEN

#define US_MR_PAR_EVEN   (0x0u << 9)

(US_MR) Even parity

Definition at line 128 of file component_usart.h.

Referenced by usart_init_iso7816().

US_MR_PAR_MARK

#define US_MR_PAR_MARK   (0x3u << 9)

(US_MR) Parity forced to 1 (Mark)

Definition at line 131 of file component_usart.h.

US_MR_PAR_Msk

#define US_MR_PAR_Msk   (0x7u << US_MR_PAR_Pos)

(US_MR) Parity Type

Definition at line 127 of file component_usart.h.

US_MR_PAR_MULTIDROP

#define US_MR_PAR_MULTIDROP   (0x6u << 9)

(US_MR) Multidrop mode

Definition at line 133 of file component_usart.h.

Referenced by usart_send_address().

US_MR_PAR_NO

#define US_MR_PAR_NO   (0x4u << 9)

(US_MR) No parity

Definition at line 132 of file component_usart.h.

US_MR_PAR_ODD

#define US_MR_PAR_ODD   (0x1u << 9)

(US_MR) Odd parity

Definition at line 129 of file component_usart.h.

Referenced by usart_init_iso7816().

US_MR_PAR_Pos

#define US_MR_PAR_Pos   9

Definition at line 126 of file component_usart.h.

US_MR_PAR_SPACE

#define US_MR_PAR_SPACE   (0x2u << 9)

(US_MR) Parity forced to 0 (Space)

Definition at line 130 of file component_usart.h.

US_MR_SYNC

#define US_MR_SYNC   (0x1u << 8)

(US_MR) Synchronous Mode Select

Definition at line 125 of file component_usart.h.

Referenced by usart_set_iso7816_clock(), usart_set_sync_master_baudrate(), and usart_set_sync_slave_baudrate().

US_MR_USART_MODE_HW_HANDSHAKING

#define US_MR_USART_MODE_HW_HANDSHAKING   (0x2u << 0)

(US_MR) Hardware Handshaking

Definition at line 107 of file component_usart.h.

Referenced by usart_init_hw_handshaking().

US_MR_USART_MODE_IRDA

#define US_MR_USART_MODE_IRDA   (0x8u << 0)

(US_MR) IrDA

Definition at line 111 of file component_usart.h.

Referenced by usart_init_irda().

US_MR_USART_MODE_IS07816_T_0

#define US_MR_USART_MODE_IS07816_T_0   (0x4u << 0)

(US_MR) IS07816 Protocol: T = 0

Definition at line 109 of file component_usart.h.

Referenced by usart_init_iso7816().

US_MR_USART_MODE_IS07816_T_1

#define US_MR_USART_MODE_IS07816_T_1   (0x6u << 0)

(US_MR) IS07816 Protocol: T = 1

Definition at line 110 of file component_usart.h.

Referenced by usart_init_iso7816().

US_MR_USART_MODE_MODEM

#define US_MR_USART_MODE_MODEM   (0x3u << 0)

(US_MR) Modem

Definition at line 108 of file component_usart.h.

Referenced by usart_init_modem().

US_MR_USART_MODE_Msk

#define US_MR_USART_MODE_Msk   (0xfu << US_MR_USART_MODE_Pos)

(US_MR) USART Mode of Operation

Definition at line 104 of file component_usart.h.

Referenced by usart_init_hw_handshaking(), usart_init_irda(), usart_init_modem(), and usart_init_rs485().

US_MR_USART_MODE_NORMAL

#define US_MR_USART_MODE_NORMAL   (0x0u << 0)

(US_MR) Normal mode

Definition at line 105 of file component_usart.h.

Referenced by usart_init_rs232(), usart_init_sync_master(), and usart_init_sync_slave().

US_MR_USART_MODE_Pos

#define US_MR_USART_MODE_Pos   0

Definition at line 103 of file component_usart.h.

US_MR_USART_MODE_RS485

#define US_MR_USART_MODE_RS485   (0x1u << 0)

(US_MR) RS485

Definition at line 106 of file component_usart.h.

Referenced by usart_init_rs485().

US_MR_USART_MODE_SPI_MASTER

#define US_MR_USART_MODE_SPI_MASTER   (0xEu << 0)

(US_MR) SPI Master

Definition at line 112 of file component_usart.h.

Referenced by usart_init_spi_master().

US_MR_USART_MODE_SPI_SLAVE

#define US_MR_USART_MODE_SPI_SLAVE   (0xFu << 0)

(US_MR) SPI Slave

Definition at line 113 of file component_usart.h.

Referenced by usart_init_spi_slave().

US_MR_USCLKS_DIV

#define US_MR_USCLKS_DIV   (0x1u << 4)

(US_MR) Internal Clock Divided MCK/DIV (DIV=8) is selected

Definition at line 117 of file component_usart.h.

US_MR_USCLKS_MCK

#define US_MR_USCLKS_MCK   (0x0u << 4)

(US_MR) Master Clock MCK is selected

Definition at line 116 of file component_usart.h.

Referenced by usart_set_iso7816_clock(), and usart_set_sync_master_baudrate().

US_MR_USCLKS_Msk

#define US_MR_USCLKS_Msk   (0x3u << US_MR_USCLKS_Pos)

(US_MR) Clock Selection

Definition at line 115 of file component_usart.h.

Referenced by usart_set_iso7816_clock(), usart_set_spi_slave_baudrate(), usart_set_sync_master_baudrate(), and usart_set_sync_slave_baudrate().

US_MR_USCLKS_Pos

#define US_MR_USCLKS_Pos   4

Definition at line 114 of file component_usart.h.

US_MR_USCLKS_SCK

#define US_MR_USCLKS_SCK   (0x3u << 4)

(US_MR) Serial Clock SLK is selected

Definition at line 118 of file component_usart.h.

Referenced by usart_set_spi_slave_baudrate(), and usart_set_sync_slave_baudrate().

US_MR_VAR_SYNC

#define US_MR_VAR_SYNC   (0x1u << 22)

(US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter

Definition at line 151 of file component_usart.h.

US_MR_WRDBT

#define US_MR_WRDBT   (0x1u << 20)

(US_MR) Wait Read Data Before Transfer

Definition at line 162 of file component_usart.h.

US_NER_NB_ERRORS_Msk

#define US_NER_NB_ERRORS_Msk   (0xffu << US_NER_NB_ERRORS_Pos)

(US_NER) Number of Errors

Definition at line 281 of file component_usart.h.

Referenced by usart_get_error_number().

US_NER_NB_ERRORS_Pos

#define US_NER_NB_ERRORS_Pos   0

Definition at line 280 of file component_usart.h.

US_PTCR_RXTDIS

#define US_PTCR_RXTDIS   (0x1u << 1)

(US_PTCR) Receiver Transfer Disable

Definition at line 357 of file component_usart.h.

US_PTCR_RXTEN

#define US_PTCR_RXTEN   (0x1u << 0)

(US_PTCR) Receiver Transfer Enable

Definition at line 356 of file component_usart.h.

US_PTCR_TXTDIS

#define US_PTCR_TXTDIS   (0x1u << 9)

(US_PTCR) Transmitter Transfer Disable

Definition at line 359 of file component_usart.h.

US_PTCR_TXTEN

#define US_PTCR_TXTEN   (0x1u << 8)

(US_PTCR) Transmitter Transfer Enable

Definition at line 358 of file component_usart.h.

US_PTSR_RXTEN

#define US_PTSR_RXTEN   (0x1u << 0)

(US_PTSR) Receiver Transfer Enable

Definition at line 361 of file component_usart.h.

US_PTSR_TXTEN

#define US_PTSR_TXTEN   (0x1u << 8)

(US_PTSR) Transmitter Transfer Enable

Definition at line 362 of file component_usart.h.

US_RCR_RXCTR

#define US_RCR_RXCTR

(

value

)

Value:

((US_RCR_RXCTR_Msk & ((value) << US_RCR_RXCTR_Pos)))

Definition at line 330 of file component_usart.h.

US_RCR_RXCTR_Msk

#define US_RCR_RXCTR_Msk   (0xffffu << US_RCR_RXCTR_Pos)

(US_RCR) Receive Counter Register

Definition at line 329 of file component_usart.h.

US_RCR_RXCTR_Pos

#define US_RCR_RXCTR_Pos   0

Definition at line 328 of file component_usart.h.

US_RHR_RXCHR_Msk

#define US_RHR_RXCHR_Msk   (0x1ffu << US_RHR_RXCHR_Pos)

(US_RHR) Received Character

Definition at line 253 of file component_usart.h.

Referenced by usart_getchar(), and usart_read().

US_RHR_RXCHR_Pos

#define US_RHR_RXCHR_Pos   0

Definition at line 252 of file component_usart.h.

US_RHR_RXSYNH

#define US_RHR_RXSYNH   (0x1u << 15)

(US_RHR) Received Sync

Definition at line 254 of file component_usart.h.

US_RNCR_RXNCTR

#define US_RNCR_RXNCTR

(

value

)

Value:

((US_RNCR_RXNCTR_Msk & ((value) << US_RNCR_RXNCTR_Pos)))

Definition at line 346 of file component_usart.h.

US_RNCR_RXNCTR_Msk

#define US_RNCR_RXNCTR_Msk   (0xffffu << US_RNCR_RXNCTR_Pos)

(US_RNCR) Receive Next Counter

Definition at line 345 of file component_usart.h.

US_RNCR_RXNCTR_Pos

#define US_RNCR_RXNCTR_Pos   0

Definition at line 344 of file component_usart.h.

US_RNPR_RXNPTR

#define US_RNPR_RXNPTR

(

value

)

Value:

((US_RNPR_RXNPTR_Msk & ((value) << US_RNPR_RXNPTR_Pos)))

Definition at line 342 of file component_usart.h.

US_RNPR_RXNPTR_Msk

#define US_RNPR_RXNPTR_Msk   (0xffffffffu << US_RNPR_RXNPTR_Pos)

(US_RNPR) Receive Next Pointer

Definition at line 341 of file component_usart.h.

US_RNPR_RXNPTR_Pos

#define US_RNPR_RXNPTR_Pos   0

Definition at line 340 of file component_usart.h.

US_RPR_RXPTR

#define US_RPR_RXPTR

(

value

)

Value:

((US_RPR_RXPTR_Msk & ((value) << US_RPR_RXPTR_Pos)))

Definition at line 326 of file component_usart.h.

US_RPR_RXPTR_Msk

#define US_RPR_RXPTR_Msk   (0xffffffffu << US_RPR_RXPTR_Pos)

(US_RPR) Receive Pointer Register

Definition at line 325 of file component_usart.h.

US_RPR_RXPTR_Pos

#define US_RPR_RXPTR_Pos   0

Definition at line 324 of file component_usart.h.

US_RTOR_TO

#define US_RTOR_TO

(

value

)

Value:

((US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos)))

Definition at line 270 of file component_usart.h.

US_RTOR_TO_Msk

#define US_RTOR_TO_Msk   (0xffffu << US_RTOR_TO_Pos)

(US_RTOR) Time-out Value

Definition at line 269 of file component_usart.h.

US_RTOR_TO_Pos

#define US_RTOR_TO_Pos   0

Definition at line 268 of file component_usart.h.

US_TCR_TXCTR

#define US_TCR_TXCTR

(

value

)

Value:

((US_TCR_TXCTR_Msk & ((value) << US_TCR_TXCTR_Pos)))

Definition at line 338 of file component_usart.h.

US_TCR_TXCTR_Msk

#define US_TCR_TXCTR_Msk   (0xffffu << US_TCR_TXCTR_Pos)

(US_TCR) Transmit Counter Register

Definition at line 337 of file component_usart.h.

US_TCR_TXCTR_Pos

#define US_TCR_TXCTR_Pos   0

Definition at line 336 of file component_usart.h.

US_THR_TXCHR

#define US_THR_TXCHR

(

value

)

Value:

((US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos)))

Definition at line 258 of file component_usart.h.

Referenced by usart_putchar(), and usart_write().

US_THR_TXCHR_Msk

#define US_THR_TXCHR_Msk   (0x1ffu << US_THR_TXCHR_Pos)

(US_THR) Character to be Transmitted

Definition at line 257 of file component_usart.h.

US_THR_TXCHR_Pos

#define US_THR_TXCHR_Pos   0

Definition at line 256 of file component_usart.h.

US_THR_TXSYNH

#define US_THR_TXSYNH   (0x1u << 15)

(US_THR) Sync Field to be Transmitted

Definition at line 259 of file component_usart.h.

US_TNCR_TXNCTR

#define US_TNCR_TXNCTR

(

value

)

Value:

((US_TNCR_TXNCTR_Msk & ((value) << US_TNCR_TXNCTR_Pos)))

Definition at line 354 of file component_usart.h.

US_TNCR_TXNCTR_Msk

#define US_TNCR_TXNCTR_Msk   (0xffffu << US_TNCR_TXNCTR_Pos)

(US_TNCR) Transmit Counter Next

Definition at line 353 of file component_usart.h.

US_TNCR_TXNCTR_Pos

#define US_TNCR_TXNCTR_Pos   0

Definition at line 352 of file component_usart.h.

US_TNPR_TXNPTR

#define US_TNPR_TXNPTR

(

value

)

Value:

((US_TNPR_TXNPTR_Msk & ((value) << US_TNPR_TXNPTR_Pos)))

Definition at line 350 of file component_usart.h.

US_TNPR_TXNPTR_Msk

#define US_TNPR_TXNPTR_Msk   (0xffffffffu << US_TNPR_TXNPTR_Pos)

(US_TNPR) Transmit Next Pointer

Definition at line 349 of file component_usart.h.

US_TNPR_TXNPTR_Pos

#define US_TNPR_TXNPTR_Pos   0

Definition at line 348 of file component_usart.h.

US_TPR_TXPTR

#define US_TPR_TXPTR

(

value

)

Value:

((US_TPR_TXPTR_Msk & ((value) << US_TPR_TXPTR_Pos)))

Definition at line 334 of file component_usart.h.

US_TPR_TXPTR_Msk

#define US_TPR_TXPTR_Msk   (0xffffffffu << US_TPR_TXPTR_Pos)

(US_TPR) Transmit Counter Register

Definition at line 333 of file component_usart.h.

US_TPR_TXPTR_Pos

#define US_TPR_TXPTR_Pos   0

Definition at line 332 of file component_usart.h.

US_TTGR_TG

#define US_TTGR_TG

(

value

)

Value:

((US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos)))

Definition at line 274 of file component_usart.h.

US_TTGR_TG_Msk

#define US_TTGR_TG_Msk   (0xffu << US_TTGR_TG_Pos)

(US_TTGR) Timeguard Value

Definition at line 273 of file component_usart.h.

US_TTGR_TG_Pos

#define US_TTGR_TG_Pos   0

Definition at line 272 of file component_usart.h.

US_VERSION_MFN_Msk

#define US_VERSION_MFN_Msk   (0x7u << US_VERSION_MFN_Pos)

(US_VERSION) Metal Fix Number

Definition at line 322 of file component_usart.h.

US_VERSION_MFN_Pos

#define US_VERSION_MFN_Pos   16

Definition at line 321 of file component_usart.h.

US_VERSION_VERSION_Msk

#define US_VERSION_VERSION_Msk   (0xfffu << US_VERSION_VERSION_Pos)

(US_VERSION) Hardware Module Version

Definition at line 320 of file component_usart.h.

US_VERSION_VERSION_Pos

#define US_VERSION_VERSION_Pos   0

Definition at line 319 of file component_usart.h.

US_WPMR_WPEN

#define US_WPMR_WPEN   (0x1u << 0)

(US_WPMR) Write Protect Enable

Definition at line 310 of file component_usart.h.

Referenced by usart_enable_writeprotect().

US_WPMR_WPKEY_Msk

#define US_WPMR_WPKEY_Msk   (0xffffffu << US_WPMR_WPKEY_Pos)

(US_WPMR) Write Protect KEY

Definition at line 312 of file component_usart.h.

US_WPMR_WPKEY_PASSWD

#define US_WPMR_WPKEY_PASSWD   (0x555341u << 8)

(US_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.

Always reads as 0.

Definition at line 313 of file component_usart.h.

US_WPMR_WPKEY_Pos

#define US_WPMR_WPKEY_Pos   8

Definition at line 311 of file component_usart.h.

US_WPSR_WPVS

#define US_WPSR_WPVS   (0x1u << 0)

(US_WPSR) Write Protect Violation Status

Definition at line 315 of file component_usart.h.

Referenced by usart_get_writeprotect_status().

US_WPSR_WPVSRC_Msk

#define US_WPSR_WPVSRC_Msk   (0xffffu << US_WPSR_WPVSRC_Pos)

(US_WPSR) Write Protect Violation Source

Definition at line 317 of file component_usart.h.

Referenced by usart_get_writeprotect_status().

US_WPSR_WPVSRC_Pos

#define US_WPSR_WPVSRC_Pos   8

Definition at line 316 of file component_usart.h.

Referenced by usart_get_writeprotect_status().