Macros
#define	REG_TC1_BCR ((__O uint32_t)0x400140C0U)
	(TC1) Block Control Register
#define	REG_TC1_BMR ((__IO uint32_t)0x400140C4U)
	(TC1) Block Mode Register
#define	REG_TC1_CCR0 ((__O uint32_t)0x40014000U)
	(TC1) Channel Control Register (channel = 0)
#define	REG_TC1_CCR1 ((__O uint32_t)0x40014040U)
	(TC1) Channel Control Register (channel = 1)
#define	REG_TC1_CCR2 ((__O uint32_t)0x40014080U)
	(TC1) Channel Control Register (channel = 2)
#define	REG_TC1_CMR0 ((__IO uint32_t)0x40014004U)
	(TC1) Channel Mode Register (channel = 0)
#define	REG_TC1_CMR1 ((__IO uint32_t)0x40014044U)
	(TC1) Channel Mode Register (channel = 1)
#define	REG_TC1_CMR2 ((__IO uint32_t)0x40014084U)
	(TC1) Channel Mode Register (channel = 2)
#define	REG_TC1_CV0 ((__I uint32_t)0x40014010U)
	(TC1) Counter Value (channel = 0)
#define	REG_TC1_CV1 ((__I uint32_t)0x40014050U)
	(TC1) Counter Value (channel = 1)
#define	REG_TC1_CV2 ((__I uint32_t)0x40014090U)
	(TC1) Counter Value (channel = 2)
#define	REG_TC1_FMR ((__IO uint32_t)0x400140D8U)
	(TC1) Fault Mode Register
#define	REG_TC1_IDR0 ((__O uint32_t)0x40014028U)
	(TC1) Interrupt Disable Register (channel = 0)
#define	REG_TC1_IDR1 ((__O uint32_t)0x40014068U)
	(TC1) Interrupt Disable Register (channel = 1)
#define	REG_TC1_IDR2 ((__O uint32_t)0x400140A8U)
	(TC1) Interrupt Disable Register (channel = 2)
#define	REG_TC1_IER0 ((__O uint32_t)0x40014024U)
	(TC1) Interrupt Enable Register (channel = 0)
#define	REG_TC1_IER1 ((__O uint32_t)0x40014064U)
	(TC1) Interrupt Enable Register (channel = 1)
#define	REG_TC1_IER2 ((__O uint32_t)0x400140A4U)
	(TC1) Interrupt Enable Register (channel = 2)
#define	REG_TC1_IMR0 ((__I uint32_t)0x4001402CU)
	(TC1) Interrupt Mask Register (channel = 0)
#define	REG_TC1_IMR1 ((__I uint32_t)0x4001406CU)
	(TC1) Interrupt Mask Register (channel = 1)
#define	REG_TC1_IMR2 ((__I uint32_t)0x400140ACU)
	(TC1) Interrupt Mask Register (channel = 2)
#define	REG_TC1_QIDR ((__O uint32_t)0x400140CCU)
	(TC1) QDEC Interrupt Disable Register
#define	REG_TC1_QIER ((__O uint32_t)0x400140C8U)
	(TC1) QDEC Interrupt Enable Register
#define	REG_TC1_QIMR ((__I uint32_t)0x400140D0U)
	(TC1) QDEC Interrupt Mask Register
#define	REG_TC1_QISR ((__I uint32_t)0x400140D4U)
	(TC1) QDEC Interrupt Status Register
#define	REG_TC1_RA0 ((__IO uint32_t)0x40014014U)
	(TC1) Register A (channel = 0)
#define	REG_TC1_RA1 ((__IO uint32_t)0x40014054U)
	(TC1) Register A (channel = 1)
#define	REG_TC1_RA2 ((__IO uint32_t)0x40014094U)
	(TC1) Register A (channel = 2)
#define	REG_TC1_RB0 ((__IO uint32_t)0x40014018U)
	(TC1) Register B (channel = 0)
#define	REG_TC1_RB1 ((__IO uint32_t)0x40014058U)
	(TC1) Register B (channel = 1)
#define	REG_TC1_RB2 ((__IO uint32_t)0x40014098U)
	(TC1) Register B (channel = 2)
#define	REG_TC1_RC0 ((__IO uint32_t)0x4001401CU)
	(TC1) Register C (channel = 0)
#define	REG_TC1_RC1 ((__IO uint32_t)0x4001405CU)
	(TC1) Register C (channel = 1)
#define	REG_TC1_RC2 ((__IO uint32_t)0x4001409CU)
	(TC1) Register C (channel = 2)
#define	REG_TC1_SMMR0 ((__IO uint32_t)0x40014008U)
	(TC1) Stepper Motor Mode Register (channel = 0)
#define	REG_TC1_SMMR1 ((__IO uint32_t)0x40014048U)
	(TC1) Stepper Motor Mode Register (channel = 1)
#define	REG_TC1_SMMR2 ((__IO uint32_t)0x40014088U)
	(TC1) Stepper Motor Mode Register (channel = 2)
#define	REG_TC1_SR0 ((__I uint32_t)0x40014020U)
	(TC1) Status Register (channel = 0)
#define	REG_TC1_SR1 ((__I uint32_t)0x40014060U)
	(TC1) Status Register (channel = 1)
#define	REG_TC1_SR2 ((__I uint32_t)0x400140A0U)
	(TC1) Status Register (channel = 2)
#define	REG_TC1_WPMR ((__IO uint32_t)0x400140E4U)
	(TC1) Write Protect Mode Register

Detailed Description

and its subsidiaries.

\cond ASF_LICENSE

Definition in file instance_tc1.h.

Macro Definition Documentation

◆ REG_TC1_BCR

#define REG_TC1_BCR (*(__O uint32_t*)0x400140C0U)

(TC1) Block Control Register

Definition at line 115 of file instance_tc1.h.

◆ REG_TC1_BMR

#define REG_TC1_BMR (*(__IO uint32_t*)0x400140C4U)

(TC1) Block Mode Register

Definition at line 116 of file instance_tc1.h.

◆ REG_TC1_CCR0

#define REG_TC1_CCR0 (*(__O uint32_t*)0x40014000U)

(TC1) Channel Control Register (channel = 0)

Definition at line 82 of file instance_tc1.h.

◆ REG_TC1_CCR1

#define REG_TC1_CCR1 (*(__O uint32_t*)0x40014040U)

(TC1) Channel Control Register (channel = 1)

Definition at line 93 of file instance_tc1.h.

◆ REG_TC1_CCR2

#define REG_TC1_CCR2 (*(__O uint32_t*)0x40014080U)

(TC1) Channel Control Register (channel = 2)

Definition at line 104 of file instance_tc1.h.

◆ REG_TC1_CMR0

#define REG_TC1_CMR0 (*(__IO uint32_t*)0x40014004U)

(TC1) Channel Mode Register (channel = 0)

Definition at line 83 of file instance_tc1.h.

◆ REG_TC1_CMR1

#define REG_TC1_CMR1 (*(__IO uint32_t*)0x40014044U)

(TC1) Channel Mode Register (channel = 1)

Definition at line 94 of file instance_tc1.h.

◆ REG_TC1_CMR2

#define REG_TC1_CMR2 (*(__IO uint32_t*)0x40014084U)

(TC1) Channel Mode Register (channel = 2)

Definition at line 105 of file instance_tc1.h.

◆ REG_TC1_CV0

#define REG_TC1_CV0 (*(__I uint32_t*)0x40014010U)

(TC1) Counter Value (channel = 0)

Definition at line 85 of file instance_tc1.h.

◆ REG_TC1_CV1

#define REG_TC1_CV1 (*(__I uint32_t*)0x40014050U)

(TC1) Counter Value (channel = 1)

Definition at line 96 of file instance_tc1.h.

◆ REG_TC1_CV2

#define REG_TC1_CV2 (*(__I uint32_t*)0x40014090U)

(TC1) Counter Value (channel = 2)

Definition at line 107 of file instance_tc1.h.

◆ REG_TC1_FMR

#define REG_TC1_FMR (*(__IO uint32_t*)0x400140D8U)

(TC1) Fault Mode Register

Definition at line 121 of file instance_tc1.h.

◆ REG_TC1_IDR0

#define REG_TC1_IDR0 (*(__O uint32_t*)0x40014028U)

(TC1) Interrupt Disable Register (channel = 0)

Definition at line 91 of file instance_tc1.h.

◆ REG_TC1_IDR1

#define REG_TC1_IDR1 (*(__O uint32_t*)0x40014068U)

(TC1) Interrupt Disable Register (channel = 1)

Definition at line 102 of file instance_tc1.h.

◆ REG_TC1_IDR2

#define REG_TC1_IDR2 (*(__O uint32_t*)0x400140A8U)

(TC1) Interrupt Disable Register (channel = 2)

Definition at line 113 of file instance_tc1.h.

◆ REG_TC1_IER0

#define REG_TC1_IER0 (*(__O uint32_t*)0x40014024U)

(TC1) Interrupt Enable Register (channel = 0)

Definition at line 90 of file instance_tc1.h.

◆ REG_TC1_IER1

#define REG_TC1_IER1 (*(__O uint32_t*)0x40014064U)

(TC1) Interrupt Enable Register (channel = 1)

Definition at line 101 of file instance_tc1.h.

◆ REG_TC1_IER2

#define REG_TC1_IER2 (*(__O uint32_t*)0x400140A4U)

(TC1) Interrupt Enable Register (channel = 2)

Definition at line 112 of file instance_tc1.h.

◆ REG_TC1_IMR0

#define REG_TC1_IMR0 (*(__I uint32_t*)0x4001402CU)

(TC1) Interrupt Mask Register (channel = 0)

Definition at line 92 of file instance_tc1.h.

◆ REG_TC1_IMR1

#define REG_TC1_IMR1 (*(__I uint32_t*)0x4001406CU)

(TC1) Interrupt Mask Register (channel = 1)

Definition at line 103 of file instance_tc1.h.

◆ REG_TC1_IMR2

#define REG_TC1_IMR2 (*(__I uint32_t*)0x400140ACU)

(TC1) Interrupt Mask Register (channel = 2)

Definition at line 114 of file instance_tc1.h.

◆ REG_TC1_QIDR

#define REG_TC1_QIDR (*(__O uint32_t*)0x400140CCU)

(TC1) QDEC Interrupt Disable Register

Definition at line 118 of file instance_tc1.h.

◆ REG_TC1_QIER

#define REG_TC1_QIER (*(__O uint32_t*)0x400140C8U)

(TC1) QDEC Interrupt Enable Register

Definition at line 117 of file instance_tc1.h.

◆ REG_TC1_QIMR

#define REG_TC1_QIMR (*(__I uint32_t*)0x400140D0U)

(TC1) QDEC Interrupt Mask Register

Definition at line 119 of file instance_tc1.h.

◆ REG_TC1_QISR

#define REG_TC1_QISR (*(__I uint32_t*)0x400140D4U)

(TC1) QDEC Interrupt Status Register

Definition at line 120 of file instance_tc1.h.

◆ REG_TC1_RA0

#define REG_TC1_RA0 (*(__IO uint32_t*)0x40014014U)

(TC1) Register A (channel = 0)

Definition at line 86 of file instance_tc1.h.

◆ REG_TC1_RA1

#define REG_TC1_RA1 (*(__IO uint32_t*)0x40014054U)

(TC1) Register A (channel = 1)

Definition at line 97 of file instance_tc1.h.

◆ REG_TC1_RA2

#define REG_TC1_RA2 (*(__IO uint32_t*)0x40014094U)

(TC1) Register A (channel = 2)

Definition at line 108 of file instance_tc1.h.

◆ REG_TC1_RB0

#define REG_TC1_RB0 (*(__IO uint32_t*)0x40014018U)

(TC1) Register B (channel = 0)

Definition at line 87 of file instance_tc1.h.

◆ REG_TC1_RB1

#define REG_TC1_RB1 (*(__IO uint32_t*)0x40014058U)

(TC1) Register B (channel = 1)

Definition at line 98 of file instance_tc1.h.

◆ REG_TC1_RB2

#define REG_TC1_RB2 (*(__IO uint32_t*)0x40014098U)

(TC1) Register B (channel = 2)

Definition at line 109 of file instance_tc1.h.

◆ REG_TC1_RC0

#define REG_TC1_RC0 (*(__IO uint32_t*)0x4001401CU)

(TC1) Register C (channel = 0)

Definition at line 88 of file instance_tc1.h.

◆ REG_TC1_RC1

#define REG_TC1_RC1 (*(__IO uint32_t*)0x4001405CU)

(TC1) Register C (channel = 1)

Definition at line 99 of file instance_tc1.h.

◆ REG_TC1_RC2

#define REG_TC1_RC2 (*(__IO uint32_t*)0x4001409CU)

(TC1) Register C (channel = 2)

Definition at line 110 of file instance_tc1.h.

◆ REG_TC1_SMMR0

#define REG_TC1_SMMR0 (*(__IO uint32_t*)0x40014008U)

(TC1) Stepper Motor Mode Register (channel = 0)

Definition at line 84 of file instance_tc1.h.

◆ REG_TC1_SMMR1

#define REG_TC1_SMMR1 (*(__IO uint32_t*)0x40014048U)

(TC1) Stepper Motor Mode Register (channel = 1)

Definition at line 95 of file instance_tc1.h.

◆ REG_TC1_SMMR2

#define REG_TC1_SMMR2 (*(__IO uint32_t*)0x40014088U)

(TC1) Stepper Motor Mode Register (channel = 2)

Definition at line 106 of file instance_tc1.h.

◆ REG_TC1_SR0

#define REG_TC1_SR0 (*(__I uint32_t*)0x40014020U)

(TC1) Status Register (channel = 0)

Definition at line 89 of file instance_tc1.h.

◆ REG_TC1_SR1

#define REG_TC1_SR1 (*(__I uint32_t*)0x40014060U)

(TC1) Status Register (channel = 1)

Definition at line 100 of file instance_tc1.h.

◆ REG_TC1_SR2

#define REG_TC1_SR2 (*(__I uint32_t*)0x400140A0U)

(TC1) Status Register (channel = 2)

Definition at line 111 of file instance_tc1.h.

◆ REG_TC1_WPMR

#define REG_TC1_WPMR (*(__IO uint32_t*)0x400140E4U)

(TC1) Write Protect Mode Register

Definition at line 122 of file instance_tc1.h.

Macros