instance_usart1.h File Reference

Copyright (c) 2012-2018 Microchip Technology Inc. More...

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Macros
#define	REG_USART1_BRGR   (*(__IO uint32_t*)0x40028020U)
	(USART1) Baud Rate Generator Register
#define	REG_USART1_CR   (*(__O uint32_t*)0x40028000U)
	(USART1) Control Register
#define	REG_USART1_CSR   (*(__I uint32_t*)0x40028014U)
	(USART1) Channel Status Register
#define	REG_USART1_FIDI   (*(__IO uint32_t*)0x40028040U)
	(USART1) FI DI Ratio Register
#define	REG_USART1_IDR   (*(__O uint32_t*)0x4002800CU)
	(USART1) Interrupt Disable Register
#define	REG_USART1_IER   (*(__O uint32_t*)0x40028008U)
	(USART1) Interrupt Enable Register
#define	REG_USART1_IF   (*(__IO uint32_t*)0x4002804CU)
	(USART1) IrDA Filter Register
#define	REG_USART1_IMR   (*(__I uint32_t*)0x40028010U)
	(USART1) Interrupt Mask Register
#define	REG_USART1_MAN   (*(__IO uint32_t*)0x40028050U)
	(USART1) Manchester Encoder Decoder Register
#define	REG_USART1_MR   (*(__IO uint32_t*)0x40028004U)
	(USART1) Mode Register
#define	REG_USART1_NER   (*(__I uint32_t*)0x40028044U)
	(USART1) Number of Errors Register
#define	REG_USART1_PTCR   (*(__O uint32_t*)0x40028120U)
	(USART1) Transfer Control Register
#define	REG_USART1_PTSR   (*(__I uint32_t*)0x40028124U)
	(USART1) Transfer Status Register
#define	REG_USART1_RCR   (*(__IO uint32_t*)0x40028104U)
	(USART1) Receive Counter Register
#define	REG_USART1_RHR   (*(__I uint32_t*)0x40028018U)
	(USART1) Receiver Holding Register
#define	REG_USART1_RNCR   (*(__IO uint32_t*)0x40028114U)
	(USART1) Receive Next Counter Register
#define	REG_USART1_RNPR   (*(__IO uint32_t*)0x40028110U)
	(USART1) Receive Next Pointer Register
#define	REG_USART1_RPR   (*(__IO uint32_t*)0x40028100U)
	(USART1) Receive Pointer Register
#define	REG_USART1_RTOR   (*(__IO uint32_t*)0x40028024U)
	(USART1) Receiver Time-out Register
#define	REG_USART1_TCR   (*(__IO uint32_t*)0x4002810CU)
	(USART1) Transmit Counter Register
#define	REG_USART1_THR   (*(__O uint32_t*)0x4002801CU)
	(USART1) Transmitter Holding Register
#define	REG_USART1_TNCR   (*(__IO uint32_t*)0x4002811CU)
	(USART1) Transmit Next Counter Register
#define	REG_USART1_TNPR   (*(__IO uint32_t*)0x40028118U)
	(USART1) Transmit Next Pointer Register
#define	REG_USART1_TPR   (*(__IO uint32_t*)0x40028108U)
	(USART1) Transmit Pointer Register
#define	REG_USART1_TTGR   (*(__IO uint32_t*)0x40028028U)
	(USART1) Transmitter Timeguard Register
#define	REG_USART1_VERSION   (*(__I uint32_t*)0x400280FCU)
	(USART1) Version Register
#define	REG_USART1_WPMR   (*(__IO uint32_t*)0x400280E4U)
	(USART1) Write Protect Mode Register
#define	REG_USART1_WPSR   (*(__I uint32_t*)0x400280E8U)
	(USART1) Write Protect Status Register

Detailed Description

Copyright (c) 2012-2018 Microchip Technology Inc.

and its subsidiaries.

\cond ASF_LICENSE

Definition in file instance_usart1.h.

Macro Definition Documentation

REG_USART1_BRGR

#define REG_USART1_BRGR   (*(__IO uint32_t*)0x40028020U)

(USART1) Baud Rate Generator Register

Definition at line 77 of file instance_usart1.h.

REG_USART1_CR

#define REG_USART1_CR   (*(__O uint32_t*)0x40028000U)

(USART1) Control Register

Definition at line 69 of file instance_usart1.h.

REG_USART1_CSR

#define REG_USART1_CSR   (*(__I uint32_t*)0x40028014U)

(USART1) Channel Status Register

Definition at line 74 of file instance_usart1.h.

REG_USART1_FIDI

#define REG_USART1_FIDI   (*(__IO uint32_t*)0x40028040U)

(USART1) FI DI Ratio Register

Definition at line 80 of file instance_usart1.h.

REG_USART1_IDR

#define REG_USART1_IDR   (*(__O uint32_t*)0x4002800CU)

(USART1) Interrupt Disable Register

Definition at line 72 of file instance_usart1.h.

REG_USART1_IER

#define REG_USART1_IER   (*(__O uint32_t*)0x40028008U)

(USART1) Interrupt Enable Register

Definition at line 71 of file instance_usart1.h.

REG_USART1_IF

#define REG_USART1_IF   (*(__IO uint32_t*)0x4002804CU)

(USART1) IrDA Filter Register

Definition at line 82 of file instance_usart1.h.

REG_USART1_IMR

#define REG_USART1_IMR   (*(__I uint32_t*)0x40028010U)

(USART1) Interrupt Mask Register

Definition at line 73 of file instance_usart1.h.

REG_USART1_MAN

#define REG_USART1_MAN   (*(__IO uint32_t*)0x40028050U)

(USART1) Manchester Encoder Decoder Register

Definition at line 83 of file instance_usart1.h.

REG_USART1_MR

#define REG_USART1_MR   (*(__IO uint32_t*)0x40028004U)

(USART1) Mode Register

Definition at line 70 of file instance_usart1.h.

REG_USART1_NER

#define REG_USART1_NER   (*(__I uint32_t*)0x40028044U)

(USART1) Number of Errors Register

Definition at line 81 of file instance_usart1.h.

REG_USART1_PTCR

#define REG_USART1_PTCR   (*(__O uint32_t*)0x40028120U)

(USART1) Transfer Control Register

Definition at line 95 of file instance_usart1.h.

REG_USART1_PTSR

#define REG_USART1_PTSR   (*(__I uint32_t*)0x40028124U)

(USART1) Transfer Status Register

Definition at line 96 of file instance_usart1.h.

REG_USART1_RCR

#define REG_USART1_RCR   (*(__IO uint32_t*)0x40028104U)

(USART1) Receive Counter Register

Definition at line 88 of file instance_usart1.h.

REG_USART1_RHR

#define REG_USART1_RHR   (*(__I uint32_t*)0x40028018U)

(USART1) Receiver Holding Register

Definition at line 75 of file instance_usart1.h.

REG_USART1_RNCR

#define REG_USART1_RNCR   (*(__IO uint32_t*)0x40028114U)

(USART1) Receive Next Counter Register

Definition at line 92 of file instance_usart1.h.

REG_USART1_RNPR

#define REG_USART1_RNPR   (*(__IO uint32_t*)0x40028110U)

(USART1) Receive Next Pointer Register

Definition at line 91 of file instance_usart1.h.

REG_USART1_RPR

#define REG_USART1_RPR   (*(__IO uint32_t*)0x40028100U)

(USART1) Receive Pointer Register

Definition at line 87 of file instance_usart1.h.

REG_USART1_RTOR

#define REG_USART1_RTOR   (*(__IO uint32_t*)0x40028024U)

(USART1) Receiver Time-out Register

Definition at line 78 of file instance_usart1.h.

REG_USART1_TCR

#define REG_USART1_TCR   (*(__IO uint32_t*)0x4002810CU)

(USART1) Transmit Counter Register

Definition at line 90 of file instance_usart1.h.

REG_USART1_THR

#define REG_USART1_THR   (*(__O uint32_t*)0x4002801CU)

(USART1) Transmitter Holding Register

Definition at line 76 of file instance_usart1.h.

REG_USART1_TNCR

#define REG_USART1_TNCR   (*(__IO uint32_t*)0x4002811CU)

(USART1) Transmit Next Counter Register

Definition at line 94 of file instance_usart1.h.

REG_USART1_TNPR

#define REG_USART1_TNPR   (*(__IO uint32_t*)0x40028118U)

(USART1) Transmit Next Pointer Register

Definition at line 93 of file instance_usart1.h.

REG_USART1_TPR

#define REG_USART1_TPR   (*(__IO uint32_t*)0x40028108U)

(USART1) Transmit Pointer Register

Definition at line 89 of file instance_usart1.h.

REG_USART1_TTGR

#define REG_USART1_TTGR   (*(__IO uint32_t*)0x40028028U)

(USART1) Transmitter Timeguard Register

Definition at line 79 of file instance_usart1.h.

REG_USART1_VERSION

#define REG_USART1_VERSION   (*(__I uint32_t*)0x400280FCU)

(USART1) Version Register

Definition at line 86 of file instance_usart1.h.

REG_USART1_WPMR

#define REG_USART1_WPMR   (*(__IO uint32_t*)0x400280E4U)

(USART1) Write Protect Mode Register

Definition at line 84 of file instance_usart1.h.

REG_USART1_WPSR

#define REG_USART1_WPSR   (*(__I uint32_t*)0x400280E8U)

(USART1) Write Protect Status Register

Definition at line 85 of file instance_usart1.h.