Spi Struct Reference

Spi hardware registers. More...

#include <component_spi.h>

Data Fields
__I uint32_t	Reserved1 [4]
__I uint32_t	Reserved2 [41]
__I uint32_t	Reserved3 [5]
__O uint32_t	SPI_CR
	(Spi Offset: 0x00) Control Register
__IO uint32_t	SPI_CSR [4]
	(Spi Offset: 0x30) Chip Select Register
__O uint32_t	SPI_IDR
	(Spi Offset: 0x18) Interrupt Disable Register
__O uint32_t	SPI_IER
	(Spi Offset: 0x14) Interrupt Enable Register
__I uint32_t	SPI_IMR
	(Spi Offset: 0x1C) Interrupt Mask Register
__IO uint32_t	SPI_MR
	(Spi Offset: 0x04) Mode Register
__O uint32_t	SPI_PTCR
	(Spi Offset: 0x120) Transfer Control Register
__I uint32_t	SPI_PTSR
	(Spi Offset: 0x124) Transfer Status Register
__IO uint32_t	SPI_RCR
	(Spi Offset: 0x104) Receive Counter Register
__I uint32_t	SPI_RDR
	(Spi Offset: 0x08) Receive Data Register
__IO uint32_t	SPI_RNCR
	(Spi Offset: 0x114) Receive Next Counter Register
__IO uint32_t	SPI_RNPR
	(Spi Offset: 0x110) Receive Next Pointer Register
__IO uint32_t	SPI_RPR
	(Spi Offset: 0x100) Receive Pointer Register
__I uint32_t	SPI_SR
	(Spi Offset: 0x10) Status Register
__IO uint32_t	SPI_TCR
	(Spi Offset: 0x10C) Transmit Counter Register
__O uint32_t	SPI_TDR
	(Spi Offset: 0x0C) Transmit Data Register
__IO uint32_t	SPI_TNCR
	(Spi Offset: 0x11C) Transmit Next Counter Register
__IO uint32_t	SPI_TNPR
	(Spi Offset: 0x118) Transmit Next Pointer Register
__IO uint32_t	SPI_TPR
	(Spi Offset: 0x108) Transmit Pointer Register
__IO uint32_t	SPI_WPMR
	(Spi Offset: 0xE4) Write Protection Control Register
__I uint32_t	SPI_WPSR
	(Spi Offset: 0xE8) Write Protection Status Register

Detailed Description

Spi hardware registers.

Definition at line 46 of file component_spi.h.

Field Documentation

Reserved1

__I uint32_t Spi::Reserved1[4]

Definition at line 55 of file component_spi.h.

Reserved2

__I uint32_t Spi::Reserved2[41]

Definition at line 57 of file component_spi.h.

Reserved3

__I uint32_t Spi::Reserved3[5]

Definition at line 60 of file component_spi.h.

SPI_CR

__O uint32_t Spi::SPI_CR

(Spi Offset: 0x00) Control Register

Definition at line 47 of file component_spi.h.

Referenced by spi_disable(), spi_enable(), spi_reset(), and spi_set_lastxfer().

SPI_CSR

__IO uint32_t Spi::SPI_CSR[4]

(Spi Offset: 0x30) Chip Select Register

Definition at line 56 of file component_spi.h.

Referenced by spi_configure_cs_behavior(), spi_set_baudrate_div(), spi_set_bits_per_transfer(), spi_set_clock_phase(), spi_set_clock_polarity(), and spi_set_transfer_delay().

SPI_IDR

__O uint32_t Spi::SPI_IDR

(Spi Offset: 0x18) Interrupt Disable Register

Definition at line 53 of file component_spi.h.

Referenced by spi_disable_interrupt().

SPI_IER

__O uint32_t Spi::SPI_IER

(Spi Offset: 0x14) Interrupt Enable Register

Definition at line 52 of file component_spi.h.

Referenced by spi_enable_interrupt().

SPI_IMR

__I uint32_t Spi::SPI_IMR

(Spi Offset: 0x1C) Interrupt Mask Register

Definition at line 54 of file component_spi.h.

Referenced by spi_read_interrupt_mask().

SPI_MR

__IO uint32_t Spi::SPI_MR

(Spi Offset: 0x04) Mode Register

Definition at line 48 of file component_spi.h.

Referenced by spi_disable_loopback(), spi_disable_mode_fault_detect(), spi_disable_peripheral_select_decode(), spi_disable_tx_on_rx_empty(), spi_enable_loopback(), spi_enable_mode_fault_detect(), spi_enable_peripheral_select_decode(), spi_enable_tx_on_rx_empty(), spi_get_mode(), spi_get_mode_fault_detect_setting(), spi_get_peripheral_select_decode_setting(), spi_get_peripheral_select_mode(), spi_get_tx_on_rx_empty_setting(), spi_set_delay_between_chip_select(), spi_set_fixed_peripheral_select(), spi_set_master_mode(), spi_set_peripheral_chip_select_value(), spi_set_slave_mode(), and spi_set_variable_peripheral_select().

SPI_PTCR

__O uint32_t Spi::SPI_PTCR

(Spi Offset: 0x120) Transfer Control Register

Definition at line 69 of file component_spi.h.

SPI_PTSR

__I uint32_t Spi::SPI_PTSR

(Spi Offset: 0x124) Transfer Status Register

Definition at line 70 of file component_spi.h.

SPI_RCR

__IO uint32_t Spi::SPI_RCR

(Spi Offset: 0x104) Receive Counter Register

Definition at line 62 of file component_spi.h.

SPI_RDR

__I uint32_t Spi::SPI_RDR

(Spi Offset: 0x08) Receive Data Register

Definition at line 49 of file component_spi.h.

Referenced by spi_get(), and spi_read().

SPI_RNCR

__IO uint32_t Spi::SPI_RNCR

(Spi Offset: 0x114) Receive Next Counter Register

Definition at line 66 of file component_spi.h.

SPI_RNPR

__IO uint32_t Spi::SPI_RNPR

(Spi Offset: 0x110) Receive Next Pointer Register

Definition at line 65 of file component_spi.h.

SPI_RPR

__IO uint32_t Spi::SPI_RPR

(Spi Offset: 0x100) Receive Pointer Register

Definition at line 61 of file component_spi.h.

Referenced by spi_get_pdc_base().

SPI_SR

__I uint32_t Spi::SPI_SR

(Spi Offset: 0x10) Status Register

Definition at line 51 of file component_spi.h.

Referenced by spi_is_enabled(), spi_is_rx_full(), spi_is_rx_ready(), spi_is_tx_empty(), spi_is_tx_ready(), spi_read(), spi_read_status(), and spi_write().

SPI_TCR

__IO uint32_t Spi::SPI_TCR

(Spi Offset: 0x10C) Transmit Counter Register

Definition at line 64 of file component_spi.h.

SPI_TDR

__O uint32_t Spi::SPI_TDR

(Spi Offset: 0x0C) Transmit Data Register

Definition at line 50 of file component_spi.h.

Referenced by spi_put(), and spi_write().

SPI_TNCR

__IO uint32_t Spi::SPI_TNCR

(Spi Offset: 0x11C) Transmit Next Counter Register

Definition at line 68 of file component_spi.h.

SPI_TNPR

__IO uint32_t Spi::SPI_TNPR

(Spi Offset: 0x118) Transmit Next Pointer Register

Definition at line 67 of file component_spi.h.

SPI_TPR

__IO uint32_t Spi::SPI_TPR

(Spi Offset: 0x108) Transmit Pointer Register

Definition at line 63 of file component_spi.h.

SPI_WPMR

__IO uint32_t Spi::SPI_WPMR

(Spi Offset: 0xE4) Write Protection Control Register

Definition at line 58 of file component_spi.h.

Referenced by spi_set_writeprotect().

SPI_WPSR

__I uint32_t Spi::SPI_WPSR

(Spi Offset: 0xE8) Write Protection Status Register

Definition at line 59 of file component_spi.h.

Referenced by spi_get_writeprotect_status().