spi.h

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/*
 * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
 */
 
#ifndef SPI_H_INCLUDED
#define SPI_H_INCLUDED
 
#include "compiler.h"


#ifdef __cplusplus
extern "C" {
#endif

#define SPI_TIMEOUT       15000

typedef enum
{
    SPI_ERROR = -1,
    SPI_OK = 0,
    SPI_ERROR_TIMEOUT = 1,
    SPI_ERROR_ARGUMENT,
    SPI_ERROR_OVERRUN,
    SPI_ERROR_MODE_FAULT,
    SPI_ERROR_OVERRUN_AND_MODE_FAULT
} spi_status_t;

typedef enum spi_cs_behavior {
    SPI_CS_KEEP_LOW = SPI_CSR_CSAAT,
    SPI_CS_RISE_NO_TX = 0,
    SPI_CS_RISE_FORCED = SPI_CSR_CSNAAT
} spi_cs_behavior_t;

#define spi_get_pcs(chip_sel_id) ((~(1u<<(chip_sel_id)))&0xF)

static inline void spi_reset(Spi *p_spi)
{
    p_spi->SPI_CR = SPI_CR_SWRST;
}

static inline void spi_enable(Spi *p_spi)
{
    p_spi->SPI_CR = SPI_CR_SPIEN;
}

static inline void spi_disable(Spi *p_spi)
{
    p_spi->SPI_CR = SPI_CR_SPIDIS;
}

static inline void spi_set_lastxfer(Spi *p_spi)
{
    p_spi->SPI_CR = SPI_CR_LASTXFER;
}

static inline void spi_set_master_mode(Spi *p_spi)
{
    p_spi->SPI_MR |= SPI_MR_MSTR;
}

static inline void spi_set_slave_mode(Spi *p_spi)
{
    p_spi->SPI_MR &= (~SPI_MR_MSTR);
}

static inline uint32_t spi_get_mode(Spi *p_spi)
{
    if (p_spi->SPI_MR & SPI_MR_MSTR) {
        return 1;
    } else {
        return 0;
    }
}

static inline void spi_set_variable_peripheral_select(Spi *p_spi)
{
    p_spi->SPI_MR |= SPI_MR_PS;
}

static inline void spi_set_fixed_peripheral_select(Spi *p_spi)
{
    p_spi->SPI_MR &= (~SPI_MR_PS);
}

static inline uint32_t spi_get_peripheral_select_mode(Spi *p_spi)
{
    if (p_spi->SPI_MR & SPI_MR_PS) {
        return 1;
    } else {
        return 0;
    }
}

static inline void spi_enable_peripheral_select_decode(Spi *p_spi)
{
    p_spi->SPI_MR |= SPI_MR_PCSDEC;
}

static inline void spi_disable_peripheral_select_decode(Spi *p_spi)
{
    p_spi->SPI_MR &= (~SPI_MR_PCSDEC);
}

static inline uint32_t spi_get_peripheral_select_decode_setting(Spi *p_spi)
{
    if (p_spi->SPI_MR & SPI_MR_PCSDEC) {
        return 1;
    } else {
        return 0;
    }
}

static inline void spi_enable_mode_fault_detect(Spi *p_spi)
{
    p_spi->SPI_MR &= (~SPI_MR_MODFDIS);
}

static inline void spi_disable_mode_fault_detect(Spi *p_spi)
{
    p_spi->SPI_MR |= SPI_MR_MODFDIS;
}

static inline uint32_t spi_get_mode_fault_detect_setting(Spi *p_spi)
{
    if (p_spi->SPI_MR & SPI_MR_MODFDIS) {
        return 1;
    } else {
        return 0;
    }
}

static inline void spi_enable_tx_on_rx_empty(Spi *p_spi)
{
    p_spi->SPI_MR |= SPI_MR_WDRBT;
}

static inline void spi_disable_tx_on_rx_empty(Spi *p_spi)
{
    p_spi->SPI_MR &= (~SPI_MR_WDRBT);
}

static inline uint32_t spi_get_tx_on_rx_empty_setting(Spi *p_spi)
{
    if (p_spi->SPI_MR & SPI_MR_WDRBT) {
        return 1;
    } else {
        return 0;
    }
}

static inline void spi_enable_loopback(Spi *p_spi)
{
    p_spi->SPI_MR |= SPI_MR_LLB;
}

static inline void spi_disable_loopback(Spi *p_spi)
{
    p_spi->SPI_MR &= (~SPI_MR_LLB);
}
 
void spi_enable_clock(Spi *p_spi);
void spi_disable_clock(Spi *p_spi);
void spi_set_peripheral_chip_select_value(Spi *p_spi, uint32_t ul_value);
void spi_set_delay_between_chip_select(Spi *p_spi, uint32_t ul_delay);
spi_status_t spi_read(Spi *p_spi, uint16_t *us_data, uint8_t *p_pcs);
spi_status_t spi_write(Spi *p_spi, uint16_t us_data, uint8_t uc_pcs,
        uint8_t uc_last);

static inline uint32_t spi_read_status(Spi *p_spi)
{
    return p_spi->SPI_SR;
}

static inline uint32_t spi_is_enabled(Spi *p_spi)
{
    if (p_spi->SPI_SR & SPI_SR_SPIENS) {
        return 1;
    } else {
        return 0;
    }
}

static inline void spi_put(Spi *p_spi, uint16_t data)
{
    p_spi->SPI_TDR = SPI_TDR_TD(data);
}

static inline uint16_t spi_get(Spi *p_spi)
{
    return (p_spi->SPI_RDR & SPI_RDR_RD_Msk);
}

static inline uint32_t spi_is_tx_empty(Spi *p_spi)
{
    if (p_spi->SPI_SR & SPI_SR_TXEMPTY) {
        return 1;
    } else {
        return 0;
    }
}

static inline uint32_t spi_is_tx_ready(Spi *p_spi)
{
    if (p_spi->SPI_SR & SPI_SR_TDRE) {
        return 1;
    } else {
        return 0;
    }
}

static inline uint32_t spi_is_rx_full(Spi *p_spi)
{
    if (p_spi->SPI_SR & SPI_SR_RDRF) {
        return 1;
    } else {
        return 0;
    }
}

static inline uint32_t spi_is_rx_ready(Spi *p_spi)
{
    if ((p_spi->SPI_SR & (SPI_SR_RDRF | SPI_SR_TXEMPTY))
            == (SPI_SR_RDRF | SPI_SR_TXEMPTY)) {
        return 1;
    } else {
        return 0;
    }
}

static inline void spi_enable_interrupt(Spi *p_spi, uint32_t ul_sources)
{
    p_spi->SPI_IER = ul_sources;
}

static inline void spi_disable_interrupt(Spi *p_spi, uint32_t ul_sources)
{
    p_spi->SPI_IDR = ul_sources;
}

static inline uint32_t spi_read_interrupt_mask(Spi *p_spi)
{
    return p_spi->SPI_IMR;
}
 
void spi_set_clock_polarity(Spi *p_spi, uint32_t ul_pcs_ch,
        uint32_t ul_polarity);
void spi_set_clock_phase(Spi *p_spi, uint32_t ul_pcs_ch, uint32_t ul_phase);
void spi_configure_cs_behavior(Spi *p_spi, uint32_t ul_pcs_ch,
        uint32_t ul_cs_behavior);
void spi_set_bits_per_transfer(Spi *p_spi, uint32_t ul_pcs_ch, uint32_t ul_bits);
int16_t spi_calc_baudrate_div(const uint32_t baudrate, uint32_t mck);
int16_t spi_set_baudrate_div(Spi *p_spi, uint32_t ul_pcs_ch,
        uint8_t uc_baudrate_divider);
void spi_set_transfer_delay(Spi *p_spi, uint32_t ul_pcs_ch, uint8_t uc_dlybs,
        uint8_t uc_dlybct);
 
#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM)
static inline Pdc *spi_get_pdc_base(Spi *p_spi)
{
    return (Pdc *)&(p_spi->SPI_RPR);
}
#endif
 
#if (SAM3U  || SAM3XA || SAMV71 || SAMV70 || SAME70 || SAMS70)
static inline void *spi_get_tx_access(Spi *p_spi)
{
    return (void *)&(p_spi->SPI_TDR);
}

static inline void *spi_get_rx_access(Spi *p_spi)
{
    return (void *)&(p_spi->SPI_RDR);
}
#endif
 
void spi_set_writeprotect(Spi *p_spi, uint32_t ul_enable);
uint32_t spi_get_writeprotect_status(Spi *p_spi);


#ifdef __cplusplus
}
#endif

#endif /* SPI_H_INCLUDED */