Data Structures
struct	Spi
	Spi hardware registers. More...

Macros
#define	SPI_CR_LASTXFER (0x1u << 24)
	(SPI_CR) Last Transfer
#define	SPI_CR_SPIDIS (0x1u << 1)
	(SPI_CR) SPI Disable
#define	SPI_CR_SPIEN (0x1u << 0)
	(SPI_CR) SPI Enable
#define	SPI_CR_SWRST (0x1u << 7)
	(SPI_CR) SPI Software Reset
#define	SPI_CSR_BITS_10_BIT (0x2u << 4)
	(SPI_CSR[4]) 10 bits for transfer
#define	SPI_CSR_BITS_11_BIT (0x3u << 4)
	(SPI_CSR[4]) 11 bits for transfer
#define	SPI_CSR_BITS_12_BIT (0x4u << 4)
	(SPI_CSR[4]) 12 bits for transfer
#define	SPI_CSR_BITS_13_BIT (0x5u << 4)
	(SPI_CSR[4]) 13 bits for transfer
#define	SPI_CSR_BITS_14_BIT (0x6u << 4)
	(SPI_CSR[4]) 14 bits for transfer
#define	SPI_CSR_BITS_15_BIT (0x7u << 4)
	(SPI_CSR[4]) 15 bits for transfer
#define	SPI_CSR_BITS_16_BIT (0x8u << 4)
	(SPI_CSR[4]) 16 bits for transfer
#define	SPI_CSR_BITS_8_BIT (0x0u << 4)
	(SPI_CSR[4]) 8 bits for transfer
#define	SPI_CSR_BITS_9_BIT (0x1u << 4)
	(SPI_CSR[4]) 9 bits for transfer
#define	SPI_CSR_BITS_Msk (0xfu << SPI_CSR_BITS_Pos)
	(SPI_CSR[4]) Bits Per Transfer
#define	SPI_CSR_BITS_Pos 4
#define	SPI_CSR_CPOL (0x1u << 0)
	(SPI_CSR[4]) Clock Polarity
#define	SPI_CSR_CSAAT (0x1u << 3)
	(SPI_CSR[4]) Chip Select Active After Transfer
#define	SPI_CSR_CSNAAT (0x1u << 2)
	(SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
#define	SPI_CSR_DLYBCT(value)
#define	SPI_CSR_DLYBCT_Msk (0xffu << SPI_CSR_DLYBCT_Pos)
	(SPI_CSR[4]) Delay Between Consecutive Transfers
#define	SPI_CSR_DLYBCT_Pos 24
#define	SPI_CSR_DLYBS(value)
#define	SPI_CSR_DLYBS_Msk (0xffu << SPI_CSR_DLYBS_Pos)
	(SPI_CSR[4]) Delay Before SPCK
#define	SPI_CSR_DLYBS_Pos 16
#define	SPI_CSR_NCPHA (0x1u << 1)
	(SPI_CSR[4]) Clock Phase
#define	SPI_CSR_SCBR(value)
#define	SPI_CSR_SCBR_Msk (0xffu << SPI_CSR_SCBR_Pos)
	(SPI_CSR[4]) Serial Clock Baud Rate
#define	SPI_CSR_SCBR_Pos 8
#define	SPI_IDR_ENDRX (0x1u << 4)
	(SPI_IDR) End of Receive Buffer Interrupt Disable
#define	SPI_IDR_ENDTX (0x1u << 5)
	(SPI_IDR) End of Transmit Buffer Interrupt Disable
#define	SPI_IDR_MODF (0x1u << 2)
	(SPI_IDR) Mode Fault Error Interrupt Disable
#define	SPI_IDR_NSSR (0x1u << 8)
	(SPI_IDR) NSS Rising Interrupt Disable
#define	SPI_IDR_OVRES (0x1u << 3)
	(SPI_IDR) Overrun Error Interrupt Disable
#define	SPI_IDR_RDRF (0x1u << 0)
	(SPI_IDR) Receive Data Register Full Interrupt Disable
#define	SPI_IDR_RXBUFF (0x1u << 6)
	(SPI_IDR) Receive Buffer Full Interrupt Disable
#define	SPI_IDR_TDRE (0x1u << 1)
	(SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable
#define	SPI_IDR_TXBUFE (0x1u << 7)
	(SPI_IDR) Transmit Buffer Empty Interrupt Disable
#define	SPI_IDR_TXEMPTY (0x1u << 9)
	(SPI_IDR) Transmission Registers Empty Disable
#define	SPI_IDR_UNDES (0x1u << 10)
	(SPI_IDR) Underrun Error Interrupt Disable
#define	SPI_IER_ENDRX (0x1u << 4)
	(SPI_IER) End of Receive Buffer Interrupt Enable
#define	SPI_IER_ENDTX (0x1u << 5)
	(SPI_IER) End of Transmit Buffer Interrupt Enable
#define	SPI_IER_MODF (0x1u << 2)
	(SPI_IER) Mode Fault Error Interrupt Enable
#define	SPI_IER_NSSR (0x1u << 8)
	(SPI_IER) NSS Rising Interrupt Enable
#define	SPI_IER_OVRES (0x1u << 3)
	(SPI_IER) Overrun Error Interrupt Enable
#define	SPI_IER_RDRF (0x1u << 0)
	(SPI_IER) Receive Data Register Full Interrupt Enable
#define	SPI_IER_RXBUFF (0x1u << 6)
	(SPI_IER) Receive Buffer Full Interrupt Enable
#define	SPI_IER_TDRE (0x1u << 1)
	(SPI_IER) SPI Transmit Data Register Empty Interrupt Enable
#define	SPI_IER_TXBUFE (0x1u << 7)
	(SPI_IER) Transmit Buffer Empty Interrupt Enable
#define	SPI_IER_TXEMPTY (0x1u << 9)
	(SPI_IER) Transmission Registers Empty Enable
#define	SPI_IER_UNDES (0x1u << 10)
	(SPI_IER) Underrun Error Interrupt Enable
#define	SPI_IMR_ENDRX (0x1u << 4)
	(SPI_IMR) End of Receive Buffer Interrupt Mask
#define	SPI_IMR_ENDTX (0x1u << 5)
	(SPI_IMR) End of Transmit Buffer Interrupt Mask
#define	SPI_IMR_MODF (0x1u << 2)
	(SPI_IMR) Mode Fault Error Interrupt Mask
#define	SPI_IMR_NSSR (0x1u << 8)
	(SPI_IMR) NSS Rising Interrupt Mask
#define	SPI_IMR_OVRES (0x1u << 3)
	(SPI_IMR) Overrun Error Interrupt Mask
#define	SPI_IMR_RDRF (0x1u << 0)
	(SPI_IMR) Receive Data Register Full Interrupt Mask
#define	SPI_IMR_RXBUFF (0x1u << 6)
	(SPI_IMR) Receive Buffer Full Interrupt Mask
#define	SPI_IMR_TDRE (0x1u << 1)
	(SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask
#define	SPI_IMR_TXBUFE (0x1u << 7)
	(SPI_IMR) Transmit Buffer Empty Interrupt Mask
#define	SPI_IMR_TXEMPTY (0x1u << 9)
	(SPI_IMR) Transmission Registers Empty Mask
#define	SPI_IMR_UNDES (0x1u << 10)
	(SPI_IMR) Underrun Error Interrupt Mask
#define	SPI_MR_DLYBCS(value)
#define	SPI_MR_DLYBCS_Msk (0xffu << SPI_MR_DLYBCS_Pos)
	(SPI_MR) Delay Between Chip Selects
#define	SPI_MR_DLYBCS_Pos 24
#define	SPI_MR_LLB (0x1u << 7)
	(SPI_MR) Local Loopback Enable
#define	SPI_MR_MODFDIS (0x1u << 4)
	(SPI_MR) Mode Fault Detection
#define	SPI_MR_MSTR (0x1u << 0)
	(SPI_MR) Master/Slave Mode
#define	SPI_MR_PCS(value)
#define	SPI_MR_PCS_Msk (0xfu << SPI_MR_PCS_Pos)
	(SPI_MR) Peripheral Chip Select
#define	SPI_MR_PCS_Pos 16
#define	SPI_MR_PCSDEC (0x1u << 2)
	(SPI_MR) Chip Select Decode
#define	SPI_MR_PS (0x1u << 1)
	(SPI_MR) Peripheral Select
#define	SPI_MR_WDRBT (0x1u << 5)
	(SPI_MR) Wait Data Read Before Transfer
#define	SPI_PTCR_RXTDIS (0x1u << 1)
	(SPI_PTCR) Receiver Transfer Disable
#define	SPI_PTCR_RXTEN (0x1u << 0)
	(SPI_PTCR) Receiver Transfer Enable
#define	SPI_PTCR_TXTDIS (0x1u << 9)
	(SPI_PTCR) Transmitter Transfer Disable
#define	SPI_PTCR_TXTEN (0x1u << 8)
	(SPI_PTCR) Transmitter Transfer Enable
#define	SPI_PTSR_RXTEN (0x1u << 0)
	(SPI_PTSR) Receiver Transfer Enable
#define	SPI_PTSR_TXTEN (0x1u << 8)
	(SPI_PTSR) Transmitter Transfer Enable
#define	SPI_RCR_RXCTR(value)
#define	SPI_RCR_RXCTR_Msk (0xffffu << SPI_RCR_RXCTR_Pos)
	(SPI_RCR) Receive Counter Register
#define	SPI_RCR_RXCTR_Pos 0
#define	SPI_RDR_PCS_Msk (0xfu << SPI_RDR_PCS_Pos)
	(SPI_RDR) Peripheral Chip Select
#define	SPI_RDR_PCS_Pos 16
#define	SPI_RDR_RD_Msk (0xffffu << SPI_RDR_RD_Pos)
	(SPI_RDR) Receive Data
#define	SPI_RDR_RD_Pos 0
#define	SPI_RNCR_RXNCTR(value)
#define	SPI_RNCR_RXNCTR_Msk (0xffffu << SPI_RNCR_RXNCTR_Pos)
	(SPI_RNCR) Receive Next Counter
#define	SPI_RNCR_RXNCTR_Pos 0
#define	SPI_RNPR_RXNPTR(value)
#define	SPI_RNPR_RXNPTR_Msk (0xffffffffu << SPI_RNPR_RXNPTR_Pos)
	(SPI_RNPR) Receive Next Pointer
#define	SPI_RNPR_RXNPTR_Pos 0
#define	SPI_RPR_RXPTR(value)
#define	SPI_RPR_RXPTR_Msk (0xffffffffu << SPI_RPR_RXPTR_Pos)
	(SPI_RPR) Receive Pointer Register
#define	SPI_RPR_RXPTR_Pos 0
#define	SPI_SR_ENDRX (0x1u << 4)
	(SPI_SR) End of RX buffer
#define	SPI_SR_ENDTX (0x1u << 5)
	(SPI_SR) End of TX buffer
#define	SPI_SR_MODF (0x1u << 2)
	(SPI_SR) Mode Fault Error
#define	SPI_SR_NSSR (0x1u << 8)
	(SPI_SR) NSS Rising
#define	SPI_SR_OVRES (0x1u << 3)
	(SPI_SR) Overrun Error Status
#define	SPI_SR_RDRF (0x1u << 0)
	(SPI_SR) Receive Data Register Full
#define	SPI_SR_RXBUFF (0x1u << 6)
	(SPI_SR) RX Buffer Full
#define	SPI_SR_SPIENS (0x1u << 16)
	(SPI_SR) SPI Enable Status
#define	SPI_SR_TDRE (0x1u << 1)
	(SPI_SR) Transmit Data Register Empty
#define	SPI_SR_TXBUFE (0x1u << 7)
	(SPI_SR) TX Buffer Empty
#define	SPI_SR_TXEMPTY (0x1u << 9)
	(SPI_SR) Transmission Registers Empty
#define	SPI_SR_UNDES (0x1u << 10)
	(SPI_SR) Underrun Error Status (Slave Mode Only)
#define	SPI_TCR_TXCTR(value)
#define	SPI_TCR_TXCTR_Msk (0xffffu << SPI_TCR_TXCTR_Pos)
	(SPI_TCR) Transmit Counter Register
#define	SPI_TCR_TXCTR_Pos 0
#define	SPI_TDR_LASTXFER (0x1u << 24)
	(SPI_TDR) Last Transfer
#define	SPI_TDR_PCS(value)
#define	SPI_TDR_PCS_Msk (0xfu << SPI_TDR_PCS_Pos)
	(SPI_TDR) Peripheral Chip Select
#define	SPI_TDR_PCS_Pos 16
#define	SPI_TDR_TD(value)
#define	SPI_TDR_TD_Msk (0xffffu << SPI_TDR_TD_Pos)
	(SPI_TDR) Transmit Data
#define	SPI_TDR_TD_Pos 0
#define	SPI_TNCR_TXNCTR(value)
#define	SPI_TNCR_TXNCTR_Msk (0xffffu << SPI_TNCR_TXNCTR_Pos)
	(SPI_TNCR) Transmit Counter Next
#define	SPI_TNCR_TXNCTR_Pos 0
#define	SPI_TNPR_TXNPTR(value)
#define	SPI_TNPR_TXNPTR_Msk (0xffffffffu << SPI_TNPR_TXNPTR_Pos)
	(SPI_TNPR) Transmit Next Pointer
#define	SPI_TNPR_TXNPTR_Pos 0
#define	SPI_TPR_TXPTR(value)
#define	SPI_TPR_TXPTR_Msk (0xffffffffu << SPI_TPR_TXPTR_Pos)
	(SPI_TPR) Transmit Counter Register
#define	SPI_TPR_TXPTR_Pos 0
#define	SPI_WPMR_WPEN (0x1u << 0)
	(SPI_WPMR) Write Protect Enable
#define	SPI_WPMR_WPKEY_Msk (0xffffffu << SPI_WPMR_WPKEY_Pos)
	(SPI_WPMR) Write Protect Key
#define	SPI_WPMR_WPKEY_PASSWD (0x535049u << 8)
	(SPI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.
#define	SPI_WPMR_WPKEY_Pos 8
#define	SPI_WPSR_WPVS (0x1u << 0)
	(SPI_WPSR) Write Protection Violation Status
#define	SPI_WPSR_WPVSRC_Msk (0xffu << SPI_WPSR_WPVSRC_Pos)
	(SPI_WPSR) Write Protection Violation Source
#define	SPI_WPSR_WPVSRC_Pos 8

Detailed Description

and its subsidiaries.

\cond ASF_LICENSE

Definition in file component_spi.h.

Macro Definition Documentation

◆ SPI_CR_LASTXFER

#define SPI_CR_LASTXFER (0x1u << 24)

(SPI_CR) Last Transfer

Definition at line 77 of file component_spi.h.

Referenced by spi_set_lastxfer().

◆ SPI_CR_SPIDIS

#define SPI_CR_SPIDIS (0x1u << 1)

(SPI_CR) SPI Disable

Definition at line 75 of file component_spi.h.

Referenced by spi_disable().

◆ SPI_CR_SPIEN

#define SPI_CR_SPIEN (0x1u << 0)

(SPI_CR) SPI Enable

Definition at line 74 of file component_spi.h.

Referenced by spi_enable().

◆ SPI_CR_SWRST

#define SPI_CR_SWRST (0x1u << 7)

(SPI_CR) SPI Software Reset

Definition at line 76 of file component_spi.h.

Referenced by spi_reset().

◆ SPI_CSR_BITS_10_BIT

#define SPI_CSR_BITS_10_BIT (0x2u << 4)

(SPI_CSR[4]) 10 bits for transfer

Definition at line 162 of file component_spi.h.

◆ SPI_CSR_BITS_11_BIT

#define SPI_CSR_BITS_11_BIT (0x3u << 4)

(SPI_CSR[4]) 11 bits for transfer

Definition at line 163 of file component_spi.h.

◆ SPI_CSR_BITS_12_BIT

#define SPI_CSR_BITS_12_BIT (0x4u << 4)

(SPI_CSR[4]) 12 bits for transfer

Definition at line 164 of file component_spi.h.

◆ SPI_CSR_BITS_13_BIT

#define SPI_CSR_BITS_13_BIT (0x5u << 4)

(SPI_CSR[4]) 13 bits for transfer

Definition at line 165 of file component_spi.h.

◆ SPI_CSR_BITS_14_BIT

#define SPI_CSR_BITS_14_BIT (0x6u << 4)

(SPI_CSR[4]) 14 bits for transfer

Definition at line 166 of file component_spi.h.

◆ SPI_CSR_BITS_15_BIT

#define SPI_CSR_BITS_15_BIT (0x7u << 4)

(SPI_CSR[4]) 15 bits for transfer

Definition at line 167 of file component_spi.h.

◆ SPI_CSR_BITS_16_BIT

#define SPI_CSR_BITS_16_BIT (0x8u << 4)

(SPI_CSR[4]) 16 bits for transfer

Definition at line 168 of file component_spi.h.

◆ SPI_CSR_BITS_8_BIT

#define SPI_CSR_BITS_8_BIT (0x0u << 4)

(SPI_CSR[4]) 8 bits for transfer

Definition at line 160 of file component_spi.h.

◆ SPI_CSR_BITS_9_BIT

#define SPI_CSR_BITS_9_BIT (0x1u << 4)

(SPI_CSR[4]) 9 bits for transfer

Definition at line 161 of file component_spi.h.

◆ SPI_CSR_BITS_Msk

#define SPI_CSR_BITS_Msk (0xfu << SPI_CSR_BITS_Pos)

(SPI_CSR[4]) Bits Per Transfer

Definition at line 159 of file component_spi.h.

Referenced by spi_set_bits_per_transfer().

◆ SPI_CSR_BITS_Pos

#define SPI_CSR_BITS_Pos 4

Definition at line 158 of file component_spi.h.

◆ SPI_CSR_CPOL

#define SPI_CSR_CPOL (0x1u << 0)

(SPI_CSR[4]) Clock Polarity

Definition at line 154 of file component_spi.h.

Referenced by spi_set_clock_polarity().

◆ SPI_CSR_CSAAT

#define SPI_CSR_CSAAT (0x1u << 3)

(SPI_CSR[4]) Chip Select Active After Transfer

Definition at line 157 of file component_spi.h.

Referenced by spi_configure_cs_behavior().

◆ SPI_CSR_CSNAAT

#define SPI_CSR_CSNAAT (0x1u << 2)

(SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1)

Definition at line 156 of file component_spi.h.

Referenced by spi_configure_cs_behavior().

◆ SPI_CSR_DLYBCT

#define SPI_CSR_DLYBCT ( value )

Value:

((SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos)))

SPI_CSR_DLYBCT_Msk

#define SPI_CSR_DLYBCT_Msk

(SPI_CSR[4]) Delay Between Consecutive Transfers

Definition component_spi.h:176

SPI_CSR_DLYBCT_Pos

#define SPI_CSR_DLYBCT_Pos

Definition component_spi.h:175

Definition at line 177 of file component_spi.h.

Referenced by spi_set_transfer_delay().

◆ SPI_CSR_DLYBCT_Msk

#define SPI_CSR_DLYBCT_Msk (0xffu << SPI_CSR_DLYBCT_Pos)

(SPI_CSR[4]) Delay Between Consecutive Transfers

Definition at line 176 of file component_spi.h.

Referenced by spi_set_transfer_delay().

◆ SPI_CSR_DLYBCT_Pos

#define SPI_CSR_DLYBCT_Pos 24

Definition at line 175 of file component_spi.h.

◆ SPI_CSR_DLYBS

#define SPI_CSR_DLYBS ( value )

Value:

((SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos)))

SPI_CSR_DLYBS_Pos

#define SPI_CSR_DLYBS_Pos

Definition component_spi.h:172

SPI_CSR_DLYBS_Msk

#define SPI_CSR_DLYBS_Msk

(SPI_CSR[4]) Delay Before SPCK

Definition component_spi.h:173

Definition at line 174 of file component_spi.h.

Referenced by spi_set_transfer_delay().

◆ SPI_CSR_DLYBS_Msk

#define SPI_CSR_DLYBS_Msk (0xffu << SPI_CSR_DLYBS_Pos)

(SPI_CSR[4]) Delay Before SPCK

Definition at line 173 of file component_spi.h.

Referenced by spi_set_transfer_delay().

◆ SPI_CSR_DLYBS_Pos

#define SPI_CSR_DLYBS_Pos 16

Definition at line 172 of file component_spi.h.

◆ SPI_CSR_NCPHA

#define SPI_CSR_NCPHA (0x1u << 1)

(SPI_CSR[4]) Clock Phase

Definition at line 155 of file component_spi.h.

Referenced by spi_set_clock_phase().

◆ SPI_CSR_SCBR

#define SPI_CSR_SCBR ( value )

Value:

((SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos)))

SPI_CSR_SCBR_Msk

#define SPI_CSR_SCBR_Msk

(SPI_CSR[4]) Serial Clock Baud Rate

Definition component_spi.h:170

SPI_CSR_SCBR_Pos

#define SPI_CSR_SCBR_Pos

Definition component_spi.h:169

Definition at line 171 of file component_spi.h.

Referenced by spi_set_baudrate_div().

◆ SPI_CSR_SCBR_Msk

#define SPI_CSR_SCBR_Msk (0xffu << SPI_CSR_SCBR_Pos)

(SPI_CSR[4]) Serial Clock Baud Rate

Definition at line 170 of file component_spi.h.

Referenced by spi_set_baudrate_div().

◆ SPI_CSR_SCBR_Pos

#define SPI_CSR_SCBR_Pos 8

Definition at line 169 of file component_spi.h.

◆ SPI_IDR_ENDRX

#define SPI_IDR_ENDRX (0x1u << 4)

(SPI_IDR) End of Receive Buffer Interrupt Disable

Definition at line 134 of file component_spi.h.

◆ SPI_IDR_ENDTX

#define SPI_IDR_ENDTX (0x1u << 5)

(SPI_IDR) End of Transmit Buffer Interrupt Disable

Definition at line 135 of file component_spi.h.

◆ SPI_IDR_MODF

#define SPI_IDR_MODF (0x1u << 2)

(SPI_IDR) Mode Fault Error Interrupt Disable

Definition at line 132 of file component_spi.h.

◆ SPI_IDR_NSSR

#define SPI_IDR_NSSR (0x1u << 8)

(SPI_IDR) NSS Rising Interrupt Disable

Definition at line 138 of file component_spi.h.

◆ SPI_IDR_OVRES

#define SPI_IDR_OVRES (0x1u << 3)

(SPI_IDR) Overrun Error Interrupt Disable

Definition at line 133 of file component_spi.h.

◆ SPI_IDR_RDRF

#define SPI_IDR_RDRF (0x1u << 0)

(SPI_IDR) Receive Data Register Full Interrupt Disable

Definition at line 130 of file component_spi.h.

◆ SPI_IDR_RXBUFF

#define SPI_IDR_RXBUFF (0x1u << 6)

(SPI_IDR) Receive Buffer Full Interrupt Disable

Definition at line 136 of file component_spi.h.

◆ SPI_IDR_TDRE

#define SPI_IDR_TDRE (0x1u << 1)

(SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable

Definition at line 131 of file component_spi.h.

◆ SPI_IDR_TXBUFE

#define SPI_IDR_TXBUFE (0x1u << 7)

(SPI_IDR) Transmit Buffer Empty Interrupt Disable

Definition at line 137 of file component_spi.h.

◆ SPI_IDR_TXEMPTY

#define SPI_IDR_TXEMPTY (0x1u << 9)

(SPI_IDR) Transmission Registers Empty Disable

Definition at line 139 of file component_spi.h.

◆ SPI_IDR_UNDES

#define SPI_IDR_UNDES (0x1u << 10)

(SPI_IDR) Underrun Error Interrupt Disable

Definition at line 140 of file component_spi.h.

◆ SPI_IER_ENDRX

#define SPI_IER_ENDRX (0x1u << 4)

(SPI_IER) End of Receive Buffer Interrupt Enable

Definition at line 122 of file component_spi.h.

◆ SPI_IER_ENDTX

#define SPI_IER_ENDTX (0x1u << 5)

(SPI_IER) End of Transmit Buffer Interrupt Enable

Definition at line 123 of file component_spi.h.

◆ SPI_IER_MODF

#define SPI_IER_MODF (0x1u << 2)

(SPI_IER) Mode Fault Error Interrupt Enable

Definition at line 120 of file component_spi.h.

◆ SPI_IER_NSSR

#define SPI_IER_NSSR (0x1u << 8)

(SPI_IER) NSS Rising Interrupt Enable

Definition at line 126 of file component_spi.h.

◆ SPI_IER_OVRES

#define SPI_IER_OVRES (0x1u << 3)

(SPI_IER) Overrun Error Interrupt Enable

Definition at line 121 of file component_spi.h.

◆ SPI_IER_RDRF

#define SPI_IER_RDRF (0x1u << 0)

(SPI_IER) Receive Data Register Full Interrupt Enable

Definition at line 118 of file component_spi.h.

◆ SPI_IER_RXBUFF

#define SPI_IER_RXBUFF (0x1u << 6)

(SPI_IER) Receive Buffer Full Interrupt Enable

Definition at line 124 of file component_spi.h.

◆ SPI_IER_TDRE

#define SPI_IER_TDRE (0x1u << 1)

(SPI_IER) SPI Transmit Data Register Empty Interrupt Enable

Definition at line 119 of file component_spi.h.

◆ SPI_IER_TXBUFE

#define SPI_IER_TXBUFE (0x1u << 7)

(SPI_IER) Transmit Buffer Empty Interrupt Enable

Definition at line 125 of file component_spi.h.

◆ SPI_IER_TXEMPTY

#define SPI_IER_TXEMPTY (0x1u << 9)

(SPI_IER) Transmission Registers Empty Enable

Definition at line 127 of file component_spi.h.

◆ SPI_IER_UNDES

#define SPI_IER_UNDES (0x1u << 10)

(SPI_IER) Underrun Error Interrupt Enable

Definition at line 128 of file component_spi.h.

◆ SPI_IMR_ENDRX

#define SPI_IMR_ENDRX (0x1u << 4)

(SPI_IMR) End of Receive Buffer Interrupt Mask

Definition at line 146 of file component_spi.h.

◆ SPI_IMR_ENDTX

#define SPI_IMR_ENDTX (0x1u << 5)

(SPI_IMR) End of Transmit Buffer Interrupt Mask

Definition at line 147 of file component_spi.h.

◆ SPI_IMR_MODF

#define SPI_IMR_MODF (0x1u << 2)

(SPI_IMR) Mode Fault Error Interrupt Mask

Definition at line 144 of file component_spi.h.

◆ SPI_IMR_NSSR

#define SPI_IMR_NSSR (0x1u << 8)

(SPI_IMR) NSS Rising Interrupt Mask

Definition at line 150 of file component_spi.h.

◆ SPI_IMR_OVRES

#define SPI_IMR_OVRES (0x1u << 3)

(SPI_IMR) Overrun Error Interrupt Mask

Definition at line 145 of file component_spi.h.

◆ SPI_IMR_RDRF

#define SPI_IMR_RDRF (0x1u << 0)

(SPI_IMR) Receive Data Register Full Interrupt Mask

Definition at line 142 of file component_spi.h.

◆ SPI_IMR_RXBUFF

#define SPI_IMR_RXBUFF (0x1u << 6)

(SPI_IMR) Receive Buffer Full Interrupt Mask

Definition at line 148 of file component_spi.h.

◆ SPI_IMR_TDRE

#define SPI_IMR_TDRE (0x1u << 1)

(SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask

Definition at line 143 of file component_spi.h.

◆ SPI_IMR_TXBUFE

#define SPI_IMR_TXBUFE (0x1u << 7)

(SPI_IMR) Transmit Buffer Empty Interrupt Mask

Definition at line 149 of file component_spi.h.

◆ SPI_IMR_TXEMPTY

#define SPI_IMR_TXEMPTY (0x1u << 9)

(SPI_IMR) Transmission Registers Empty Mask

Definition at line 151 of file component_spi.h.

◆ SPI_IMR_UNDES

#define SPI_IMR_UNDES (0x1u << 10)

(SPI_IMR) Underrun Error Interrupt Mask

Definition at line 152 of file component_spi.h.

◆ SPI_MR_DLYBCS

#define SPI_MR_DLYBCS ( value )

Value:

((SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos)))

SPI_MR_DLYBCS_Msk

#define SPI_MR_DLYBCS_Msk

(SPI_MR) Delay Between Chip Selects

Definition component_spi.h:89

SPI_MR_DLYBCS_Pos

#define SPI_MR_DLYBCS_Pos

Definition component_spi.h:88

Definition at line 90 of file component_spi.h.

Referenced by spi_set_delay_between_chip_select().

◆ SPI_MR_DLYBCS_Msk

#define SPI_MR_DLYBCS_Msk (0xffu << SPI_MR_DLYBCS_Pos)

(SPI_MR) Delay Between Chip Selects

Definition at line 89 of file component_spi.h.

Referenced by spi_set_delay_between_chip_select().

◆ SPI_MR_DLYBCS_Pos

#define SPI_MR_DLYBCS_Pos 24

Definition at line 88 of file component_spi.h.

◆ SPI_MR_LLB

#define SPI_MR_LLB (0x1u << 7)

(SPI_MR) Local Loopback Enable

Definition at line 84 of file component_spi.h.

Referenced by spi_disable_loopback(), and spi_enable_loopback().

◆ SPI_MR_MODFDIS

#define SPI_MR_MODFDIS (0x1u << 4)

(SPI_MR) Mode Fault Detection

Definition at line 82 of file component_spi.h.

Referenced by spi_disable_mode_fault_detect(), spi_enable_mode_fault_detect(), and spi_get_mode_fault_detect_setting().

◆ SPI_MR_MSTR

#define SPI_MR_MSTR (0x1u << 0)

(SPI_MR) Master/Slave Mode

Definition at line 79 of file component_spi.h.

Referenced by spi_get_mode(), spi_set_master_mode(), and spi_set_slave_mode().

◆ SPI_MR_PCS

#define SPI_MR_PCS ( value )

Value:

((SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos)))

SPI_MR_PCS_Msk

#define SPI_MR_PCS_Msk

(SPI_MR) Peripheral Chip Select

Definition component_spi.h:86

SPI_MR_PCS_Pos

#define SPI_MR_PCS_Pos

Definition component_spi.h:85

Definition at line 87 of file component_spi.h.

Referenced by spi_set_peripheral_chip_select_value().

◆ SPI_MR_PCS_Msk

#define SPI_MR_PCS_Msk (0xfu << SPI_MR_PCS_Pos)

(SPI_MR) Peripheral Chip Select

Definition at line 86 of file component_spi.h.

Referenced by spi_set_peripheral_chip_select_value().

◆ SPI_MR_PCS_Pos

#define SPI_MR_PCS_Pos 16

Definition at line 85 of file component_spi.h.

◆ SPI_MR_PCSDEC

#define SPI_MR_PCSDEC (0x1u << 2)

(SPI_MR) Chip Select Decode

Definition at line 81 of file component_spi.h.

Referenced by spi_disable_peripheral_select_decode(), spi_enable_peripheral_select_decode(), and spi_get_peripheral_select_decode_setting().

◆ SPI_MR_PS

#define SPI_MR_PS (0x1u << 1)

(SPI_MR) Peripheral Select

Definition at line 80 of file component_spi.h.

Referenced by spi_get_peripheral_select_mode(), spi_set_fixed_peripheral_select(), and spi_set_variable_peripheral_select().

◆ SPI_MR_WDRBT

#define SPI_MR_WDRBT (0x1u << 5)

(SPI_MR) Wait Data Read Before Transfer

Definition at line 83 of file component_spi.h.

Referenced by spi_disable_tx_on_rx_empty(), spi_enable_tx_on_rx_empty(), and spi_get_tx_on_rx_empty_setting().

◆ SPI_PTCR_RXTDIS

#define SPI_PTCR_RXTDIS (0x1u << 1)

(SPI_PTCR) Receiver Transfer Disable

Definition at line 221 of file component_spi.h.

◆ SPI_PTCR_RXTEN

#define SPI_PTCR_RXTEN (0x1u << 0)

(SPI_PTCR) Receiver Transfer Enable

Definition at line 220 of file component_spi.h.

◆ SPI_PTCR_TXTDIS

#define SPI_PTCR_TXTDIS (0x1u << 9)

(SPI_PTCR) Transmitter Transfer Disable

Definition at line 223 of file component_spi.h.

◆ SPI_PTCR_TXTEN

#define SPI_PTCR_TXTEN (0x1u << 8)

(SPI_PTCR) Transmitter Transfer Enable

Definition at line 222 of file component_spi.h.

◆ SPI_PTSR_RXTEN

#define SPI_PTSR_RXTEN (0x1u << 0)

(SPI_PTSR) Receiver Transfer Enable

Definition at line 225 of file component_spi.h.

◆ SPI_PTSR_TXTEN

#define SPI_PTSR_TXTEN (0x1u << 8)

(SPI_PTSR) Transmitter Transfer Enable

Definition at line 226 of file component_spi.h.

◆ SPI_RCR_RXCTR

#define SPI_RCR_RXCTR ( value )

Value:

((SPI_RCR_RXCTR_Msk & ((value) << SPI_RCR_RXCTR_Pos)))

SPI_RCR_RXCTR_Msk

#define SPI_RCR_RXCTR_Msk

(SPI_RCR) Receive Counter Register

Definition component_spi.h:193

SPI_RCR_RXCTR_Pos

#define SPI_RCR_RXCTR_Pos

Definition component_spi.h:192

Definition at line 194 of file component_spi.h.

◆ SPI_RCR_RXCTR_Msk

#define SPI_RCR_RXCTR_Msk (0xffffu << SPI_RCR_RXCTR_Pos)

(SPI_RCR) Receive Counter Register

Definition at line 193 of file component_spi.h.

◆ SPI_RCR_RXCTR_Pos

#define SPI_RCR_RXCTR_Pos 0

Definition at line 192 of file component_spi.h.

◆ SPI_RDR_PCS_Msk

#define SPI_RDR_PCS_Msk (0xfu << SPI_RDR_PCS_Pos)

(SPI_RDR) Peripheral Chip Select

Definition at line 95 of file component_spi.h.

Referenced by spi_read().

◆ SPI_RDR_PCS_Pos

#define SPI_RDR_PCS_Pos 16

Definition at line 94 of file component_spi.h.

Referenced by spi_read().

◆ SPI_RDR_RD_Msk

#define SPI_RDR_RD_Msk (0xffffu << SPI_RDR_RD_Pos)

(SPI_RDR) Receive Data

Definition at line 93 of file component_spi.h.

Referenced by spi_get(), and spi_read().

◆ SPI_RDR_RD_Pos

#define SPI_RDR_RD_Pos 0

Definition at line 92 of file component_spi.h.

◆ SPI_RNCR_RXNCTR

#define SPI_RNCR_RXNCTR ( value )

Value:

((SPI_RNCR_RXNCTR_Msk & ((value) << SPI_RNCR_RXNCTR_Pos)))

SPI_RNCR_RXNCTR_Pos

#define SPI_RNCR_RXNCTR_Pos

Definition component_spi.h:208

SPI_RNCR_RXNCTR_Msk

#define SPI_RNCR_RXNCTR_Msk

(SPI_RNCR) Receive Next Counter

Definition component_spi.h:209

Definition at line 210 of file component_spi.h.

◆ SPI_RNCR_RXNCTR_Msk

#define SPI_RNCR_RXNCTR_Msk (0xffffu << SPI_RNCR_RXNCTR_Pos)

(SPI_RNCR) Receive Next Counter

Definition at line 209 of file component_spi.h.

◆ SPI_RNCR_RXNCTR_Pos

#define SPI_RNCR_RXNCTR_Pos 0

Definition at line 208 of file component_spi.h.

◆ SPI_RNPR_RXNPTR

#define SPI_RNPR_RXNPTR ( value )

Value:

((SPI_RNPR_RXNPTR_Msk & ((value) << SPI_RNPR_RXNPTR_Pos)))

SPI_RNPR_RXNPTR_Pos

#define SPI_RNPR_RXNPTR_Pos

Definition component_spi.h:204

SPI_RNPR_RXNPTR_Msk

#define SPI_RNPR_RXNPTR_Msk

(SPI_RNPR) Receive Next Pointer

Definition component_spi.h:205

Definition at line 206 of file component_spi.h.

◆ SPI_RNPR_RXNPTR_Msk

#define SPI_RNPR_RXNPTR_Msk (0xffffffffu << SPI_RNPR_RXNPTR_Pos)

(SPI_RNPR) Receive Next Pointer

Definition at line 205 of file component_spi.h.

◆ SPI_RNPR_RXNPTR_Pos

#define SPI_RNPR_RXNPTR_Pos 0

Definition at line 204 of file component_spi.h.

◆ SPI_RPR_RXPTR

#define SPI_RPR_RXPTR ( value )

Value:

((SPI_RPR_RXPTR_Msk & ((value) << SPI_RPR_RXPTR_Pos)))

SPI_RPR_RXPTR_Pos

#define SPI_RPR_RXPTR_Pos

Definition component_spi.h:188

SPI_RPR_RXPTR_Msk

#define SPI_RPR_RXPTR_Msk

(SPI_RPR) Receive Pointer Register

Definition component_spi.h:189

Definition at line 190 of file component_spi.h.

◆ SPI_RPR_RXPTR_Msk

#define SPI_RPR_RXPTR_Msk (0xffffffffu << SPI_RPR_RXPTR_Pos)

(SPI_RPR) Receive Pointer Register

Definition at line 189 of file component_spi.h.

◆ SPI_RPR_RXPTR_Pos

#define SPI_RPR_RXPTR_Pos 0

Definition at line 188 of file component_spi.h.

◆ SPI_SR_ENDRX

#define SPI_SR_ENDRX (0x1u << 4)

(SPI_SR) End of RX buffer

Definition at line 109 of file component_spi.h.

◆ SPI_SR_ENDTX

#define SPI_SR_ENDTX (0x1u << 5)

(SPI_SR) End of TX buffer

Definition at line 110 of file component_spi.h.

◆ SPI_SR_MODF

#define SPI_SR_MODF (0x1u << 2)

(SPI_SR) Mode Fault Error

Definition at line 107 of file component_spi.h.

◆ SPI_SR_NSSR

#define SPI_SR_NSSR (0x1u << 8)

(SPI_SR) NSS Rising

Definition at line 113 of file component_spi.h.

◆ SPI_SR_OVRES

#define SPI_SR_OVRES (0x1u << 3)

(SPI_SR) Overrun Error Status

Definition at line 108 of file component_spi.h.

◆ SPI_SR_RDRF

#define SPI_SR_RDRF (0x1u << 0)

(SPI_SR) Receive Data Register Full

Definition at line 105 of file component_spi.h.

Referenced by spi_is_rx_full(), spi_is_rx_ready(), and spi_read().

◆ SPI_SR_RXBUFF

#define SPI_SR_RXBUFF (0x1u << 6)

(SPI_SR) RX Buffer Full

Definition at line 111 of file component_spi.h.

◆ SPI_SR_SPIENS

#define SPI_SR_SPIENS (0x1u << 16)

(SPI_SR) SPI Enable Status

Definition at line 116 of file component_spi.h.

Referenced by spi_is_enabled().

◆ SPI_SR_TDRE

#define SPI_SR_TDRE (0x1u << 1)

(SPI_SR) Transmit Data Register Empty

Definition at line 106 of file component_spi.h.

Referenced by spi_is_tx_ready(), and spi_write().

◆ SPI_SR_TXBUFE

#define SPI_SR_TXBUFE (0x1u << 7)

(SPI_SR) TX Buffer Empty

Definition at line 112 of file component_spi.h.

◆ SPI_SR_TXEMPTY

#define SPI_SR_TXEMPTY (0x1u << 9)

(SPI_SR) Transmission Registers Empty

Definition at line 114 of file component_spi.h.

Referenced by spi_is_rx_ready(), and spi_is_tx_empty().

◆ SPI_SR_UNDES

#define SPI_SR_UNDES (0x1u << 10)

(SPI_SR) Underrun Error Status (Slave Mode Only)

Definition at line 115 of file component_spi.h.

◆ SPI_TCR_TXCTR

#define SPI_TCR_TXCTR ( value )

Value:

((SPI_TCR_TXCTR_Msk & ((value) << SPI_TCR_TXCTR_Pos)))

SPI_TCR_TXCTR_Pos

#define SPI_TCR_TXCTR_Pos

Definition component_spi.h:200

SPI_TCR_TXCTR_Msk

#define SPI_TCR_TXCTR_Msk

(SPI_TCR) Transmit Counter Register

Definition component_spi.h:201

Definition at line 202 of file component_spi.h.

◆ SPI_TCR_TXCTR_Msk

#define SPI_TCR_TXCTR_Msk (0xffffu << SPI_TCR_TXCTR_Pos)

(SPI_TCR) Transmit Counter Register

Definition at line 201 of file component_spi.h.

◆ SPI_TCR_TXCTR_Pos

#define SPI_TCR_TXCTR_Pos 0

Definition at line 200 of file component_spi.h.

◆ SPI_TDR_LASTXFER

#define SPI_TDR_LASTXFER (0x1u << 24)

(SPI_TDR) Last Transfer

Definition at line 103 of file component_spi.h.

Referenced by spi_write().

◆ SPI_TDR_PCS

#define SPI_TDR_PCS ( value )

Value:

((SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos)))

SPI_TDR_PCS_Msk

#define SPI_TDR_PCS_Msk

(SPI_TDR) Peripheral Chip Select

Definition component_spi.h:101

SPI_TDR_PCS_Pos

#define SPI_TDR_PCS_Pos

Definition component_spi.h:100

Definition at line 102 of file component_spi.h.

Referenced by spi_write().

◆ SPI_TDR_PCS_Msk

#define SPI_TDR_PCS_Msk (0xfu << SPI_TDR_PCS_Pos)

(SPI_TDR) Peripheral Chip Select

Definition at line 101 of file component_spi.h.

◆ SPI_TDR_PCS_Pos

#define SPI_TDR_PCS_Pos 16

Definition at line 100 of file component_spi.h.

◆ SPI_TDR_TD

#define SPI_TDR_TD ( value )

Value:

((SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos)))

SPI_TDR_TD_Pos

#define SPI_TDR_TD_Pos

Definition component_spi.h:97

SPI_TDR_TD_Msk

#define SPI_TDR_TD_Msk

(SPI_TDR) Transmit Data

Definition component_spi.h:98

Definition at line 99 of file component_spi.h.

Referenced by spi_put(), and spi_write().

◆ SPI_TDR_TD_Msk

#define SPI_TDR_TD_Msk (0xffffu << SPI_TDR_TD_Pos)

(SPI_TDR) Transmit Data

Definition at line 98 of file component_spi.h.

◆ SPI_TDR_TD_Pos

#define SPI_TDR_TD_Pos 0

Definition at line 97 of file component_spi.h.

◆ SPI_TNCR_TXNCTR

#define SPI_TNCR_TXNCTR ( value )

Value:

((SPI_TNCR_TXNCTR_Msk & ((value) << SPI_TNCR_TXNCTR_Pos)))

SPI_TNCR_TXNCTR_Msk

#define SPI_TNCR_TXNCTR_Msk

(SPI_TNCR) Transmit Counter Next

Definition component_spi.h:217

SPI_TNCR_TXNCTR_Pos

#define SPI_TNCR_TXNCTR_Pos

Definition component_spi.h:216

Definition at line 218 of file component_spi.h.

◆ SPI_TNCR_TXNCTR_Msk

#define SPI_TNCR_TXNCTR_Msk (0xffffu << SPI_TNCR_TXNCTR_Pos)

(SPI_TNCR) Transmit Counter Next

Definition at line 217 of file component_spi.h.

◆ SPI_TNCR_TXNCTR_Pos

#define SPI_TNCR_TXNCTR_Pos 0

Definition at line 216 of file component_spi.h.

◆ SPI_TNPR_TXNPTR

#define SPI_TNPR_TXNPTR ( value )

Value:

((SPI_TNPR_TXNPTR_Msk & ((value) << SPI_TNPR_TXNPTR_Pos)))

SPI_TNPR_TXNPTR_Msk

#define SPI_TNPR_TXNPTR_Msk

(SPI_TNPR) Transmit Next Pointer

Definition component_spi.h:213

SPI_TNPR_TXNPTR_Pos

#define SPI_TNPR_TXNPTR_Pos

Definition component_spi.h:212

Definition at line 214 of file component_spi.h.

◆ SPI_TNPR_TXNPTR_Msk

#define SPI_TNPR_TXNPTR_Msk (0xffffffffu << SPI_TNPR_TXNPTR_Pos)

(SPI_TNPR) Transmit Next Pointer

Definition at line 213 of file component_spi.h.

◆ SPI_TNPR_TXNPTR_Pos

#define SPI_TNPR_TXNPTR_Pos 0

Definition at line 212 of file component_spi.h.

◆ SPI_TPR_TXPTR

#define SPI_TPR_TXPTR ( value )

Value:

((SPI_TPR_TXPTR_Msk & ((value) << SPI_TPR_TXPTR_Pos)))

SPI_TPR_TXPTR_Msk

#define SPI_TPR_TXPTR_Msk

(SPI_TPR) Transmit Counter Register

Definition component_spi.h:197

SPI_TPR_TXPTR_Pos

#define SPI_TPR_TXPTR_Pos

Definition component_spi.h:196

Definition at line 198 of file component_spi.h.

◆ SPI_TPR_TXPTR_Msk

#define SPI_TPR_TXPTR_Msk (0xffffffffu << SPI_TPR_TXPTR_Pos)

(SPI_TPR) Transmit Counter Register

Definition at line 197 of file component_spi.h.

◆ SPI_TPR_TXPTR_Pos

#define SPI_TPR_TXPTR_Pos 0

Definition at line 196 of file component_spi.h.

◆ SPI_WPMR_WPEN

#define SPI_WPMR_WPEN (0x1u << 0)

(SPI_WPMR) Write Protect Enable

Definition at line 179 of file component_spi.h.

Referenced by spi_set_writeprotect().

◆ SPI_WPMR_WPKEY_Msk

#define SPI_WPMR_WPKEY_Msk (0xffffffu << SPI_WPMR_WPKEY_Pos)

(SPI_WPMR) Write Protect Key

Definition at line 181 of file component_spi.h.

◆ SPI_WPMR_WPKEY_PASSWD

#define SPI_WPMR_WPKEY_PASSWD (0x535049u << 8)

(SPI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.

Definition at line 182 of file component_spi.h.

◆ SPI_WPMR_WPKEY_Pos

#define SPI_WPMR_WPKEY_Pos 8

Definition at line 180 of file component_spi.h.

◆ SPI_WPSR_WPVS

#define SPI_WPSR_WPVS (0x1u << 0)

(SPI_WPSR) Write Protection Violation Status

Definition at line 184 of file component_spi.h.

◆ SPI_WPSR_WPVSRC_Msk

#define SPI_WPSR_WPVSRC_Msk (0xffu << SPI_WPSR_WPVSRC_Pos)

(SPI_WPSR) Write Protection Violation Source

Definition at line 186 of file component_spi.h.

◆ SPI_WPSR_WPVSRC_Pos

#define SPI_WPSR_WPVSRC_Pos 8

Definition at line 185 of file component_spi.h.

Data Structures

Macros

Detailed Description

Macro Definition Documentation

◆ SPI_CR_LASTXFER

◆ SPI_CR_SPIDIS

◆ SPI_CR_SPIEN

◆ SPI_CR_SWRST

◆ SPI_CSR_BITS_10_BIT

◆ SPI_CSR_BITS_11_BIT

◆ SPI_CSR_BITS_12_BIT

◆ SPI_CSR_BITS_13_BIT

◆ SPI_CSR_BITS_14_BIT

◆ SPI_CSR_BITS_15_BIT

◆ SPI_CSR_BITS_16_BIT

◆ SPI_CSR_BITS_8_BIT

◆ SPI_CSR_BITS_9_BIT

◆ SPI_CSR_BITS_Msk

◆ SPI_CSR_BITS_Pos

◆ SPI_CSR_CPOL

◆ SPI_CSR_CSAAT

◆ SPI_CSR_CSNAAT

◆ SPI_CSR_DLYBCT

◆ SPI_CSR_DLYBCT_Msk

◆ SPI_CSR_DLYBCT_Pos

◆ SPI_CSR_DLYBS

◆ SPI_CSR_DLYBS_Msk

◆ SPI_CSR_DLYBS_Pos

◆ SPI_CSR_NCPHA

◆ SPI_CSR_SCBR

◆ SPI_CSR_SCBR_Msk

◆ SPI_CSR_SCBR_Pos

◆ SPI_IDR_ENDRX

◆ SPI_IDR_ENDTX

◆ SPI_IDR_MODF

◆ SPI_IDR_NSSR

◆ SPI_IDR_OVRES

◆ SPI_IDR_RDRF

◆ SPI_IDR_RXBUFF

◆ SPI_IDR_TDRE

◆ SPI_IDR_TXBUFE

◆ SPI_IDR_TXEMPTY

◆ SPI_IDR_UNDES

◆ SPI_IER_ENDRX

◆ SPI_IER_ENDTX

◆ SPI_IER_MODF

◆ SPI_IER_NSSR

◆ SPI_IER_OVRES

◆ SPI_IER_RDRF

◆ SPI_IER_RXBUFF

◆ SPI_IER_TDRE

◆ SPI_IER_TXBUFE

◆ SPI_IER_TXEMPTY

◆ SPI_IER_UNDES

◆ SPI_IMR_ENDRX

◆ SPI_IMR_ENDTX

◆ SPI_IMR_MODF

◆ SPI_IMR_NSSR

◆ SPI_IMR_OVRES

◆ SPI_IMR_RDRF

◆ SPI_IMR_RXBUFF

◆ SPI_IMR_TDRE

◆ SPI_IMR_TXBUFE

◆ SPI_IMR_TXEMPTY

◆ SPI_IMR_UNDES

◆ SPI_MR_DLYBCS

◆ SPI_MR_DLYBCS_Msk

◆ SPI_MR_DLYBCS_Pos

◆ SPI_MR_LLB

◆ SPI_MR_MODFDIS

◆ SPI_MR_MSTR

◆ SPI_MR_PCS

◆ SPI_MR_PCS_Msk

◆ SPI_MR_PCS_Pos

◆ SPI_MR_PCSDEC

◆ SPI_MR_PS

◆ SPI_MR_WDRBT

◆ SPI_PTCR_RXTDIS

◆ SPI_PTCR_RXTEN

◆ SPI_PTCR_TXTDIS