Data Structures
struct	Pwm
struct	PwmCh_num
	PwmCh_num hardware registers. More...
struct	PwmCmp
	PwmCmp hardware registers. More...

Macros
#define	PWM_CCNT_CNT_Msk (0xffffffu << PWM_CCNT_CNT_Pos)
	(PWM_CCNT) Channel Counter Register
#define	PWM_CCNT_CNT_Pos 0
#define	PWM_CDTY_CDTY(value)
#define	PWM_CDTY_CDTY_Msk (0xffffffu << PWM_CDTY_CDTY_Pos)
	(PWM_CDTY) Channel Duty-Cycle
#define	PWM_CDTY_CDTY_Pos 0
#define	PWM_CDTYUPD_CDTYUPD(value)
#define	PWM_CDTYUPD_CDTYUPD_Msk (0xffffffu << PWM_CDTYUPD_CDTYUPD_Pos)
	(PWM_CDTYUPD) Channel Duty-Cycle Update
#define	PWM_CDTYUPD_CDTYUPD_Pos 0
#define	PWM_CLK_DIVA(value)
#define	PWM_CLK_DIVA_Msk (0xffu << PWM_CLK_DIVA_Pos)
	(PWM_CLK) CLKA, CLKB Divide Factor
#define	PWM_CLK_DIVA_Pos 0
#define	PWM_CLK_DIVB(value)
#define	PWM_CLK_DIVB_Msk (0xffu << PWM_CLK_DIVB_Pos)
	(PWM_CLK) CLKA, CLKB Divide Factor
#define	PWM_CLK_DIVB_Pos 16
#define	PWM_CLK_PREA(value)
#define	PWM_CLK_PREA_Msk (0xfu << PWM_CLK_PREA_Pos)
	(PWM_CLK) CLKA, CLKB Source Clock Selection
#define	PWM_CLK_PREA_Pos 8
#define	PWM_CLK_PREB(value)
#define	PWM_CLK_PREB_Msk (0xfu << PWM_CLK_PREB_Pos)
	(PWM_CLK) CLKA, CLKB Source Clock Selection
#define	PWM_CLK_PREB_Pos 24
#define	PWM_CMPM_CEN (0x1u << 0)
	(PWM_CMPM) Comparison x Enable
#define	PWM_CMPM_CPR(value)
#define	PWM_CMPM_CPR_Msk (0xfu << PWM_CMPM_CPR_Pos)
	(PWM_CMPM) Comparison x Period
#define	PWM_CMPM_CPR_Pos 8
#define	PWM_CMPM_CPRCNT(value)
#define	PWM_CMPM_CPRCNT_Msk (0xfu << PWM_CMPM_CPRCNT_Pos)
	(PWM_CMPM) Comparison x Period Counter
#define	PWM_CMPM_CPRCNT_Pos 12
#define	PWM_CMPM_CTR(value)
#define	PWM_CMPM_CTR_Msk (0xfu << PWM_CMPM_CTR_Pos)
	(PWM_CMPM) Comparison x Trigger
#define	PWM_CMPM_CTR_Pos 4
#define	PWM_CMPM_CUPR(value)
#define	PWM_CMPM_CUPR_Msk (0xfu << PWM_CMPM_CUPR_Pos)
	(PWM_CMPM) Comparison x Update Period
#define	PWM_CMPM_CUPR_Pos 16
#define	PWM_CMPM_CUPRCNT(value)
#define	PWM_CMPM_CUPRCNT_Msk (0xfu << PWM_CMPM_CUPRCNT_Pos)
	(PWM_CMPM) Comparison x Update Period Counter
#define	PWM_CMPM_CUPRCNT_Pos 20
#define	PWM_CMPMUPD_CENUPD (0x1u << 0)
	(PWM_CMPMUPD) Comparison x Enable Update
#define	PWM_CMPMUPD_CPRUPD(value)
#define	PWM_CMPMUPD_CPRUPD_Msk (0xfu << PWM_CMPMUPD_CPRUPD_Pos)
	(PWM_CMPMUPD) Comparison x Period Update
#define	PWM_CMPMUPD_CPRUPD_Pos 8
#define	PWM_CMPMUPD_CTRUPD(value)
#define	PWM_CMPMUPD_CTRUPD_Msk (0xfu << PWM_CMPMUPD_CTRUPD_Pos)
	(PWM_CMPMUPD) Comparison x Trigger Update
#define	PWM_CMPMUPD_CTRUPD_Pos 4
#define	PWM_CMPMUPD_CUPRUPD(value)
#define	PWM_CMPMUPD_CUPRUPD_Msk (0xfu << PWM_CMPMUPD_CUPRUPD_Pos)
	(PWM_CMPMUPD) Comparison x Update Period Update
#define	PWM_CMPMUPD_CUPRUPD_Pos 16
#define	PWM_CMPV_CV(value)
#define	PWM_CMPV_CV_Msk (0xffffffu << PWM_CMPV_CV_Pos)
	(PWM_CMPV) Comparison x Value
#define	PWM_CMPV_CV_Pos 0
#define	PWM_CMPV_CVM (0x1u << 24)
	(PWM_CMPV) Comparison x Value Mode
#define	PWM_CMPVUPD_CVMUPD (0x1u << 24)
	(PWM_CMPVUPD) Comparison x Value Mode Update
#define	PWM_CMPVUPD_CVUPD(value)
#define	PWM_CMPVUPD_CVUPD_Msk (0xffffffu << PWM_CMPVUPD_CVUPD_Pos)
	(PWM_CMPVUPD) Comparison x Value Update
#define	PWM_CMPVUPD_CVUPD_Pos 0
#define	PWM_CMR_CALG (0x1u << 8)
	(PWM_CMR) Channel Alignment
#define	PWM_CMR_CES (0x1u << 10)
	(PWM_CMR) Counter Event Selection
#define	PWM_CMR_CPOL (0x1u << 9)
	(PWM_CMR) Channel Polarity
#define	PWM_CMR_CPRE_CLKA (0xBu << 0)
	(PWM_CMR) Clock A
#define	PWM_CMR_CPRE_CLKB (0xCu << 0)
	(PWM_CMR) Clock B
#define	PWM_CMR_CPRE_MCK (0x0u << 0)
	(PWM_CMR) Master clock
#define	PWM_CMR_CPRE_MCK_DIV_1024 (0xAu << 0)
	(PWM_CMR) Master clock/1024
#define	PWM_CMR_CPRE_MCK_DIV_128 (0x7u << 0)
	(PWM_CMR) Master clock/128
#define	PWM_CMR_CPRE_MCK_DIV_16 (0x4u << 0)
	(PWM_CMR) Master clock/16
#define	PWM_CMR_CPRE_MCK_DIV_2 (0x1u << 0)
	(PWM_CMR) Master clock/2
#define	PWM_CMR_CPRE_MCK_DIV_256 (0x8u << 0)
	(PWM_CMR) Master clock/256
#define	PWM_CMR_CPRE_MCK_DIV_32 (0x5u << 0)
	(PWM_CMR) Master clock/32
#define	PWM_CMR_CPRE_MCK_DIV_4 (0x2u << 0)
	(PWM_CMR) Master clock/4
#define	PWM_CMR_CPRE_MCK_DIV_512 (0x9u << 0)
	(PWM_CMR) Master clock/512
#define	PWM_CMR_CPRE_MCK_DIV_64 (0x6u << 0)
	(PWM_CMR) Master clock/64
#define	PWM_CMR_CPRE_MCK_DIV_8 (0x3u << 0)
	(PWM_CMR) Master clock/8
#define	PWM_CMR_CPRE_Msk (0xfu << PWM_CMR_CPRE_Pos)
	(PWM_CMR) Channel Pre-scaler
#define	PWM_CMR_CPRE_Pos 0
#define	PWM_CMR_DTE (0x1u << 16)
	(PWM_CMR) Dead-Time Generator Enable
#define	PWM_CMR_DTHI (0x1u << 17)
	(PWM_CMR) Dead-Time PWMHx Output Inverted
#define	PWM_CMR_DTLI (0x1u << 18)
	(PWM_CMR) Dead-Time PWMLx Output Inverted
#define	PWM_CPRD_CPRD(value)
#define	PWM_CPRD_CPRD_Msk (0xffffffu << PWM_CPRD_CPRD_Pos)
	(PWM_CPRD) Channel Period
#define	PWM_CPRD_CPRD_Pos 0
#define	PWM_CPRDUPD_CPRDUPD(value)
#define	PWM_CPRDUPD_CPRDUPD_Msk (0xffffffu << PWM_CPRDUPD_CPRDUPD_Pos)
	(PWM_CPRDUPD) Channel Period Update
#define	PWM_CPRDUPD_CPRDUPD_Pos 0
#define	PWM_DIS_CHID0 (0x1u << 0)
	(PWM_DIS) Channel ID
#define	PWM_DIS_CHID1 (0x1u << 1)
	(PWM_DIS) Channel ID
#define	PWM_DIS_CHID2 (0x1u << 2)
	(PWM_DIS) Channel ID
#define	PWM_DIS_CHID3 (0x1u << 3)
	(PWM_DIS) Channel ID
#define	PWM_DT_DTH(value)
#define	PWM_DT_DTH_Msk (0xffffu << PWM_DT_DTH_Pos)
	(PWM_DT) Dead-Time Value for PWMHx Output
#define	PWM_DT_DTH_Pos 0
#define	PWM_DT_DTL(value)
#define	PWM_DT_DTL_Msk (0xffffu << PWM_DT_DTL_Pos)
	(PWM_DT) Dead-Time Value for PWMLx Output
#define	PWM_DT_DTL_Pos 16
#define	PWM_DTUPD_DTHUPD(value)
#define	PWM_DTUPD_DTHUPD_Msk (0xffffu << PWM_DTUPD_DTHUPD_Pos)
	(PWM_DTUPD) Dead-Time Value Update for PWMHx Output
#define	PWM_DTUPD_DTHUPD_Pos 0
#define	PWM_DTUPD_DTLUPD(value)
#define	PWM_DTUPD_DTLUPD_Msk (0xffffu << PWM_DTUPD_DTLUPD_Pos)
	(PWM_DTUPD) Dead-Time Value Update for PWMLx Output
#define	PWM_DTUPD_DTLUPD_Pos 16
#define	PWM_ELMR_CSEL0 (0x1u << 0)
	(PWM_ELMR[2]) Comparison 0 Selection
#define	PWM_ELMR_CSEL1 (0x1u << 1)
	(PWM_ELMR[2]) Comparison 1 Selection
#define	PWM_ELMR_CSEL2 (0x1u << 2)
	(PWM_ELMR[2]) Comparison 2 Selection
#define	PWM_ELMR_CSEL3 (0x1u << 3)
	(PWM_ELMR[2]) Comparison 3 Selection
#define	PWM_ELMR_CSEL4 (0x1u << 4)
	(PWM_ELMR[2]) Comparison 4 Selection
#define	PWM_ELMR_CSEL5 (0x1u << 5)
	(PWM_ELMR[2]) Comparison 5 Selection
#define	PWM_ELMR_CSEL6 (0x1u << 6)
	(PWM_ELMR[2]) Comparison 6 Selection
#define	PWM_ELMR_CSEL7 (0x1u << 7)
	(PWM_ELMR[2]) Comparison 7 Selection
#define	PWM_ENA_CHID0 (0x1u << 0)
	(PWM_ENA) Channel ID
#define	PWM_ENA_CHID1 (0x1u << 1)
	(PWM_ENA) Channel ID
#define	PWM_ENA_CHID2 (0x1u << 2)
	(PWM_ENA) Channel ID
#define	PWM_ENA_CHID3 (0x1u << 3)
	(PWM_ENA) Channel ID
#define	PWM_FCR_FCLR(value)
#define	PWM_FCR_FCLR_Msk (0xffu << PWM_FCR_FCLR_Pos)
	(PWM_FCR) Fault Clear
#define	PWM_FCR_FCLR_Pos 0
#define	PWM_FMR_FFIL(value)
#define	PWM_FMR_FFIL_Msk (0xffu << PWM_FMR_FFIL_Pos)
	(PWM_FMR) Fault Filtering
#define	PWM_FMR_FFIL_Pos 16
#define	PWM_FMR_FMOD(value)
#define	PWM_FMR_FMOD_Msk (0xffu << PWM_FMR_FMOD_Pos)
	(PWM_FMR) Fault Activation Mode
#define	PWM_FMR_FMOD_Pos 8
#define	PWM_FMR_FPOL(value)
#define	PWM_FMR_FPOL_Msk (0xffu << PWM_FMR_FPOL_Pos)
	(PWM_FMR) Fault Polarity
#define	PWM_FMR_FPOL_Pos 0
#define	PWM_FPE_FPE0(value)
#define	PWM_FPE_FPE0_Msk (0xffu << PWM_FPE_FPE0_Pos)
	(PWM_FPE) Fault Protection Enable for channel 0
#define	PWM_FPE_FPE0_Pos 0
#define	PWM_FPE_FPE1(value)
#define	PWM_FPE_FPE1_Msk (0xffu << PWM_FPE_FPE1_Pos)
	(PWM_FPE) Fault Protection Enable for channel 1
#define	PWM_FPE_FPE1_Pos 8
#define	PWM_FPE_FPE2(value)
#define	PWM_FPE_FPE2_Msk (0xffu << PWM_FPE_FPE2_Pos)
	(PWM_FPE) Fault Protection Enable for channel 2
#define	PWM_FPE_FPE2_Pos 16
#define	PWM_FPE_FPE3(value)
#define	PWM_FPE_FPE3_Msk (0xffu << PWM_FPE_FPE3_Pos)
	(PWM_FPE) Fault Protection Enable for channel 3
#define	PWM_FPE_FPE3_Pos 24
#define	PWM_FPV_FPVH0 (0x1u << 0)
	(PWM_FPV) Fault Protection Value for PWMH output on channel 0
#define	PWM_FPV_FPVH1 (0x1u << 1)
	(PWM_FPV) Fault Protection Value for PWMH output on channel 1
#define	PWM_FPV_FPVH2 (0x1u << 2)
	(PWM_FPV) Fault Protection Value for PWMH output on channel 2
#define	PWM_FPV_FPVH3 (0x1u << 3)
	(PWM_FPV) Fault Protection Value for PWMH output on channel 3
#define	PWM_FPV_FPVL0 (0x1u << 16)
	(PWM_FPV) Fault Protection Value for PWML output on channel 0
#define	PWM_FPV_FPVL1 (0x1u << 17)
	(PWM_FPV) Fault Protection Value for PWML output on channel 1
#define	PWM_FPV_FPVL2 (0x1u << 18)
	(PWM_FPV) Fault Protection Value for PWML output on channel 2
#define	PWM_FPV_FPVL3 (0x1u << 19)
	(PWM_FPV) Fault Protection Value for PWML output on channel 3
#define	PWM_FSR_FIV_Msk (0xffu << PWM_FSR_FIV_Pos)
	(PWM_FSR) Fault Input Value
#define	PWM_FSR_FIV_Pos 0
#define	PWM_FSR_FS_Msk (0xffu << PWM_FSR_FS_Pos)
	(PWM_FSR) Fault Status
#define	PWM_FSR_FS_Pos 8
#define	PWM_IDR1_CHID0 (0x1u << 0)
	(PWM_IDR1) Counter Event on Channel 0 Interrupt Disable
#define	PWM_IDR1_CHID1 (0x1u << 1)
	(PWM_IDR1) Counter Event on Channel 1 Interrupt Disable
#define	PWM_IDR1_CHID2 (0x1u << 2)
	(PWM_IDR1) Counter Event on Channel 2 Interrupt Disable
#define	PWM_IDR1_CHID3 (0x1u << 3)
	(PWM_IDR1) Counter Event on Channel 3 Interrupt Disable
#define	PWM_IDR1_FCHID0 (0x1u << 16)
	(PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable
#define	PWM_IDR1_FCHID1 (0x1u << 17)
	(PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable
#define	PWM_IDR1_FCHID2 (0x1u << 18)
	(PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable
#define	PWM_IDR1_FCHID3 (0x1u << 19)
	(PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable
#define	PWM_IDR2_CMPM0 (0x1u << 8)
	(PWM_IDR2) Comparison 0 Match Interrupt Disable
#define	PWM_IDR2_CMPM1 (0x1u << 9)
	(PWM_IDR2) Comparison 1 Match Interrupt Disable
#define	PWM_IDR2_CMPM2 (0x1u << 10)
	(PWM_IDR2) Comparison 2 Match Interrupt Disable
#define	PWM_IDR2_CMPM3 (0x1u << 11)
	(PWM_IDR2) Comparison 3 Match Interrupt Disable
#define	PWM_IDR2_CMPM4 (0x1u << 12)
	(PWM_IDR2) Comparison 4 Match Interrupt Disable
#define	PWM_IDR2_CMPM5 (0x1u << 13)
	(PWM_IDR2) Comparison 5 Match Interrupt Disable
#define	PWM_IDR2_CMPM6 (0x1u << 14)
	(PWM_IDR2) Comparison 6 Match Interrupt Disable
#define	PWM_IDR2_CMPM7 (0x1u << 15)
	(PWM_IDR2) Comparison 7 Match Interrupt Disable
#define	PWM_IDR2_CMPU0 (0x1u << 16)
	(PWM_IDR2) Comparison 0 Update Interrupt Disable
#define	PWM_IDR2_CMPU1 (0x1u << 17)
	(PWM_IDR2) Comparison 1 Update Interrupt Disable
#define	PWM_IDR2_CMPU2 (0x1u << 18)
	(PWM_IDR2) Comparison 2 Update Interrupt Disable
#define	PWM_IDR2_CMPU3 (0x1u << 19)
	(PWM_IDR2) Comparison 3 Update Interrupt Disable
#define	PWM_IDR2_CMPU4 (0x1u << 20)
	(PWM_IDR2) Comparison 4 Update Interrupt Disable
#define	PWM_IDR2_CMPU5 (0x1u << 21)
	(PWM_IDR2) Comparison 5 Update Interrupt Disable
#define	PWM_IDR2_CMPU6 (0x1u << 22)
	(PWM_IDR2) Comparison 6 Update Interrupt Disable
#define	PWM_IDR2_CMPU7 (0x1u << 23)
	(PWM_IDR2) Comparison 7 Update Interrupt Disable
#define	PWM_IDR2_ENDTX (0x1u << 1)
	(PWM_IDR2) PDC End of TX Buffer Interrupt Disable
#define	PWM_IDR2_TXBUFE (0x1u << 2)
	(PWM_IDR2) PDC TX Buffer Empty Interrupt Disable
#define	PWM_IDR2_UNRE (0x1u << 3)
	(PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable
#define	PWM_IDR2_WRDY (0x1u << 0)
	(PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable
#define	PWM_IER1_CHID0 (0x1u << 0)
	(PWM_IER1) Counter Event on Channel 0 Interrupt Enable
#define	PWM_IER1_CHID1 (0x1u << 1)
	(PWM_IER1) Counter Event on Channel 1 Interrupt Enable
#define	PWM_IER1_CHID2 (0x1u << 2)
	(PWM_IER1) Counter Event on Channel 2 Interrupt Enable
#define	PWM_IER1_CHID3 (0x1u << 3)
	(PWM_IER1) Counter Event on Channel 3 Interrupt Enable
#define	PWM_IER1_FCHID0 (0x1u << 16)
	(PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable
#define	PWM_IER1_FCHID1 (0x1u << 17)
	(PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable
#define	PWM_IER1_FCHID2 (0x1u << 18)
	(PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable
#define	PWM_IER1_FCHID3 (0x1u << 19)
	(PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable
#define	PWM_IER2_CMPM0 (0x1u << 8)
	(PWM_IER2) Comparison 0 Match Interrupt Enable
#define	PWM_IER2_CMPM1 (0x1u << 9)
	(PWM_IER2) Comparison 1 Match Interrupt Enable
#define	PWM_IER2_CMPM2 (0x1u << 10)
	(PWM_IER2) Comparison 2 Match Interrupt Enable
#define	PWM_IER2_CMPM3 (0x1u << 11)
	(PWM_IER2) Comparison 3 Match Interrupt Enable
#define	PWM_IER2_CMPM4 (0x1u << 12)
	(PWM_IER2) Comparison 4 Match Interrupt Enable
#define	PWM_IER2_CMPM5 (0x1u << 13)
	(PWM_IER2) Comparison 5 Match Interrupt Enable
#define	PWM_IER2_CMPM6 (0x1u << 14)
	(PWM_IER2) Comparison 6 Match Interrupt Enable
#define	PWM_IER2_CMPM7 (0x1u << 15)
	(PWM_IER2) Comparison 7 Match Interrupt Enable
#define	PWM_IER2_CMPU0 (0x1u << 16)
	(PWM_IER2) Comparison 0 Update Interrupt Enable
#define	PWM_IER2_CMPU1 (0x1u << 17)
	(PWM_IER2) Comparison 1 Update Interrupt Enable
#define	PWM_IER2_CMPU2 (0x1u << 18)
	(PWM_IER2) Comparison 2 Update Interrupt Enable
#define	PWM_IER2_CMPU3 (0x1u << 19)
	(PWM_IER2) Comparison 3 Update Interrupt Enable
#define	PWM_IER2_CMPU4 (0x1u << 20)
	(PWM_IER2) Comparison 4 Update Interrupt Enable
#define	PWM_IER2_CMPU5 (0x1u << 21)
	(PWM_IER2) Comparison 5 Update Interrupt Enable
#define	PWM_IER2_CMPU6 (0x1u << 22)
	(PWM_IER2) Comparison 6 Update Interrupt Enable
#define	PWM_IER2_CMPU7 (0x1u << 23)
	(PWM_IER2) Comparison 7 Update Interrupt Enable
#define	PWM_IER2_ENDTX (0x1u << 1)
	(PWM_IER2) PDC End of TX Buffer Interrupt Enable
#define	PWM_IER2_TXBUFE (0x1u << 2)
	(PWM_IER2) PDC TX Buffer Empty Interrupt Enable
#define	PWM_IER2_UNRE (0x1u << 3)
	(PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable
#define	PWM_IER2_WRDY (0x1u << 0)
	(PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable
#define	PWM_IMR1_CHID0 (0x1u << 0)
	(PWM_IMR1) Counter Event on Channel 0 Interrupt Mask
#define	PWM_IMR1_CHID1 (0x1u << 1)
	(PWM_IMR1) Counter Event on Channel 1 Interrupt Mask
#define	PWM_IMR1_CHID2 (0x1u << 2)
	(PWM_IMR1) Counter Event on Channel 2 Interrupt Mask
#define	PWM_IMR1_CHID3 (0x1u << 3)
	(PWM_IMR1) Counter Event on Channel 3 Interrupt Mask
#define	PWM_IMR1_FCHID0 (0x1u << 16)
	(PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask
#define	PWM_IMR1_FCHID1 (0x1u << 17)
	(PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask
#define	PWM_IMR1_FCHID2 (0x1u << 18)
	(PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask
#define	PWM_IMR1_FCHID3 (0x1u << 19)
	(PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask
#define	PWM_IMR2_CMPM0 (0x1u << 8)
	(PWM_IMR2) Comparison 0 Match Interrupt Mask
#define	PWM_IMR2_CMPM1 (0x1u << 9)
	(PWM_IMR2) Comparison 1 Match Interrupt Mask
#define	PWM_IMR2_CMPM2 (0x1u << 10)
	(PWM_IMR2) Comparison 2 Match Interrupt Mask
#define	PWM_IMR2_CMPM3 (0x1u << 11)
	(PWM_IMR2) Comparison 3 Match Interrupt Mask
#define	PWM_IMR2_CMPM4 (0x1u << 12)
	(PWM_IMR2) Comparison 4 Match Interrupt Mask
#define	PWM_IMR2_CMPM5 (0x1u << 13)
	(PWM_IMR2) Comparison 5 Match Interrupt Mask
#define	PWM_IMR2_CMPM6 (0x1u << 14)
	(PWM_IMR2) Comparison 6 Match Interrupt Mask
#define	PWM_IMR2_CMPM7 (0x1u << 15)
	(PWM_IMR2) Comparison 7 Match Interrupt Mask
#define	PWM_IMR2_CMPU0 (0x1u << 16)
	(PWM_IMR2) Comparison 0 Update Interrupt Mask
#define	PWM_IMR2_CMPU1 (0x1u << 17)
	(PWM_IMR2) Comparison 1 Update Interrupt Mask
#define	PWM_IMR2_CMPU2 (0x1u << 18)
	(PWM_IMR2) Comparison 2 Update Interrupt Mask
#define	PWM_IMR2_CMPU3 (0x1u << 19)
	(PWM_IMR2) Comparison 3 Update Interrupt Mask
#define	PWM_IMR2_CMPU4 (0x1u << 20)
	(PWM_IMR2) Comparison 4 Update Interrupt Mask
#define	PWM_IMR2_CMPU5 (0x1u << 21)
	(PWM_IMR2) Comparison 5 Update Interrupt Mask
#define	PWM_IMR2_CMPU6 (0x1u << 22)
	(PWM_IMR2) Comparison 6 Update Interrupt Mask
#define	PWM_IMR2_CMPU7 (0x1u << 23)
	(PWM_IMR2) Comparison 7 Update Interrupt Mask
#define	PWM_IMR2_ENDTX (0x1u << 1)
	(PWM_IMR2) PDC End of TX Buffer Interrupt Mask
#define	PWM_IMR2_TXBUFE (0x1u << 2)
	(PWM_IMR2) PDC TX Buffer Empty Interrupt Mask
#define	PWM_IMR2_UNRE (0x1u << 3)
	(PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask
#define	PWM_IMR2_WRDY (0x1u << 0)
	(PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask
#define	PWM_ISR1_CHID0 (0x1u << 0)
	(PWM_ISR1) Counter Event on Channel 0
#define	PWM_ISR1_CHID1 (0x1u << 1)
	(PWM_ISR1) Counter Event on Channel 1
#define	PWM_ISR1_CHID2 (0x1u << 2)
	(PWM_ISR1) Counter Event on Channel 2
#define	PWM_ISR1_CHID3 (0x1u << 3)
	(PWM_ISR1) Counter Event on Channel 3
#define	PWM_ISR1_FCHID0 (0x1u << 16)
	(PWM_ISR1) Fault Protection Trigger on Channel 0
#define	PWM_ISR1_FCHID1 (0x1u << 17)
	(PWM_ISR1) Fault Protection Trigger on Channel 1
#define	PWM_ISR1_FCHID2 (0x1u << 18)
	(PWM_ISR1) Fault Protection Trigger on Channel 2
#define	PWM_ISR1_FCHID3 (0x1u << 19)
	(PWM_ISR1) Fault Protection Trigger on Channel 3
#define	PWM_ISR2_CMPM0 (0x1u << 8)
	(PWM_ISR2) Comparison 0 Match
#define	PWM_ISR2_CMPM1 (0x1u << 9)
	(PWM_ISR2) Comparison 1 Match
#define	PWM_ISR2_CMPM2 (0x1u << 10)
	(PWM_ISR2) Comparison 2 Match
#define	PWM_ISR2_CMPM3 (0x1u << 11)
	(PWM_ISR2) Comparison 3 Match
#define	PWM_ISR2_CMPM4 (0x1u << 12)
	(PWM_ISR2) Comparison 4 Match
#define	PWM_ISR2_CMPM5 (0x1u << 13)
	(PWM_ISR2) Comparison 5 Match
#define	PWM_ISR2_CMPM6 (0x1u << 14)
	(PWM_ISR2) Comparison 6 Match
#define	PWM_ISR2_CMPM7 (0x1u << 15)
	(PWM_ISR2) Comparison 7 Match
#define	PWM_ISR2_CMPU0 (0x1u << 16)
	(PWM_ISR2) Comparison 0 Update
#define	PWM_ISR2_CMPU1 (0x1u << 17)
	(PWM_ISR2) Comparison 1 Update
#define	PWM_ISR2_CMPU2 (0x1u << 18)
	(PWM_ISR2) Comparison 2 Update
#define	PWM_ISR2_CMPU3 (0x1u << 19)
	(PWM_ISR2) Comparison 3 Update
#define	PWM_ISR2_CMPU4 (0x1u << 20)
	(PWM_ISR2) Comparison 4 Update
#define	PWM_ISR2_CMPU5 (0x1u << 21)
	(PWM_ISR2) Comparison 5 Update
#define	PWM_ISR2_CMPU6 (0x1u << 22)
	(PWM_ISR2) Comparison 6 Update
#define	PWM_ISR2_CMPU7 (0x1u << 23)
	(PWM_ISR2) Comparison 7 Update
#define	PWM_ISR2_ENDTX (0x1u << 1)
	(PWM_ISR2) PDC End of TX Buffer
#define	PWM_ISR2_TXBUFE (0x1u << 2)
	(PWM_ISR2) PDC TX Buffer Empty
#define	PWM_ISR2_UNRE (0x1u << 3)
	(PWM_ISR2) Synchronous Channels Update Underrun Error
#define	PWM_ISR2_WRDY (0x1u << 0)
	(PWM_ISR2) Write Ready for Synchronous Channels Update
#define	PWM_OOV_OOVH0 (0x1u << 0)
	(PWM_OOV) Output Override Value for PWMH output of the channel 0
#define	PWM_OOV_OOVH1 (0x1u << 1)
	(PWM_OOV) Output Override Value for PWMH output of the channel 1
#define	PWM_OOV_OOVH2 (0x1u << 2)
	(PWM_OOV) Output Override Value for PWMH output of the channel 2
#define	PWM_OOV_OOVH3 (0x1u << 3)
	(PWM_OOV) Output Override Value for PWMH output of the channel 3
#define	PWM_OOV_OOVL0 (0x1u << 16)
	(PWM_OOV) Output Override Value for PWML output of the channel 0
#define	PWM_OOV_OOVL1 (0x1u << 17)
	(PWM_OOV) Output Override Value for PWML output of the channel 1
#define	PWM_OOV_OOVL2 (0x1u << 18)
	(PWM_OOV) Output Override Value for PWML output of the channel 2
#define	PWM_OOV_OOVL3 (0x1u << 19)
	(PWM_OOV) Output Override Value for PWML output of the channel 3
#define	PWM_OS_OSH0 (0x1u << 0)
	(PWM_OS) Output Selection for PWMH output of the channel 0
#define	PWM_OS_OSH1 (0x1u << 1)
	(PWM_OS) Output Selection for PWMH output of the channel 1
#define	PWM_OS_OSH2 (0x1u << 2)
	(PWM_OS) Output Selection for PWMH output of the channel 2
#define	PWM_OS_OSH3 (0x1u << 3)
	(PWM_OS) Output Selection for PWMH output of the channel 3
#define	PWM_OS_OSL0 (0x1u << 16)
	(PWM_OS) Output Selection for PWML output of the channel 0
#define	PWM_OS_OSL1 (0x1u << 17)
	(PWM_OS) Output Selection for PWML output of the channel 1
#define	PWM_OS_OSL2 (0x1u << 18)
	(PWM_OS) Output Selection for PWML output of the channel 2
#define	PWM_OS_OSL3 (0x1u << 19)
	(PWM_OS) Output Selection for PWML output of the channel 3
#define	PWM_OSC_OSCH0 (0x1u << 0)
	(PWM_OSC) Output Selection Clear for PWMH output of the channel 0
#define	PWM_OSC_OSCH1 (0x1u << 1)
	(PWM_OSC) Output Selection Clear for PWMH output of the channel 1
#define	PWM_OSC_OSCH2 (0x1u << 2)
	(PWM_OSC) Output Selection Clear for PWMH output of the channel 2
#define	PWM_OSC_OSCH3 (0x1u << 3)
	(PWM_OSC) Output Selection Clear for PWMH output of the channel 3
#define	PWM_OSC_OSCL0 (0x1u << 16)
	(PWM_OSC) Output Selection Clear for PWML output of the channel 0
#define	PWM_OSC_OSCL1 (0x1u << 17)
	(PWM_OSC) Output Selection Clear for PWML output of the channel 1
#define	PWM_OSC_OSCL2 (0x1u << 18)
	(PWM_OSC) Output Selection Clear for PWML output of the channel 2
#define	PWM_OSC_OSCL3 (0x1u << 19)
	(PWM_OSC) Output Selection Clear for PWML output of the channel 3
#define	PWM_OSCUPD_OSCUPH0 (0x1u << 0)
	(PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0
#define	PWM_OSCUPD_OSCUPH1 (0x1u << 1)
	(PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1
#define	PWM_OSCUPD_OSCUPH2 (0x1u << 2)
	(PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2
#define	PWM_OSCUPD_OSCUPH3 (0x1u << 3)
	(PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3
#define	PWM_OSCUPD_OSCUPL0 (0x1u << 16)
	(PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0
#define	PWM_OSCUPD_OSCUPL1 (0x1u << 17)
	(PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1
#define	PWM_OSCUPD_OSCUPL2 (0x1u << 18)
	(PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2
#define	PWM_OSCUPD_OSCUPL3 (0x1u << 19)
	(PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3
#define	PWM_OSS_OSSH0 (0x1u << 0)
	(PWM_OSS) Output Selection Set for PWMH output of the channel 0
#define	PWM_OSS_OSSH1 (0x1u << 1)
	(PWM_OSS) Output Selection Set for PWMH output of the channel 1
#define	PWM_OSS_OSSH2 (0x1u << 2)
	(PWM_OSS) Output Selection Set for PWMH output of the channel 2
#define	PWM_OSS_OSSH3 (0x1u << 3)
	(PWM_OSS) Output Selection Set for PWMH output of the channel 3
#define	PWM_OSS_OSSL0 (0x1u << 16)
	(PWM_OSS) Output Selection Set for PWML output of the channel 0
#define	PWM_OSS_OSSL1 (0x1u << 17)
	(PWM_OSS) Output Selection Set for PWML output of the channel 1
#define	PWM_OSS_OSSL2 (0x1u << 18)
	(PWM_OSS) Output Selection Set for PWML output of the channel 2
#define	PWM_OSS_OSSL3 (0x1u << 19)
	(PWM_OSS) Output Selection Set for PWML output of the channel 3
#define	PWM_OSSUPD_OSSUPH0 (0x1u << 0)
	(PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0
#define	PWM_OSSUPD_OSSUPH1 (0x1u << 1)
	(PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1
#define	PWM_OSSUPD_OSSUPH2 (0x1u << 2)
	(PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2
#define	PWM_OSSUPD_OSSUPH3 (0x1u << 3)
	(PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3
#define	PWM_OSSUPD_OSSUPL0 (0x1u << 16)
	(PWM_OSSUPD) Output Selection Set for PWML output of the channel 0
#define	PWM_OSSUPD_OSSUPL1 (0x1u << 17)
	(PWM_OSSUPD) Output Selection Set for PWML output of the channel 1
#define	PWM_OSSUPD_OSSUPL2 (0x1u << 18)
	(PWM_OSSUPD) Output Selection Set for PWML output of the channel 2
#define	PWM_OSSUPD_OSSUPL3 (0x1u << 19)
	(PWM_OSSUPD) Output Selection Set for PWML output of the channel 3
#define	PWM_PTCR_RXTDIS (0x1u << 1)
	(PWM_PTCR) Receiver Transfer Disable
#define	PWM_PTCR_RXTEN (0x1u << 0)
	(PWM_PTCR) Receiver Transfer Enable
#define	PWM_PTCR_TXTDIS (0x1u << 9)
	(PWM_PTCR) Transmitter Transfer Disable
#define	PWM_PTCR_TXTEN (0x1u << 8)
	(PWM_PTCR) Transmitter Transfer Enable
#define	PWM_PTSR_RXTEN (0x1u << 0)
	(PWM_PTSR) Receiver Transfer Enable
#define	PWM_PTSR_TXTEN (0x1u << 8)
	(PWM_PTSR) Transmitter Transfer Enable
#define	PWM_SCM_PTRCS(value)
#define	PWM_SCM_PTRCS_Msk (0x7u << PWM_SCM_PTRCS_Pos)
	(PWM_SCM) PDC Transfer Request Comparison Selection
#define	PWM_SCM_PTRCS_Pos 21
#define	PWM_SCM_PTRM (0x1u << 20)
	(PWM_SCM) PDC Transfer Request Mode
#define	PWM_SCM_SYNC0 (0x1u << 0)
	(PWM_SCM) Synchronous Channel 0
#define	PWM_SCM_SYNC1 (0x1u << 1)
	(PWM_SCM) Synchronous Channel 1
#define	PWM_SCM_SYNC2 (0x1u << 2)
	(PWM_SCM) Synchronous Channel 2
#define	PWM_SCM_SYNC3 (0x1u << 3)
	(PWM_SCM) Synchronous Channel 3
#define	PWM_SCM_UPDM_MODE0 (0x0u << 16)
	(PWM_SCM) Manual write of double buffer registers and manual update of synchronous channels
#define	PWM_SCM_UPDM_MODE1 (0x1u << 16)
	(PWM_SCM) Manual write of double buffer registers and automatic update of synchronous channels
#define	PWM_SCM_UPDM_MODE2 (0x2u << 16)
	(PWM_SCM) Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous channels
#define	PWM_SCM_UPDM_Msk (0x3u << PWM_SCM_UPDM_Pos)
	(PWM_SCM) Synchronous Channels Update Mode
#define	PWM_SCM_UPDM_Pos 16
#define	PWM_SCUC_UPDULOCK (0x1u << 0)
	(PWM_SCUC) Synchronous Channels Update Unlock
#define	PWM_SCUP_UPR(value)
#define	PWM_SCUP_UPR_Msk (0xfu << PWM_SCUP_UPR_Pos)
	(PWM_SCUP) Update Period
#define	PWM_SCUP_UPR_Pos 0
#define	PWM_SCUP_UPRCNT(value)
#define	PWM_SCUP_UPRCNT_Msk (0xfu << PWM_SCUP_UPRCNT_Pos)
	(PWM_SCUP) Update Period Counter
#define	PWM_SCUP_UPRCNT_Pos 4
#define	PWM_SCUPUPD_UPRUPD(value)
#define	PWM_SCUPUPD_UPRUPD_Msk (0xfu << PWM_SCUPUPD_UPRUPD_Pos)
	(PWM_SCUPUPD) Update Period Update
#define	PWM_SCUPUPD_UPRUPD_Pos 0
#define	PWM_SMMR_DOWN0 (0x1u << 16)
	(PWM_SMMR) DOWN Count
#define	PWM_SMMR_DOWN1 (0x1u << 17)
	(PWM_SMMR) DOWN Count
#define	PWM_SMMR_GCEN0 (0x1u << 0)
	(PWM_SMMR) Gray Count ENable
#define	PWM_SMMR_GCEN1 (0x1u << 1)
	(PWM_SMMR) Gray Count ENable
#define	PWM_SR_CHID0 (0x1u << 0)
	(PWM_SR) Channel ID
#define	PWM_SR_CHID1 (0x1u << 1)
	(PWM_SR) Channel ID
#define	PWM_SR_CHID2 (0x1u << 2)
	(PWM_SR) Channel ID
#define	PWM_SR_CHID3 (0x1u << 3)
	(PWM_SR) Channel ID
#define	PWM_TCR_TXCTR(value)
#define	PWM_TCR_TXCTR_Msk (0xffffu << PWM_TCR_TXCTR_Pos)
	(PWM_TCR) Transmit Counter Register
#define	PWM_TCR_TXCTR_Pos 0
#define	PWM_TNCR_TXNCTR(value)
#define	PWM_TNCR_TXNCTR_Msk (0xffffu << PWM_TNCR_TXNCTR_Pos)
	(PWM_TNCR) Transmit Counter Next
#define	PWM_TNCR_TXNCTR_Pos 0
#define	PWM_TNPR_TXNPTR(value)
#define	PWM_TNPR_TXNPTR_Msk (0xffffffffu << PWM_TNPR_TXNPTR_Pos)
	(PWM_TNPR) Transmit Next Pointer
#define	PWM_TNPR_TXNPTR_Pos 0
#define	PWM_TPR_TXPTR(value)
#define	PWM_TPR_TXPTR_Msk (0xffffffffu << PWM_TPR_TXPTR_Pos)
	(PWM_TPR) Transmit Counter Register
#define	PWM_TPR_TXPTR_Pos 0
#define	PWM_WPCR_WPCMD_DISABLE_SW_PROT (0x0u << 0)
	(PWM_WPCR) Disable the Software Write Protect of the register groups of which the bit WPRGx is at '1'.
#define	PWM_WPCR_WPCMD_ENABLE_HW_PROT (0x2u << 0)
	(PWM_WPCR) Enable the Hardware Write Protect of the register groups of which the bit WPRGx is at '1'.
#define	PWM_WPCR_WPCMD_ENABLE_SW_PROT (0x1u << 0)
	(PWM_WPCR) Enable the Software Write Protect of the register groups of which the bit WPRGx is at '1'.
#define	PWM_WPCR_WPCMD_Msk (0x3u << PWM_WPCR_WPCMD_Pos)
	(PWM_WPCR) Write Protect Command
#define	PWM_WPCR_WPCMD_Pos 0
#define	PWM_WPCR_WPKEY_Msk (0xffffffu << PWM_WPCR_WPKEY_Pos)
	(PWM_WPCR) Write Protect Key
#define	PWM_WPCR_WPKEY_PASSWD (0x50574Du << 8)
	(PWM_WPCR) Writing any other value in this field aborts the write operation of the WPCMD field.Always reads as 0
#define	PWM_WPCR_WPKEY_Pos 8
#define	PWM_WPCR_WPRG0 (0x1u << 2)
	(PWM_WPCR) Write Protect Register Group 0
#define	PWM_WPCR_WPRG1 (0x1u << 3)
	(PWM_WPCR) Write Protect Register Group 1
#define	PWM_WPCR_WPRG2 (0x1u << 4)
	(PWM_WPCR) Write Protect Register Group 2
#define	PWM_WPCR_WPRG3 (0x1u << 5)
	(PWM_WPCR) Write Protect Register Group 3
#define	PWM_WPCR_WPRG4 (0x1u << 6)
	(PWM_WPCR) Write Protect Register Group 4
#define	PWM_WPCR_WPRG5 (0x1u << 7)
	(PWM_WPCR) Write Protect Register Group 5
#define	PWM_WPSR_WPHWS0 (0x1u << 8)
	(PWM_WPSR) Write Protect HW Status
#define	PWM_WPSR_WPHWS1 (0x1u << 9)
	(PWM_WPSR) Write Protect HW Status
#define	PWM_WPSR_WPHWS2 (0x1u << 10)
	(PWM_WPSR) Write Protect HW Status
#define	PWM_WPSR_WPHWS3 (0x1u << 11)
	(PWM_WPSR) Write Protect HW Status
#define	PWM_WPSR_WPHWS4 (0x1u << 12)
	(PWM_WPSR) Write Protect HW Status
#define	PWM_WPSR_WPHWS5 (0x1u << 13)
	(PWM_WPSR) Write Protect HW Status
#define	PWM_WPSR_WPSWS0 (0x1u << 0)
	(PWM_WPSR) Write Protect SW Status
#define	PWM_WPSR_WPSWS1 (0x1u << 1)
	(PWM_WPSR) Write Protect SW Status
#define	PWM_WPSR_WPSWS2 (0x1u << 2)
	(PWM_WPSR) Write Protect SW Status
#define	PWM_WPSR_WPSWS3 (0x1u << 3)
	(PWM_WPSR) Write Protect SW Status
#define	PWM_WPSR_WPSWS4 (0x1u << 4)
	(PWM_WPSR) Write Protect SW Status
#define	PWM_WPSR_WPSWS5 (0x1u << 5)
	(PWM_WPSR) Write Protect SW Status
#define	PWM_WPSR_WPVS (0x1u << 7)
	(PWM_WPSR) Write Protect Violation Status
#define	PWM_WPSR_WPVSRC_Msk (0xffffu << PWM_WPSR_WPVSRC_Pos)
	(PWM_WPSR) Write Protect Violation Source
#define	PWM_WPSR_WPVSRC_Pos 16
#define	PWMCH_NUM_NUMBER 4
#define	PWMCMP_NUMBER 8
	Pwm hardware registers.

Detailed Description

and its subsidiaries.

\cond ASF_LICENSE

Definition in file component_pwm.h.

Macro Definition Documentation

◆ PWM_CCNT_CNT_Msk

#define PWM_CCNT_CNT_Msk (0xffffffu << PWM_CCNT_CNT_Pos)

(PWM_CCNT) Channel Counter Register

Definition at line 533 of file component_pwm.h.

◆ PWM_CCNT_CNT_Pos

#define PWM_CCNT_CNT_Pos 0

Definition at line 532 of file component_pwm.h.

◆ PWM_CDTY_CDTY

#define PWM_CDTY_CDTY ( value )

Value:

((PWM_CDTY_CDTY_Msk & ((value) << PWM_CDTY_CDTY_Pos)))

PWM_CDTY_CDTY_Pos

#define PWM_CDTY_CDTY_Pos

Definition component_pwm.h:516

PWM_CDTY_CDTY_Msk

#define PWM_CDTY_CDTY_Msk

(PWM_CDTY) Channel Duty-Cycle

Definition component_pwm.h:517

Definition at line 518 of file component_pwm.h.

◆ PWM_CDTY_CDTY_Msk

#define PWM_CDTY_CDTY_Msk (0xffffffu << PWM_CDTY_CDTY_Pos)

(PWM_CDTY) Channel Duty-Cycle

Definition at line 517 of file component_pwm.h.

◆ PWM_CDTY_CDTY_Pos

#define PWM_CDTY_CDTY_Pos 0

Definition at line 516 of file component_pwm.h.

◆ PWM_CDTYUPD_CDTYUPD

#define PWM_CDTYUPD_CDTYUPD ( value )

Value:

((PWM_CDTYUPD_CDTYUPD_Msk & ((value) << PWM_CDTYUPD_CDTYUPD_Pos)))

PWM_CDTYUPD_CDTYUPD_Msk

#define PWM_CDTYUPD_CDTYUPD_Msk

(PWM_CDTYUPD) Channel Duty-Cycle Update

Definition component_pwm.h:521

PWM_CDTYUPD_CDTYUPD_Pos

#define PWM_CDTYUPD_CDTYUPD_Pos

Definition component_pwm.h:520

Definition at line 522 of file component_pwm.h.

◆ PWM_CDTYUPD_CDTYUPD_Msk

#define PWM_CDTYUPD_CDTYUPD_Msk (0xffffffu << PWM_CDTYUPD_CDTYUPD_Pos)

(PWM_CDTYUPD) Channel Duty-Cycle Update

Definition at line 521 of file component_pwm.h.

◆ PWM_CDTYUPD_CDTYUPD_Pos

#define PWM_CDTYUPD_CDTYUPD_Pos 0

Definition at line 520 of file component_pwm.h.

◆ PWM_CLK_DIVA

#define PWM_CLK_DIVA ( value )

Value:

((PWM_CLK_DIVA_Msk & ((value) << PWM_CLK_DIVA_Pos)))

PWM_CLK_DIVA_Msk

#define PWM_CLK_DIVA_Msk

(PWM_CLK) CLKA, CLKB Divide Factor

Definition component_pwm.h:118

PWM_CLK_DIVA_Pos

#define PWM_CLK_DIVA_Pos

Definition component_pwm.h:117

Definition at line 119 of file component_pwm.h.

◆ PWM_CLK_DIVA_Msk

#define PWM_CLK_DIVA_Msk (0xffu << PWM_CLK_DIVA_Pos)

(PWM_CLK) CLKA, CLKB Divide Factor

Definition at line 118 of file component_pwm.h.

◆ PWM_CLK_DIVA_Pos

#define PWM_CLK_DIVA_Pos 0

Definition at line 117 of file component_pwm.h.

◆ PWM_CLK_DIVB

#define PWM_CLK_DIVB ( value )

Value:

((PWM_CLK_DIVB_Msk & ((value) << PWM_CLK_DIVB_Pos)))

PWM_CLK_DIVB_Msk

#define PWM_CLK_DIVB_Msk

(PWM_CLK) CLKA, CLKB Divide Factor

Definition component_pwm.h:124

PWM_CLK_DIVB_Pos

#define PWM_CLK_DIVB_Pos

Definition component_pwm.h:123

Definition at line 125 of file component_pwm.h.

◆ PWM_CLK_DIVB_Msk

#define PWM_CLK_DIVB_Msk (0xffu << PWM_CLK_DIVB_Pos)

(PWM_CLK) CLKA, CLKB Divide Factor

Definition at line 124 of file component_pwm.h.

◆ PWM_CLK_DIVB_Pos

#define PWM_CLK_DIVB_Pos 16

Definition at line 123 of file component_pwm.h.

◆ PWM_CLK_PREA

#define PWM_CLK_PREA ( value )

Value:

((PWM_CLK_PREA_Msk & ((value) << PWM_CLK_PREA_Pos)))

PWM_CLK_PREA_Pos

#define PWM_CLK_PREA_Pos

Definition component_pwm.h:120

PWM_CLK_PREA_Msk

#define PWM_CLK_PREA_Msk

(PWM_CLK) CLKA, CLKB Source Clock Selection

Definition component_pwm.h:121

Definition at line 122 of file component_pwm.h.

◆ PWM_CLK_PREA_Msk

#define PWM_CLK_PREA_Msk (0xfu << PWM_CLK_PREA_Pos)

(PWM_CLK) CLKA, CLKB Source Clock Selection

Definition at line 121 of file component_pwm.h.

◆ PWM_CLK_PREA_Pos

#define PWM_CLK_PREA_Pos 8

Definition at line 120 of file component_pwm.h.

◆ PWM_CLK_PREB

#define PWM_CLK_PREB ( value )

Value:

((PWM_CLK_PREB_Msk & ((value) << PWM_CLK_PREB_Pos)))

PWM_CLK_PREB_Msk

#define PWM_CLK_PREB_Msk

(PWM_CLK) CLKA, CLKB Source Clock Selection

Definition component_pwm.h:127

PWM_CLK_PREB_Pos

#define PWM_CLK_PREB_Pos

Definition component_pwm.h:126

Definition at line 128 of file component_pwm.h.

◆ PWM_CLK_PREB_Msk

#define PWM_CLK_PREB_Msk (0xfu << PWM_CLK_PREB_Pos)

(PWM_CLK) CLKA, CLKB Source Clock Selection

Definition at line 127 of file component_pwm.h.

◆ PWM_CLK_PREB_Pos

#define PWM_CLK_PREB_Pos 24

Definition at line 126 of file component_pwm.h.

◆ PWM_CMPM_CEN

#define PWM_CMPM_CEN (0x1u << 0)

(PWM_CMPM) Comparison x Enable

Definition at line 466 of file component_pwm.h.

Referenced by pwm_cmp_change_setting(), and pwm_cmp_init().

◆ PWM_CMPM_CPR

#define PWM_CMPM_CPR ( value )

Value:

((PWM_CMPM_CPR_Msk & ((value) << PWM_CMPM_CPR_Pos)))

PWM_CMPM_CPR_Pos

#define PWM_CMPM_CPR_Pos

Definition component_pwm.h:470

PWM_CMPM_CPR_Msk

#define PWM_CMPM_CPR_Msk

(PWM_CMPM) Comparison x Period

Definition component_pwm.h:471

Definition at line 472 of file component_pwm.h.

Referenced by pwm_cmp_change_setting(), and pwm_cmp_init().

◆ PWM_CMPM_CPR_Msk

#define PWM_CMPM_CPR_Msk (0xfu << PWM_CMPM_CPR_Pos)

(PWM_CMPM) Comparison x Period

Definition at line 471 of file component_pwm.h.

◆ PWM_CMPM_CPR_Pos

#define PWM_CMPM_CPR_Pos 8

Definition at line 470 of file component_pwm.h.

◆ PWM_CMPM_CPRCNT

#define PWM_CMPM_CPRCNT ( value )

Value:

((PWM_CMPM_CPRCNT_Msk & ((value) << PWM_CMPM_CPRCNT_Pos)))

PWM_CMPM_CPRCNT_Msk

#define PWM_CMPM_CPRCNT_Msk

(PWM_CMPM) Comparison x Period Counter

Definition component_pwm.h:474

PWM_CMPM_CPRCNT_Pos

#define PWM_CMPM_CPRCNT_Pos

Definition component_pwm.h:473

Definition at line 475 of file component_pwm.h.

Referenced by pwm_cmp_get_period_counter().

◆ PWM_CMPM_CPRCNT_Msk

#define PWM_CMPM_CPRCNT_Msk (0xfu << PWM_CMPM_CPRCNT_Pos)

(PWM_CMPM) Comparison x Period Counter

Definition at line 474 of file component_pwm.h.

◆ PWM_CMPM_CPRCNT_Pos

#define PWM_CMPM_CPRCNT_Pos 12

Definition at line 473 of file component_pwm.h.

Referenced by pwm_cmp_get_period_counter().

◆ PWM_CMPM_CTR

#define PWM_CMPM_CTR ( value )

Value:

((PWM_CMPM_CTR_Msk & ((value) << PWM_CMPM_CTR_Pos)))

PWM_CMPM_CTR_Msk

#define PWM_CMPM_CTR_Msk

(PWM_CMPM) Comparison x Trigger

Definition component_pwm.h:468

PWM_CMPM_CTR_Pos

#define PWM_CMPM_CTR_Pos

Definition component_pwm.h:467

Definition at line 469 of file component_pwm.h.

Referenced by pwm_cmp_change_setting(), and pwm_cmp_init().

◆ PWM_CMPM_CTR_Msk

#define PWM_CMPM_CTR_Msk (0xfu << PWM_CMPM_CTR_Pos)

(PWM_CMPM) Comparison x Trigger

Definition at line 468 of file component_pwm.h.

◆ PWM_CMPM_CTR_Pos

#define PWM_CMPM_CTR_Pos 4

Definition at line 467 of file component_pwm.h.

◆ PWM_CMPM_CUPR

#define PWM_CMPM_CUPR ( value )

Value:

((PWM_CMPM_CUPR_Msk & ((value) << PWM_CMPM_CUPR_Pos)))

PWM_CMPM_CUPR_Pos

#define PWM_CMPM_CUPR_Pos

Definition component_pwm.h:476

PWM_CMPM_CUPR_Msk

#define PWM_CMPM_CUPR_Msk

(PWM_CMPM) Comparison x Update Period

Definition component_pwm.h:477

Definition at line 478 of file component_pwm.h.

Referenced by pwm_cmp_change_setting(), and pwm_cmp_init().

◆ PWM_CMPM_CUPR_Msk

#define PWM_CMPM_CUPR_Msk (0xfu << PWM_CMPM_CUPR_Pos)

(PWM_CMPM) Comparison x Update Period

Definition at line 477 of file component_pwm.h.

◆ PWM_CMPM_CUPR_Pos

#define PWM_CMPM_CUPR_Pos 16

Definition at line 476 of file component_pwm.h.

◆ PWM_CMPM_CUPRCNT

#define PWM_CMPM_CUPRCNT ( value )

Value:

((PWM_CMPM_CUPRCNT_Msk & ((value) << PWM_CMPM_CUPRCNT_Pos)))

PWM_CMPM_CUPRCNT_Pos

#define PWM_CMPM_CUPRCNT_Pos

Definition component_pwm.h:479

PWM_CMPM_CUPRCNT_Msk

#define PWM_CMPM_CUPRCNT_Msk

(PWM_CMPM) Comparison x Update Period Counter

Definition component_pwm.h:480

Definition at line 481 of file component_pwm.h.

Referenced by pwm_cmp_get_update_counter().

◆ PWM_CMPM_CUPRCNT_Msk

#define PWM_CMPM_CUPRCNT_Msk (0xfu << PWM_CMPM_CUPRCNT_Pos)

(PWM_CMPM) Comparison x Update Period Counter

Definition at line 480 of file component_pwm.h.

◆ PWM_CMPM_CUPRCNT_Pos

#define PWM_CMPM_CUPRCNT_Pos 20

Definition at line 479 of file component_pwm.h.

Referenced by pwm_cmp_get_update_counter().

◆ PWM_CMPMUPD_CENUPD

#define PWM_CMPMUPD_CENUPD (0x1u << 0)

(PWM_CMPMUPD) Comparison x Enable Update

Definition at line 483 of file component_pwm.h.

◆ PWM_CMPMUPD_CPRUPD

#define PWM_CMPMUPD_CPRUPD ( value )

Value:

((PWM_CMPMUPD_CPRUPD_Msk & ((value) << PWM_CMPMUPD_CPRUPD_Pos)))

PWM_CMPMUPD_CPRUPD_Pos

#define PWM_CMPMUPD_CPRUPD_Pos

Definition component_pwm.h:487

PWM_CMPMUPD_CPRUPD_Msk

#define PWM_CMPMUPD_CPRUPD_Msk

(PWM_CMPMUPD) Comparison x Period Update

Definition component_pwm.h:488

Definition at line 489 of file component_pwm.h.

◆ PWM_CMPMUPD_CPRUPD_Msk

#define PWM_CMPMUPD_CPRUPD_Msk (0xfu << PWM_CMPMUPD_CPRUPD_Pos)

(PWM_CMPMUPD) Comparison x Period Update

Definition at line 488 of file component_pwm.h.

◆ PWM_CMPMUPD_CPRUPD_Pos

#define PWM_CMPMUPD_CPRUPD_Pos 8

Definition at line 487 of file component_pwm.h.

◆ PWM_CMPMUPD_CTRUPD

#define PWM_CMPMUPD_CTRUPD ( value )

Value:

((PWM_CMPMUPD_CTRUPD_Msk & ((value) << PWM_CMPMUPD_CTRUPD_Pos)))

PWM_CMPMUPD_CTRUPD_Pos

#define PWM_CMPMUPD_CTRUPD_Pos

Definition component_pwm.h:484

PWM_CMPMUPD_CTRUPD_Msk

#define PWM_CMPMUPD_CTRUPD_Msk

(PWM_CMPMUPD) Comparison x Trigger Update

Definition component_pwm.h:485

Definition at line 486 of file component_pwm.h.

◆ PWM_CMPMUPD_CTRUPD_Msk

#define PWM_CMPMUPD_CTRUPD_Msk (0xfu << PWM_CMPMUPD_CTRUPD_Pos)

(PWM_CMPMUPD) Comparison x Trigger Update

Definition at line 485 of file component_pwm.h.

◆ PWM_CMPMUPD_CTRUPD_Pos

#define PWM_CMPMUPD_CTRUPD_Pos 4

Definition at line 484 of file component_pwm.h.

◆ PWM_CMPMUPD_CUPRUPD

#define PWM_CMPMUPD_CUPRUPD ( value )

Value:

((PWM_CMPMUPD_CUPRUPD_Msk & ((value) << PWM_CMPMUPD_CUPRUPD_Pos)))

PWM_CMPMUPD_CUPRUPD_Pos

#define PWM_CMPMUPD_CUPRUPD_Pos

Definition component_pwm.h:490

PWM_CMPMUPD_CUPRUPD_Msk

#define PWM_CMPMUPD_CUPRUPD_Msk

(PWM_CMPMUPD) Comparison x Update Period Update

Definition component_pwm.h:491

Definition at line 492 of file component_pwm.h.

◆ PWM_CMPMUPD_CUPRUPD_Msk

#define PWM_CMPMUPD_CUPRUPD_Msk (0xfu << PWM_CMPMUPD_CUPRUPD_Pos)

(PWM_CMPMUPD) Comparison x Update Period Update

Definition at line 491 of file component_pwm.h.

◆ PWM_CMPMUPD_CUPRUPD_Pos

#define PWM_CMPMUPD_CUPRUPD_Pos 16

Definition at line 490 of file component_pwm.h.

◆ PWM_CMPV_CV

#define PWM_CMPV_CV ( value )

Value:

((PWM_CMPV_CV_Msk & ((value) << PWM_CMPV_CV_Pos)))

PWM_CMPV_CV_Pos

#define PWM_CMPV_CV_Pos

Definition component_pwm.h:456

PWM_CMPV_CV_Msk

#define PWM_CMPV_CV_Msk

(PWM_CMPV) Comparison x Value

Definition component_pwm.h:457

Definition at line 458 of file component_pwm.h.

Referenced by pwm_cmp_change_setting(), and pwm_cmp_init().

◆ PWM_CMPV_CV_Msk

#define PWM_CMPV_CV_Msk (0xffffffu << PWM_CMPV_CV_Pos)

(PWM_CMPV) Comparison x Value

Definition at line 457 of file component_pwm.h.

◆ PWM_CMPV_CV_Pos

#define PWM_CMPV_CV_Pos 0

Definition at line 456 of file component_pwm.h.

◆ PWM_CMPV_CVM

#define PWM_CMPV_CVM (0x1u << 24)

(PWM_CMPV) Comparison x Value Mode

Definition at line 459 of file component_pwm.h.

◆ PWM_CMPVUPD_CVMUPD

#define PWM_CMPVUPD_CVMUPD (0x1u << 24)

(PWM_CMPVUPD) Comparison x Value Mode Update

Definition at line 464 of file component_pwm.h.

◆ PWM_CMPVUPD_CVUPD

#define PWM_CMPVUPD_CVUPD ( value )

Value:

((PWM_CMPVUPD_CVUPD_Msk & ((value) << PWM_CMPVUPD_CVUPD_Pos)))

PWM_CMPVUPD_CVUPD_Pos

#define PWM_CMPVUPD_CVUPD_Pos

Definition component_pwm.h:461

PWM_CMPVUPD_CVUPD_Msk

#define PWM_CMPVUPD_CVUPD_Msk

(PWM_CMPVUPD) Comparison x Value Update

Definition component_pwm.h:462

Definition at line 463 of file component_pwm.h.

◆ PWM_CMPVUPD_CVUPD_Msk

#define PWM_CMPVUPD_CVUPD_Msk (0xffffffu << PWM_CMPVUPD_CVUPD_Pos)

(PWM_CMPVUPD) Comparison x Value Update

Definition at line 462 of file component_pwm.h.

◆ PWM_CMPVUPD_CVUPD_Pos

#define PWM_CMPVUPD_CVUPD_Pos 0

Definition at line 461 of file component_pwm.h.

◆ PWM_CMR_CALG

#define PWM_CMR_CALG (0x1u << 8)

(PWM_CMR) Channel Alignment

Definition at line 509 of file component_pwm.h.

◆ PWM_CMR_CES

#define PWM_CMR_CES (0x1u << 10)

(PWM_CMR) Counter Event Selection

Definition at line 511 of file component_pwm.h.

◆ PWM_CMR_CPOL

#define PWM_CMR_CPOL (0x1u << 9)

(PWM_CMR) Channel Polarity

Definition at line 510 of file component_pwm.h.

◆ PWM_CMR_CPRE_CLKA

#define PWM_CMR_CPRE_CLKA (0xBu << 0)

(PWM_CMR) Clock A

Definition at line 507 of file component_pwm.h.

◆ PWM_CMR_CPRE_CLKB

#define PWM_CMR_CPRE_CLKB (0xCu << 0)

(PWM_CMR) Clock B

Definition at line 508 of file component_pwm.h.

◆ PWM_CMR_CPRE_MCK

#define PWM_CMR_CPRE_MCK (0x0u << 0)

(PWM_CMR) Master clock

Definition at line 496 of file component_pwm.h.

◆ PWM_CMR_CPRE_MCK_DIV_1024

#define PWM_CMR_CPRE_MCK_DIV_1024 (0xAu << 0)

(PWM_CMR) Master clock/1024

Definition at line 506 of file component_pwm.h.

◆ PWM_CMR_CPRE_MCK_DIV_128

#define PWM_CMR_CPRE_MCK_DIV_128 (0x7u << 0)

(PWM_CMR) Master clock/128

Definition at line 503 of file component_pwm.h.

◆ PWM_CMR_CPRE_MCK_DIV_16

#define PWM_CMR_CPRE_MCK_DIV_16 (0x4u << 0)

(PWM_CMR) Master clock/16

Definition at line 500 of file component_pwm.h.

◆ PWM_CMR_CPRE_MCK_DIV_2

#define PWM_CMR_CPRE_MCK_DIV_2 (0x1u << 0)

(PWM_CMR) Master clock/2

Definition at line 497 of file component_pwm.h.

◆ PWM_CMR_CPRE_MCK_DIV_256

#define PWM_CMR_CPRE_MCK_DIV_256 (0x8u << 0)

(PWM_CMR) Master clock/256

Definition at line 504 of file component_pwm.h.

◆ PWM_CMR_CPRE_MCK_DIV_32

#define PWM_CMR_CPRE_MCK_DIV_32 (0x5u << 0)

(PWM_CMR) Master clock/32

Definition at line 501 of file component_pwm.h.

◆ PWM_CMR_CPRE_MCK_DIV_4

#define PWM_CMR_CPRE_MCK_DIV_4 (0x2u << 0)

(PWM_CMR) Master clock/4

Definition at line 498 of file component_pwm.h.

◆ PWM_CMR_CPRE_MCK_DIV_512

#define PWM_CMR_CPRE_MCK_DIV_512 (0x9u << 0)

(PWM_CMR) Master clock/512

Definition at line 505 of file component_pwm.h.

◆ PWM_CMR_CPRE_MCK_DIV_64

#define PWM_CMR_CPRE_MCK_DIV_64 (0x6u << 0)

(PWM_CMR) Master clock/64

Definition at line 502 of file component_pwm.h.

◆ PWM_CMR_CPRE_MCK_DIV_8

#define PWM_CMR_CPRE_MCK_DIV_8 (0x3u << 0)

(PWM_CMR) Master clock/8

Definition at line 499 of file component_pwm.h.

◆ PWM_CMR_CPRE_Msk

#define PWM_CMR_CPRE_Msk (0xfu << PWM_CMR_CPRE_Pos)

(PWM_CMR) Channel Pre-scaler

Definition at line 495 of file component_pwm.h.

◆ PWM_CMR_CPRE_Pos

#define PWM_CMR_CPRE_Pos 0

Definition at line 494 of file component_pwm.h.

◆ PWM_CMR_DTE

#define PWM_CMR_DTE (0x1u << 16)

(PWM_CMR) Dead-Time Generator Enable

Definition at line 512 of file component_pwm.h.

◆ PWM_CMR_DTHI

#define PWM_CMR_DTHI (0x1u << 17)

(PWM_CMR) Dead-Time PWMHx Output Inverted

Definition at line 513 of file component_pwm.h.

◆ PWM_CMR_DTLI

#define PWM_CMR_DTLI (0x1u << 18)

(PWM_CMR) Dead-Time PWMLx Output Inverted

Definition at line 514 of file component_pwm.h.

◆ PWM_CPRD_CPRD

#define PWM_CPRD_CPRD ( value )

Value:

((PWM_CPRD_CPRD_Msk & ((value) << PWM_CPRD_CPRD_Pos)))

PWM_CPRD_CPRD_Pos

#define PWM_CPRD_CPRD_Pos

Definition component_pwm.h:524

PWM_CPRD_CPRD_Msk

#define PWM_CPRD_CPRD_Msk

(PWM_CPRD) Channel Period

Definition component_pwm.h:525

Definition at line 526 of file component_pwm.h.

◆ PWM_CPRD_CPRD_Msk

#define PWM_CPRD_CPRD_Msk (0xffffffu << PWM_CPRD_CPRD_Pos)

(PWM_CPRD) Channel Period

Definition at line 525 of file component_pwm.h.

◆ PWM_CPRD_CPRD_Pos

#define PWM_CPRD_CPRD_Pos 0

Definition at line 524 of file component_pwm.h.

◆ PWM_CPRDUPD_CPRDUPD

#define PWM_CPRDUPD_CPRDUPD ( value )

Value:

((PWM_CPRDUPD_CPRDUPD_Msk & ((value) << PWM_CPRDUPD_CPRDUPD_Pos)))

PWM_CPRDUPD_CPRDUPD_Msk

#define PWM_CPRDUPD_CPRDUPD_Msk

(PWM_CPRDUPD) Channel Period Update

Definition component_pwm.h:529

PWM_CPRDUPD_CPRDUPD_Pos

#define PWM_CPRDUPD_CPRDUPD_Pos

Definition component_pwm.h:528

Definition at line 530 of file component_pwm.h.

◆ PWM_CPRDUPD_CPRDUPD_Msk

#define PWM_CPRDUPD_CPRDUPD_Msk (0xffffffu << PWM_CPRDUPD_CPRDUPD_Pos)

(PWM_CPRDUPD) Channel Period Update

Definition at line 529 of file component_pwm.h.

◆ PWM_CPRDUPD_CPRDUPD_Pos

#define PWM_CPRDUPD_CPRDUPD_Pos 0

Definition at line 528 of file component_pwm.h.

◆ PWM_DIS_CHID0

#define PWM_DIS_CHID0 (0x1u << 0)

(PWM_DIS) Channel ID

Definition at line 135 of file component_pwm.h.

◆ PWM_DIS_CHID1

#define PWM_DIS_CHID1 (0x1u << 1)

(PWM_DIS) Channel ID

Definition at line 136 of file component_pwm.h.

◆ PWM_DIS_CHID2

#define PWM_DIS_CHID2 (0x1u << 2)

(PWM_DIS) Channel ID

Definition at line 137 of file component_pwm.h.

◆ PWM_DIS_CHID3

#define PWM_DIS_CHID3 (0x1u << 3)

(PWM_DIS) Channel ID

Definition at line 138 of file component_pwm.h.

◆ PWM_DT_DTH

#define PWM_DT_DTH ( value )

Value:

((PWM_DT_DTH_Msk & ((value) << PWM_DT_DTH_Pos)))

PWM_DT_DTH_Msk

#define PWM_DT_DTH_Msk

(PWM_DT) Dead-Time Value for PWMHx Output

Definition component_pwm.h:536

PWM_DT_DTH_Pos

#define PWM_DT_DTH_Pos

Definition component_pwm.h:535

Definition at line 537 of file component_pwm.h.

Referenced by pwm_channel_init().

◆ PWM_DT_DTH_Msk

#define PWM_DT_DTH_Msk (0xffffu << PWM_DT_DTH_Pos)

(PWM_DT) Dead-Time Value for PWMHx Output

Definition at line 536 of file component_pwm.h.

◆ PWM_DT_DTH_Pos

#define PWM_DT_DTH_Pos 0

Definition at line 535 of file component_pwm.h.

◆ PWM_DT_DTL

#define PWM_DT_DTL ( value )

Value:

((PWM_DT_DTL_Msk & ((value) << PWM_DT_DTL_Pos)))

PWM_DT_DTL_Pos

#define PWM_DT_DTL_Pos

Definition component_pwm.h:538

PWM_DT_DTL_Msk

#define PWM_DT_DTL_Msk

(PWM_DT) Dead-Time Value for PWMLx Output

Definition component_pwm.h:539

Definition at line 540 of file component_pwm.h.

Referenced by pwm_channel_init().

◆ PWM_DT_DTL_Msk

#define PWM_DT_DTL_Msk (0xffffu << PWM_DT_DTL_Pos)

(PWM_DT) Dead-Time Value for PWMLx Output

Definition at line 539 of file component_pwm.h.

◆ PWM_DT_DTL_Pos

#define PWM_DT_DTL_Pos 16

Definition at line 538 of file component_pwm.h.

◆ PWM_DTUPD_DTHUPD

#define PWM_DTUPD_DTHUPD ( value )

Value:

((PWM_DTUPD_DTHUPD_Msk & ((value) << PWM_DTUPD_DTHUPD_Pos)))

PWM_DTUPD_DTHUPD_Msk

#define PWM_DTUPD_DTHUPD_Msk

(PWM_DTUPD) Dead-Time Value Update for PWMHx Output

Definition component_pwm.h:543

PWM_DTUPD_DTHUPD_Pos

#define PWM_DTUPD_DTHUPD_Pos

Definition component_pwm.h:542

Definition at line 544 of file component_pwm.h.

Referenced by pwm_channel_update_dead_time().

◆ PWM_DTUPD_DTHUPD_Msk

#define PWM_DTUPD_DTHUPD_Msk (0xffffu << PWM_DTUPD_DTHUPD_Pos)

(PWM_DTUPD) Dead-Time Value Update for PWMHx Output

Definition at line 543 of file component_pwm.h.

◆ PWM_DTUPD_DTHUPD_Pos

#define PWM_DTUPD_DTHUPD_Pos 0

Definition at line 542 of file component_pwm.h.

◆ PWM_DTUPD_DTLUPD

#define PWM_DTUPD_DTLUPD ( value )

Value:

((PWM_DTUPD_DTLUPD_Msk & ((value) << PWM_DTUPD_DTLUPD_Pos)))

PWM_DTUPD_DTLUPD_Pos

#define PWM_DTUPD_DTLUPD_Pos

Definition component_pwm.h:545

PWM_DTUPD_DTLUPD_Msk

#define PWM_DTUPD_DTLUPD_Msk

(PWM_DTUPD) Dead-Time Value Update for PWMLx Output

Definition component_pwm.h:546

Definition at line 547 of file component_pwm.h.

Referenced by pwm_channel_update_dead_time().

◆ PWM_DTUPD_DTLUPD_Msk

#define PWM_DTUPD_DTLUPD_Msk (0xffffu << PWM_DTUPD_DTLUPD_Pos)

(PWM_DTUPD) Dead-Time Value Update for PWMLx Output

Definition at line 546 of file component_pwm.h.

◆ PWM_DTUPD_DTLUPD_Pos

#define PWM_DTUPD_DTLUPD_Pos 16

Definition at line 545 of file component_pwm.h.

◆ PWM_ELMR_CSEL0

#define PWM_ELMR_CSEL0 (0x1u << 0)

(PWM_ELMR[2]) Comparison 0 Selection

Definition at line 387 of file component_pwm.h.

◆ PWM_ELMR_CSEL1

#define PWM_ELMR_CSEL1 (0x1u << 1)

(PWM_ELMR[2]) Comparison 1 Selection

Definition at line 388 of file component_pwm.h.

◆ PWM_ELMR_CSEL2

#define PWM_ELMR_CSEL2 (0x1u << 2)

(PWM_ELMR[2]) Comparison 2 Selection

Definition at line 389 of file component_pwm.h.

◆ PWM_ELMR_CSEL3

#define PWM_ELMR_CSEL3 (0x1u << 3)

(PWM_ELMR[2]) Comparison 3 Selection

Definition at line 390 of file component_pwm.h.

◆ PWM_ELMR_CSEL4

#define PWM_ELMR_CSEL4 (0x1u << 4)

(PWM_ELMR[2]) Comparison 4 Selection

Definition at line 391 of file component_pwm.h.

◆ PWM_ELMR_CSEL5

#define PWM_ELMR_CSEL5 (0x1u << 5)

(PWM_ELMR[2]) Comparison 5 Selection

Definition at line 392 of file component_pwm.h.

◆ PWM_ELMR_CSEL6

#define PWM_ELMR_CSEL6 (0x1u << 6)

(PWM_ELMR[2]) Comparison 6 Selection

Definition at line 393 of file component_pwm.h.

◆ PWM_ELMR_CSEL7

#define PWM_ELMR_CSEL7 (0x1u << 7)

(PWM_ELMR[2]) Comparison 7 Selection

Definition at line 394 of file component_pwm.h.

◆ PWM_ENA_CHID0

#define PWM_ENA_CHID0 (0x1u << 0)

(PWM_ENA) Channel ID

Definition at line 130 of file component_pwm.h.

◆ PWM_ENA_CHID1

#define PWM_ENA_CHID1 (0x1u << 1)

(PWM_ENA) Channel ID

Definition at line 131 of file component_pwm.h.

◆ PWM_ENA_CHID2

#define PWM_ENA_CHID2 (0x1u << 2)

(PWM_ENA) Channel ID

Definition at line 132 of file component_pwm.h.

◆ PWM_ENA_CHID3

#define PWM_ENA_CHID3 (0x1u << 3)

(PWM_ENA) Channel ID

Definition at line 133 of file component_pwm.h.

◆ PWM_FCR_FCLR

#define PWM_FCR_FCLR ( value )

Value:

((PWM_FCR_FCLR_Msk & ((value) << PWM_FCR_FCLR_Pos)))

PWM_FCR_FCLR_Msk

#define PWM_FCR_FCLR_Msk

(PWM_FCR) Fault Clear

Definition component_pwm.h:362

PWM_FCR_FCLR_Pos

#define PWM_FCR_FCLR_Pos

Definition component_pwm.h:361

Definition at line 363 of file component_pwm.h.

◆ PWM_FCR_FCLR_Msk

#define PWM_FCR_FCLR_Msk (0xffu << PWM_FCR_FCLR_Pos)

(PWM_FCR) Fault Clear

Definition at line 362 of file component_pwm.h.

◆ PWM_FCR_FCLR_Pos

#define PWM_FCR_FCLR_Pos 0

Definition at line 361 of file component_pwm.h.

◆ PWM_FMR_FFIL

#define PWM_FMR_FFIL ( value )

Value:

((PWM_FMR_FFIL_Msk & ((value) << PWM_FMR_FFIL_Pos)))

PWM_FMR_FFIL_Pos

#define PWM_FMR_FFIL_Pos

Definition component_pwm.h:352

PWM_FMR_FFIL_Msk

#define PWM_FMR_FFIL_Msk

(PWM_FMR) Fault Filtering

Definition component_pwm.h:353

Definition at line 354 of file component_pwm.h.

◆ PWM_FMR_FFIL_Msk

#define PWM_FMR_FFIL_Msk (0xffu << PWM_FMR_FFIL_Pos)

(PWM_FMR) Fault Filtering

Definition at line 353 of file component_pwm.h.

◆ PWM_FMR_FFIL_Pos

#define PWM_FMR_FFIL_Pos 16

Definition at line 352 of file component_pwm.h.

◆ PWM_FMR_FMOD

#define PWM_FMR_FMOD ( value )

Value:

((PWM_FMR_FMOD_Msk & ((value) << PWM_FMR_FMOD_Pos)))

PWM_FMR_FMOD_Msk

#define PWM_FMR_FMOD_Msk

(PWM_FMR) Fault Activation Mode

Definition component_pwm.h:350

PWM_FMR_FMOD_Pos

#define PWM_FMR_FMOD_Pos

Definition component_pwm.h:349

Definition at line 351 of file component_pwm.h.

◆ PWM_FMR_FMOD_Msk

#define PWM_FMR_FMOD_Msk (0xffu << PWM_FMR_FMOD_Pos)

(PWM_FMR) Fault Activation Mode

Definition at line 350 of file component_pwm.h.

◆ PWM_FMR_FMOD_Pos

#define PWM_FMR_FMOD_Pos 8

Definition at line 349 of file component_pwm.h.

◆ PWM_FMR_FPOL

#define PWM_FMR_FPOL ( value )

Value:

((PWM_FMR_FPOL_Msk & ((value) << PWM_FMR_FPOL_Pos)))

PWM_FMR_FPOL_Msk

#define PWM_FMR_FPOL_Msk

(PWM_FMR) Fault Polarity

Definition component_pwm.h:347

PWM_FMR_FPOL_Pos

#define PWM_FMR_FPOL_Pos

Definition component_pwm.h:346

Definition at line 348 of file component_pwm.h.

◆ PWM_FMR_FPOL_Msk

#define PWM_FMR_FPOL_Msk (0xffu << PWM_FMR_FPOL_Pos)

(PWM_FMR) Fault Polarity

Definition at line 347 of file component_pwm.h.

◆ PWM_FMR_FPOL_Pos

#define PWM_FMR_FPOL_Pos 0

Definition at line 346 of file component_pwm.h.

◆ PWM_FPE_FPE0

#define PWM_FPE_FPE0 ( value )

Value:

((PWM_FPE_FPE0_Msk & ((value) << PWM_FPE_FPE0_Pos)))

PWM_FPE_FPE0_Pos

#define PWM_FPE_FPE0_Pos

Definition component_pwm.h:374

PWM_FPE_FPE0_Msk

#define PWM_FPE_FPE0_Msk

(PWM_FPE) Fault Protection Enable for channel 0

Definition component_pwm.h:375

Definition at line 376 of file component_pwm.h.

◆ PWM_FPE_FPE0_Msk

#define PWM_FPE_FPE0_Msk (0xffu << PWM_FPE_FPE0_Pos)

(PWM_FPE) Fault Protection Enable for channel 0

Definition at line 375 of file component_pwm.h.

◆ PWM_FPE_FPE0_Pos

#define PWM_FPE_FPE0_Pos 0

Definition at line 374 of file component_pwm.h.

◆ PWM_FPE_FPE1

#define PWM_FPE_FPE1 ( value )

Value:

((PWM_FPE_FPE1_Msk & ((value) << PWM_FPE_FPE1_Pos)))

PWM_FPE_FPE1_Msk

#define PWM_FPE_FPE1_Msk

(PWM_FPE) Fault Protection Enable for channel 1

Definition component_pwm.h:378

PWM_FPE_FPE1_Pos

#define PWM_FPE_FPE1_Pos

Definition component_pwm.h:377

Definition at line 379 of file component_pwm.h.

◆ PWM_FPE_FPE1_Msk

#define PWM_FPE_FPE1_Msk (0xffu << PWM_FPE_FPE1_Pos)

(PWM_FPE) Fault Protection Enable for channel 1

Definition at line 378 of file component_pwm.h.

◆ PWM_FPE_FPE1_Pos

#define PWM_FPE_FPE1_Pos 8

Definition at line 377 of file component_pwm.h.

◆ PWM_FPE_FPE2

#define PWM_FPE_FPE2 ( value )

Value:

((PWM_FPE_FPE2_Msk & ((value) << PWM_FPE_FPE2_Pos)))

PWM_FPE_FPE2_Pos

#define PWM_FPE_FPE2_Pos

Definition component_pwm.h:380

PWM_FPE_FPE2_Msk

#define PWM_FPE_FPE2_Msk

(PWM_FPE) Fault Protection Enable for channel 2

Definition component_pwm.h:381

Definition at line 382 of file component_pwm.h.

◆ PWM_FPE_FPE2_Msk

#define PWM_FPE_FPE2_Msk (0xffu << PWM_FPE_FPE2_Pos)

(PWM_FPE) Fault Protection Enable for channel 2

Definition at line 381 of file component_pwm.h.

◆ PWM_FPE_FPE2_Pos

#define PWM_FPE_FPE2_Pos 16

Definition at line 380 of file component_pwm.h.

◆ PWM_FPE_FPE3

#define PWM_FPE_FPE3 ( value )

Value:

((PWM_FPE_FPE3_Msk & ((value) << PWM_FPE_FPE3_Pos)))

PWM_FPE_FPE3_Pos

#define PWM_FPE_FPE3_Pos

Definition component_pwm.h:383

PWM_FPE_FPE3_Msk

#define PWM_FPE_FPE3_Msk

(PWM_FPE) Fault Protection Enable for channel 3

Definition component_pwm.h:384

Definition at line 385 of file component_pwm.h.

◆ PWM_FPE_FPE3_Msk

#define PWM_FPE_FPE3_Msk (0xffu << PWM_FPE_FPE3_Pos)

(PWM_FPE) Fault Protection Enable for channel 3

Definition at line 384 of file component_pwm.h.

◆ PWM_FPE_FPE3_Pos

#define PWM_FPE_FPE3_Pos 24

Definition at line 383 of file component_pwm.h.

◆ PWM_FPV_FPVH0

#define PWM_FPV_FPVH0 (0x1u << 0)

(PWM_FPV) Fault Protection Value for PWMH output on channel 0

Definition at line 365 of file component_pwm.h.

◆ PWM_FPV_FPVH1

#define PWM_FPV_FPVH1 (0x1u << 1)

(PWM_FPV) Fault Protection Value for PWMH output on channel 1

Definition at line 366 of file component_pwm.h.

◆ PWM_FPV_FPVH2

#define PWM_FPV_FPVH2 (0x1u << 2)

(PWM_FPV) Fault Protection Value for PWMH output on channel 2

Definition at line 367 of file component_pwm.h.

◆ PWM_FPV_FPVH3

#define PWM_FPV_FPVH3 (0x1u << 3)

(PWM_FPV) Fault Protection Value for PWMH output on channel 3

Definition at line 368 of file component_pwm.h.

◆ PWM_FPV_FPVL0

#define PWM_FPV_FPVL0 (0x1u << 16)

(PWM_FPV) Fault Protection Value for PWML output on channel 0

Definition at line 369 of file component_pwm.h.

◆ PWM_FPV_FPVL1

#define PWM_FPV_FPVL1 (0x1u << 17)

(PWM_FPV) Fault Protection Value for PWML output on channel 1

Definition at line 370 of file component_pwm.h.

◆ PWM_FPV_FPVL2

#define PWM_FPV_FPVL2 (0x1u << 18)

(PWM_FPV) Fault Protection Value for PWML output on channel 2

Definition at line 371 of file component_pwm.h.

◆ PWM_FPV_FPVL3

#define PWM_FPV_FPVL3 (0x1u << 19)

(PWM_FPV) Fault Protection Value for PWML output on channel 3

Definition at line 372 of file component_pwm.h.

◆ PWM_FSR_FIV_Msk

#define PWM_FSR_FIV_Msk (0xffu << PWM_FSR_FIV_Pos)

(PWM_FSR) Fault Input Value

Definition at line 357 of file component_pwm.h.

◆ PWM_FSR_FIV_Pos

#define PWM_FSR_FIV_Pos 0

Definition at line 356 of file component_pwm.h.

◆ PWM_FSR_FS_Msk

#define PWM_FSR_FS_Msk (0xffu << PWM_FSR_FS_Pos)

(PWM_FSR) Fault Status

Definition at line 359 of file component_pwm.h.

◆ PWM_FSR_FS_Pos

#define PWM_FSR_FS_Pos 8

Definition at line 358 of file component_pwm.h.

◆ PWM_IDR1_CHID0

#define PWM_IDR1_CHID0 (0x1u << 0)

(PWM_IDR1) Counter Event on Channel 0 Interrupt Disable

Definition at line 154 of file component_pwm.h.

◆ PWM_IDR1_CHID1

#define PWM_IDR1_CHID1 (0x1u << 1)

(PWM_IDR1) Counter Event on Channel 1 Interrupt Disable

Definition at line 155 of file component_pwm.h.

◆ PWM_IDR1_CHID2

#define PWM_IDR1_CHID2 (0x1u << 2)

(PWM_IDR1) Counter Event on Channel 2 Interrupt Disable

Definition at line 156 of file component_pwm.h.

◆ PWM_IDR1_CHID3

#define PWM_IDR1_CHID3 (0x1u << 3)

(PWM_IDR1) Counter Event on Channel 3 Interrupt Disable

Definition at line 157 of file component_pwm.h.

◆ PWM_IDR1_FCHID0

#define PWM_IDR1_FCHID0 (0x1u << 16)

(PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable

Definition at line 158 of file component_pwm.h.

◆ PWM_IDR1_FCHID1

#define PWM_IDR1_FCHID1 (0x1u << 17)

(PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable

Definition at line 159 of file component_pwm.h.

◆ PWM_IDR1_FCHID2

#define PWM_IDR1_FCHID2 (0x1u << 18)

(PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable

Definition at line 160 of file component_pwm.h.

◆ PWM_IDR1_FCHID3

#define PWM_IDR1_FCHID3 (0x1u << 19)

(PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable

Definition at line 161 of file component_pwm.h.

◆ PWM_IDR2_CMPM0

#define PWM_IDR2_CMPM0 (0x1u << 8)

(PWM_IDR2) Comparison 0 Match Interrupt Disable

Definition at line 233 of file component_pwm.h.

◆ PWM_IDR2_CMPM1

#define PWM_IDR2_CMPM1 (0x1u << 9)

(PWM_IDR2) Comparison 1 Match Interrupt Disable

Definition at line 234 of file component_pwm.h.

◆ PWM_IDR2_CMPM2

#define PWM_IDR2_CMPM2 (0x1u << 10)

(PWM_IDR2) Comparison 2 Match Interrupt Disable

Definition at line 235 of file component_pwm.h.

◆ PWM_IDR2_CMPM3

#define PWM_IDR2_CMPM3 (0x1u << 11)

(PWM_IDR2) Comparison 3 Match Interrupt Disable

Definition at line 236 of file component_pwm.h.

◆ PWM_IDR2_CMPM4

#define PWM_IDR2_CMPM4 (0x1u << 12)

(PWM_IDR2) Comparison 4 Match Interrupt Disable

Definition at line 237 of file component_pwm.h.

◆ PWM_IDR2_CMPM5

#define PWM_IDR2_CMPM5 (0x1u << 13)

(PWM_IDR2) Comparison 5 Match Interrupt Disable

Definition at line 238 of file component_pwm.h.

◆ PWM_IDR2_CMPM6

#define PWM_IDR2_CMPM6 (0x1u << 14)

(PWM_IDR2) Comparison 6 Match Interrupt Disable

Definition at line 239 of file component_pwm.h.

◆ PWM_IDR2_CMPM7

#define PWM_IDR2_CMPM7 (0x1u << 15)

(PWM_IDR2) Comparison 7 Match Interrupt Disable

Definition at line 240 of file component_pwm.h.

◆ PWM_IDR2_CMPU0

#define PWM_IDR2_CMPU0 (0x1u << 16)

(PWM_IDR2) Comparison 0 Update Interrupt Disable

Definition at line 241 of file component_pwm.h.

◆ PWM_IDR2_CMPU1

#define PWM_IDR2_CMPU1 (0x1u << 17)

(PWM_IDR2) Comparison 1 Update Interrupt Disable

Definition at line 242 of file component_pwm.h.

◆ PWM_IDR2_CMPU2

#define PWM_IDR2_CMPU2 (0x1u << 18)

(PWM_IDR2) Comparison 2 Update Interrupt Disable

Definition at line 243 of file component_pwm.h.

◆ PWM_IDR2_CMPU3

#define PWM_IDR2_CMPU3 (0x1u << 19)

(PWM_IDR2) Comparison 3 Update Interrupt Disable

Definition at line 244 of file component_pwm.h.

◆ PWM_IDR2_CMPU4

#define PWM_IDR2_CMPU4 (0x1u << 20)

(PWM_IDR2) Comparison 4 Update Interrupt Disable

Definition at line 245 of file component_pwm.h.

◆ PWM_IDR2_CMPU5

#define PWM_IDR2_CMPU5 (0x1u << 21)

(PWM_IDR2) Comparison 5 Update Interrupt Disable

Definition at line 246 of file component_pwm.h.

◆ PWM_IDR2_CMPU6

#define PWM_IDR2_CMPU6 (0x1u << 22)

(PWM_IDR2) Comparison 6 Update Interrupt Disable

Definition at line 247 of file component_pwm.h.

◆ PWM_IDR2_CMPU7

#define PWM_IDR2_CMPU7 (0x1u << 23)

(PWM_IDR2) Comparison 7 Update Interrupt Disable

Definition at line 248 of file component_pwm.h.

◆ PWM_IDR2_ENDTX

#define PWM_IDR2_ENDTX (0x1u << 1)

(PWM_IDR2) PDC End of TX Buffer Interrupt Disable

Definition at line 230 of file component_pwm.h.

◆ PWM_IDR2_TXBUFE

#define PWM_IDR2_TXBUFE (0x1u << 2)

(PWM_IDR2) PDC TX Buffer Empty Interrupt Disable

Definition at line 231 of file component_pwm.h.

◆ PWM_IDR2_UNRE

#define PWM_IDR2_UNRE (0x1u << 3)

(PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable

Definition at line 232 of file component_pwm.h.

◆ PWM_IDR2_WRDY

#define PWM_IDR2_WRDY (0x1u << 0)

(PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable

Definition at line 229 of file component_pwm.h.

◆ PWM_IER1_CHID0

#define PWM_IER1_CHID0 (0x1u << 0)

(PWM_IER1) Counter Event on Channel 0 Interrupt Enable

Definition at line 145 of file component_pwm.h.

◆ PWM_IER1_CHID1

#define PWM_IER1_CHID1 (0x1u << 1)

(PWM_IER1) Counter Event on Channel 1 Interrupt Enable

Definition at line 146 of file component_pwm.h.

◆ PWM_IER1_CHID2

#define PWM_IER1_CHID2 (0x1u << 2)

(PWM_IER1) Counter Event on Channel 2 Interrupt Enable

Definition at line 147 of file component_pwm.h.

◆ PWM_IER1_CHID3

#define PWM_IER1_CHID3 (0x1u << 3)

(PWM_IER1) Counter Event on Channel 3 Interrupt Enable

Definition at line 148 of file component_pwm.h.

◆ PWM_IER1_FCHID0

#define PWM_IER1_FCHID0 (0x1u << 16)

(PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable

Definition at line 149 of file component_pwm.h.

◆ PWM_IER1_FCHID1

#define PWM_IER1_FCHID1 (0x1u << 17)

(PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable

Definition at line 150 of file component_pwm.h.

◆ PWM_IER1_FCHID2

#define PWM_IER1_FCHID2 (0x1u << 18)

(PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable

Definition at line 151 of file component_pwm.h.

◆ PWM_IER1_FCHID3

#define PWM_IER1_FCHID3 (0x1u << 19)

(PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable

Definition at line 152 of file component_pwm.h.

◆ PWM_IER2_CMPM0

#define PWM_IER2_CMPM0 (0x1u << 8)

(PWM_IER2) Comparison 0 Match Interrupt Enable

Definition at line 212 of file component_pwm.h.

◆ PWM_IER2_CMPM1

#define PWM_IER2_CMPM1 (0x1u << 9)

(PWM_IER2) Comparison 1 Match Interrupt Enable

Definition at line 213 of file component_pwm.h.

◆ PWM_IER2_CMPM2

#define PWM_IER2_CMPM2 (0x1u << 10)

(PWM_IER2) Comparison 2 Match Interrupt Enable

Definition at line 214 of file component_pwm.h.

◆ PWM_IER2_CMPM3

#define PWM_IER2_CMPM3 (0x1u << 11)

(PWM_IER2) Comparison 3 Match Interrupt Enable

Definition at line 215 of file component_pwm.h.

◆ PWM_IER2_CMPM4

#define PWM_IER2_CMPM4 (0x1u << 12)

(PWM_IER2) Comparison 4 Match Interrupt Enable

Definition at line 216 of file component_pwm.h.

◆ PWM_IER2_CMPM5

#define PWM_IER2_CMPM5 (0x1u << 13)

(PWM_IER2) Comparison 5 Match Interrupt Enable

Definition at line 217 of file component_pwm.h.

◆ PWM_IER2_CMPM6

#define PWM_IER2_CMPM6 (0x1u << 14)

(PWM_IER2) Comparison 6 Match Interrupt Enable

Definition at line 218 of file component_pwm.h.

◆ PWM_IER2_CMPM7

#define PWM_IER2_CMPM7 (0x1u << 15)

(PWM_IER2) Comparison 7 Match Interrupt Enable

Definition at line 219 of file component_pwm.h.

◆ PWM_IER2_CMPU0

#define PWM_IER2_CMPU0 (0x1u << 16)

(PWM_IER2) Comparison 0 Update Interrupt Enable

Definition at line 220 of file component_pwm.h.

◆ PWM_IER2_CMPU1

#define PWM_IER2_CMPU1 (0x1u << 17)

(PWM_IER2) Comparison 1 Update Interrupt Enable

Definition at line 221 of file component_pwm.h.

◆ PWM_IER2_CMPU2

#define PWM_IER2_CMPU2 (0x1u << 18)

(PWM_IER2) Comparison 2 Update Interrupt Enable

Definition at line 222 of file component_pwm.h.

◆ PWM_IER2_CMPU3

#define PWM_IER2_CMPU3 (0x1u << 19)

(PWM_IER2) Comparison 3 Update Interrupt Enable

Definition at line 223 of file component_pwm.h.

◆ PWM_IER2_CMPU4

#define PWM_IER2_CMPU4 (0x1u << 20)

(PWM_IER2) Comparison 4 Update Interrupt Enable

Definition at line 224 of file component_pwm.h.

◆ PWM_IER2_CMPU5

#define PWM_IER2_CMPU5 (0x1u << 21)

(PWM_IER2) Comparison 5 Update Interrupt Enable

Definition at line 225 of file component_pwm.h.

◆ PWM_IER2_CMPU6

#define PWM_IER2_CMPU6 (0x1u << 22)

(PWM_IER2) Comparison 6 Update Interrupt Enable

Definition at line 226 of file component_pwm.h.

◆ PWM_IER2_CMPU7

#define PWM_IER2_CMPU7 (0x1u << 23)

(PWM_IER2) Comparison 7 Update Interrupt Enable

Definition at line 227 of file component_pwm.h.

◆ PWM_IER2_ENDTX

#define PWM_IER2_ENDTX (0x1u << 1)

(PWM_IER2) PDC End of TX Buffer Interrupt Enable

Definition at line 209 of file component_pwm.h.

◆ PWM_IER2_TXBUFE

#define PWM_IER2_TXBUFE (0x1u << 2)

(PWM_IER2) PDC TX Buffer Empty Interrupt Enable

Definition at line 210 of file component_pwm.h.

◆ PWM_IER2_UNRE

#define PWM_IER2_UNRE (0x1u << 3)

(PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable

Definition at line 211 of file component_pwm.h.

◆ PWM_IER2_WRDY

#define PWM_IER2_WRDY (0x1u << 0)

(PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable

Definition at line 208 of file component_pwm.h.

◆ PWM_IMR1_CHID0

#define PWM_IMR1_CHID0 (0x1u << 0)

(PWM_IMR1) Counter Event on Channel 0 Interrupt Mask

Definition at line 163 of file component_pwm.h.

◆ PWM_IMR1_CHID1

#define PWM_IMR1_CHID1 (0x1u << 1)

(PWM_IMR1) Counter Event on Channel 1 Interrupt Mask

Definition at line 164 of file component_pwm.h.

◆ PWM_IMR1_CHID2

#define PWM_IMR1_CHID2 (0x1u << 2)

(PWM_IMR1) Counter Event on Channel 2 Interrupt Mask

Definition at line 165 of file component_pwm.h.

◆ PWM_IMR1_CHID3

#define PWM_IMR1_CHID3 (0x1u << 3)

(PWM_IMR1) Counter Event on Channel 3 Interrupt Mask

Definition at line 166 of file component_pwm.h.

◆ PWM_IMR1_FCHID0

#define PWM_IMR1_FCHID0 (0x1u << 16)

(PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask

Definition at line 167 of file component_pwm.h.

◆ PWM_IMR1_FCHID1

#define PWM_IMR1_FCHID1 (0x1u << 17)

(PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask

Definition at line 168 of file component_pwm.h.

◆ PWM_IMR1_FCHID2

#define PWM_IMR1_FCHID2 (0x1u << 18)

(PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask

Definition at line 169 of file component_pwm.h.

◆ PWM_IMR1_FCHID3

#define PWM_IMR1_FCHID3 (0x1u << 19)

(PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask

Definition at line 170 of file component_pwm.h.

◆ PWM_IMR2_CMPM0

#define PWM_IMR2_CMPM0 (0x1u << 8)

(PWM_IMR2) Comparison 0 Match Interrupt Mask

Definition at line 254 of file component_pwm.h.

◆ PWM_IMR2_CMPM1

#define PWM_IMR2_CMPM1 (0x1u << 9)

(PWM_IMR2) Comparison 1 Match Interrupt Mask

Definition at line 255 of file component_pwm.h.

◆ PWM_IMR2_CMPM2

#define PWM_IMR2_CMPM2 (0x1u << 10)

(PWM_IMR2) Comparison 2 Match Interrupt Mask

Definition at line 256 of file component_pwm.h.

◆ PWM_IMR2_CMPM3

#define PWM_IMR2_CMPM3 (0x1u << 11)

(PWM_IMR2) Comparison 3 Match Interrupt Mask

Definition at line 257 of file component_pwm.h.

◆ PWM_IMR2_CMPM4

#define PWM_IMR2_CMPM4 (0x1u << 12)

(PWM_IMR2) Comparison 4 Match Interrupt Mask

Definition at line 258 of file component_pwm.h.

◆ PWM_IMR2_CMPM5

#define PWM_IMR2_CMPM5 (0x1u << 13)

(PWM_IMR2) Comparison 5 Match Interrupt Mask

Definition at line 259 of file component_pwm.h.

◆ PWM_IMR2_CMPM6

#define PWM_IMR2_CMPM6 (0x1u << 14)

(PWM_IMR2) Comparison 6 Match Interrupt Mask

Definition at line 260 of file component_pwm.h.

◆ PWM_IMR2_CMPM7

#define PWM_IMR2_CMPM7 (0x1u << 15)

(PWM_IMR2) Comparison 7 Match Interrupt Mask

Definition at line 261 of file component_pwm.h.

◆ PWM_IMR2_CMPU0

#define PWM_IMR2_CMPU0 (0x1u << 16)

(PWM_IMR2) Comparison 0 Update Interrupt Mask

Definition at line 262 of file component_pwm.h.

◆ PWM_IMR2_CMPU1

#define PWM_IMR2_CMPU1 (0x1u << 17)

(PWM_IMR2) Comparison 1 Update Interrupt Mask

Definition at line 263 of file component_pwm.h.

◆ PWM_IMR2_CMPU2

#define PWM_IMR2_CMPU2 (0x1u << 18)

(PWM_IMR2) Comparison 2 Update Interrupt Mask

Definition at line 264 of file component_pwm.h.

◆ PWM_IMR2_CMPU3

#define PWM_IMR2_CMPU3 (0x1u << 19)

(PWM_IMR2) Comparison 3 Update Interrupt Mask

Definition at line 265 of file component_pwm.h.

◆ PWM_IMR2_CMPU4

#define PWM_IMR2_CMPU4 (0x1u << 20)

(PWM_IMR2) Comparison 4 Update Interrupt Mask

Definition at line 266 of file component_pwm.h.

◆ PWM_IMR2_CMPU5

#define PWM_IMR2_CMPU5 (0x1u << 21)

(PWM_IMR2) Comparison 5 Update Interrupt Mask

Definition at line 267 of file component_pwm.h.

◆ PWM_IMR2_CMPU6

#define PWM_IMR2_CMPU6 (0x1u << 22)

(PWM_IMR2) Comparison 6 Update Interrupt Mask

Definition at line 268 of file component_pwm.h.

◆ PWM_IMR2_CMPU7

#define PWM_IMR2_CMPU7 (0x1u << 23)

(PWM_IMR2) Comparison 7 Update Interrupt Mask

Definition at line 269 of file component_pwm.h.

◆ PWM_IMR2_ENDTX

#define PWM_IMR2_ENDTX (0x1u << 1)

(PWM_IMR2) PDC End of TX Buffer Interrupt Mask

Definition at line 251 of file component_pwm.h.

◆ PWM_IMR2_TXBUFE

#define PWM_IMR2_TXBUFE (0x1u << 2)

(PWM_IMR2) PDC TX Buffer Empty Interrupt Mask

Definition at line 252 of file component_pwm.h.

◆ PWM_IMR2_UNRE

#define PWM_IMR2_UNRE (0x1u << 3)

(PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask

Definition at line 253 of file component_pwm.h.

◆ PWM_IMR2_WRDY

#define PWM_IMR2_WRDY (0x1u << 0)

(PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask

Definition at line 250 of file component_pwm.h.

◆ PWM_ISR1_CHID0

#define PWM_ISR1_CHID0 (0x1u << 0)

(PWM_ISR1) Counter Event on Channel 0

Definition at line 172 of file component_pwm.h.

◆ PWM_ISR1_CHID1

#define PWM_ISR1_CHID1 (0x1u << 1)

(PWM_ISR1) Counter Event on Channel 1

Definition at line 173 of file component_pwm.h.

◆ PWM_ISR1_CHID2

#define PWM_ISR1_CHID2 (0x1u << 2)

(PWM_ISR1) Counter Event on Channel 2

Definition at line 174 of file component_pwm.h.

◆ PWM_ISR1_CHID3

#define PWM_ISR1_CHID3 (0x1u << 3)

(PWM_ISR1) Counter Event on Channel 3

Definition at line 175 of file component_pwm.h.

◆ PWM_ISR1_FCHID0

#define PWM_ISR1_FCHID0 (0x1u << 16)

(PWM_ISR1) Fault Protection Trigger on Channel 0

Definition at line 176 of file component_pwm.h.

◆ PWM_ISR1_FCHID1

#define PWM_ISR1_FCHID1 (0x1u << 17)

(PWM_ISR1) Fault Protection Trigger on Channel 1

Definition at line 177 of file component_pwm.h.

◆ PWM_ISR1_FCHID2

#define PWM_ISR1_FCHID2 (0x1u << 18)

(PWM_ISR1) Fault Protection Trigger on Channel 2

Definition at line 178 of file component_pwm.h.

◆ PWM_ISR1_FCHID3

#define PWM_ISR1_FCHID3 (0x1u << 19)

(PWM_ISR1) Fault Protection Trigger on Channel 3

Definition at line 179 of file component_pwm.h.

◆ PWM_ISR2_CMPM0

#define PWM_ISR2_CMPM0 (0x1u << 8)

(PWM_ISR2) Comparison 0 Match

Definition at line 275 of file component_pwm.h.

◆ PWM_ISR2_CMPM1

#define PWM_ISR2_CMPM1 (0x1u << 9)

(PWM_ISR2) Comparison 1 Match

Definition at line 276 of file component_pwm.h.

◆ PWM_ISR2_CMPM2

#define PWM_ISR2_CMPM2 (0x1u << 10)

(PWM_ISR2) Comparison 2 Match

Definition at line 277 of file component_pwm.h.

◆ PWM_ISR2_CMPM3

#define PWM_ISR2_CMPM3 (0x1u << 11)

(PWM_ISR2) Comparison 3 Match

Definition at line 278 of file component_pwm.h.

◆ PWM_ISR2_CMPM4

#define PWM_ISR2_CMPM4 (0x1u << 12)

(PWM_ISR2) Comparison 4 Match

Definition at line 279 of file component_pwm.h.

◆ PWM_ISR2_CMPM5

#define PWM_ISR2_CMPM5 (0x1u << 13)

(PWM_ISR2) Comparison 5 Match

Definition at line 280 of file component_pwm.h.

◆ PWM_ISR2_CMPM6

#define PWM_ISR2_CMPM6 (0x1u << 14)

(PWM_ISR2) Comparison 6 Match

Definition at line 281 of file component_pwm.h.

◆ PWM_ISR2_CMPM7

#define PWM_ISR2_CMPM7 (0x1u << 15)

(PWM_ISR2) Comparison 7 Match

Definition at line 282 of file component_pwm.h.

◆ PWM_ISR2_CMPU0

#define PWM_ISR2_CMPU0 (0x1u << 16)

(PWM_ISR2) Comparison 0 Update

Definition at line 283 of file component_pwm.h.

◆ PWM_ISR2_CMPU1

#define PWM_ISR2_CMPU1 (0x1u << 17)

(PWM_ISR2) Comparison 1 Update

Definition at line 284 of file component_pwm.h.

◆ PWM_ISR2_CMPU2

#define PWM_ISR2_CMPU2 (0x1u << 18)

(PWM_ISR2) Comparison 2 Update

Definition at line 285 of file component_pwm.h.

◆ PWM_ISR2_CMPU3

#define PWM_ISR2_CMPU3 (0x1u << 19)

(PWM_ISR2) Comparison 3 Update

Definition at line 286 of file component_pwm.h.

◆ PWM_ISR2_CMPU4

#define PWM_ISR2_CMPU4 (0x1u << 20)

(PWM_ISR2) Comparison 4 Update

Definition at line 287 of file component_pwm.h.

◆ PWM_ISR2_CMPU5

#define PWM_ISR2_CMPU5 (0x1u << 21)

(PWM_ISR2) Comparison 5 Update

Definition at line 288 of file component_pwm.h.

◆ PWM_ISR2_CMPU6

#define PWM_ISR2_CMPU6 (0x1u << 22)

(PWM_ISR2) Comparison 6 Update

Definition at line 289 of file component_pwm.h.

◆ PWM_ISR2_CMPU7

#define PWM_ISR2_CMPU7 (0x1u << 23)

(PWM_ISR2) Comparison 7 Update

Definition at line 290 of file component_pwm.h.

◆ PWM_ISR2_ENDTX

#define PWM_ISR2_ENDTX (0x1u << 1)

(PWM_ISR2) PDC End of TX Buffer

Definition at line 272 of file component_pwm.h.

◆ PWM_ISR2_TXBUFE

#define PWM_ISR2_TXBUFE (0x1u << 2)

(PWM_ISR2) PDC TX Buffer Empty

Definition at line 273 of file component_pwm.h.

◆ PWM_ISR2_UNRE

#define PWM_ISR2_UNRE (0x1u << 3)

(PWM_ISR2) Synchronous Channels Update Underrun Error

Definition at line 274 of file component_pwm.h.

◆ PWM_ISR2_WRDY

#define PWM_ISR2_WRDY (0x1u << 0)

(PWM_ISR2) Write Ready for Synchronous Channels Update

Definition at line 271 of file component_pwm.h.

◆ PWM_OOV_OOVH0

#define PWM_OOV_OOVH0 (0x1u << 0)

(PWM_OOV) Output Override Value for PWMH output of the channel 0

Definition at line 292 of file component_pwm.h.

Referenced by pwm_channel_init(), and pwm_channel_update_output().

◆ PWM_OOV_OOVH1

#define PWM_OOV_OOVH1 (0x1u << 1)

(PWM_OOV) Output Override Value for PWMH output of the channel 1

Definition at line 293 of file component_pwm.h.

◆ PWM_OOV_OOVH2

#define PWM_OOV_OOVH2 (0x1u << 2)

(PWM_OOV) Output Override Value for PWMH output of the channel 2

Definition at line 294 of file component_pwm.h.

◆ PWM_OOV_OOVH3

#define PWM_OOV_OOVH3 (0x1u << 3)

(PWM_OOV) Output Override Value for PWMH output of the channel 3

Definition at line 295 of file component_pwm.h.

◆ PWM_OOV_OOVL0

#define PWM_OOV_OOVL0 (0x1u << 16)

(PWM_OOV) Output Override Value for PWML output of the channel 0

Definition at line 296 of file component_pwm.h.

Referenced by pwm_channel_init(), and pwm_channel_update_output().

◆ PWM_OOV_OOVL1

#define PWM_OOV_OOVL1 (0x1u << 17)

(PWM_OOV) Output Override Value for PWML output of the channel 1

Definition at line 297 of file component_pwm.h.

◆ PWM_OOV_OOVL2

#define PWM_OOV_OOVL2 (0x1u << 18)

(PWM_OOV) Output Override Value for PWML output of the channel 2

Definition at line 298 of file component_pwm.h.

◆ PWM_OOV_OOVL3

#define PWM_OOV_OOVL3 (0x1u << 19)

(PWM_OOV) Output Override Value for PWML output of the channel 3

Definition at line 299 of file component_pwm.h.

◆ PWM_OS_OSH0

#define PWM_OS_OSH0 (0x1u << 0)

(PWM_OS) Output Selection for PWMH output of the channel 0

Definition at line 301 of file component_pwm.h.

Referenced by pwm_channel_init().

◆ PWM_OS_OSH1

#define PWM_OS_OSH1 (0x1u << 1)

(PWM_OS) Output Selection for PWMH output of the channel 1

Definition at line 302 of file component_pwm.h.

◆ PWM_OS_OSH2

#define PWM_OS_OSH2 (0x1u << 2)

(PWM_OS) Output Selection for PWMH output of the channel 2

Definition at line 303 of file component_pwm.h.

◆ PWM_OS_OSH3

#define PWM_OS_OSH3 (0x1u << 3)

(PWM_OS) Output Selection for PWMH output of the channel 3

Definition at line 304 of file component_pwm.h.

◆ PWM_OS_OSL0

#define PWM_OS_OSL0 (0x1u << 16)

(PWM_OS) Output Selection for PWML output of the channel 0

Definition at line 305 of file component_pwm.h.

Referenced by pwm_channel_init().

◆ PWM_OS_OSL1

#define PWM_OS_OSL1 (0x1u << 17)

(PWM_OS) Output Selection for PWML output of the channel 1

Definition at line 306 of file component_pwm.h.

◆ PWM_OS_OSL2

#define PWM_OS_OSL2 (0x1u << 18)

(PWM_OS) Output Selection for PWML output of the channel 2

Definition at line 307 of file component_pwm.h.

◆ PWM_OS_OSL3

#define PWM_OS_OSL3 (0x1u << 19)

(PWM_OS) Output Selection for PWML output of the channel 3

Definition at line 308 of file component_pwm.h.

◆ PWM_OSC_OSCH0

#define PWM_OSC_OSCH0 (0x1u << 0)

(PWM_OSC) Output Selection Clear for PWMH output of the channel 0

Definition at line 319 of file component_pwm.h.

◆ PWM_OSC_OSCH1

#define PWM_OSC_OSCH1 (0x1u << 1)

(PWM_OSC) Output Selection Clear for PWMH output of the channel 1

Definition at line 320 of file component_pwm.h.

◆ PWM_OSC_OSCH2

#define PWM_OSC_OSCH2 (0x1u << 2)

(PWM_OSC) Output Selection Clear for PWMH output of the channel 2

Definition at line 321 of file component_pwm.h.

◆ PWM_OSC_OSCH3

#define PWM_OSC_OSCH3 (0x1u << 3)

(PWM_OSC) Output Selection Clear for PWMH output of the channel 3

Definition at line 322 of file component_pwm.h.

◆ PWM_OSC_OSCL0

#define PWM_OSC_OSCL0 (0x1u << 16)

(PWM_OSC) Output Selection Clear for PWML output of the channel 0

Definition at line 323 of file component_pwm.h.

◆ PWM_OSC_OSCL1

#define PWM_OSC_OSCL1 (0x1u << 17)

(PWM_OSC) Output Selection Clear for PWML output of the channel 1

Definition at line 324 of file component_pwm.h.

◆ PWM_OSC_OSCL2

#define PWM_OSC_OSCL2 (0x1u << 18)

(PWM_OSC) Output Selection Clear for PWML output of the channel 2

Definition at line 325 of file component_pwm.h.

◆ PWM_OSC_OSCL3

#define PWM_OSC_OSCL3 (0x1u << 19)

(PWM_OSC) Output Selection Clear for PWML output of the channel 3

Definition at line 326 of file component_pwm.h.

◆ PWM_OSCUPD_OSCUPH0

#define PWM_OSCUPD_OSCUPH0 (0x1u << 0)

(PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0

Definition at line 337 of file component_pwm.h.

◆ PWM_OSCUPD_OSCUPH1

#define PWM_OSCUPD_OSCUPH1 (0x1u << 1)

(PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1

Definition at line 338 of file component_pwm.h.

◆ PWM_OSCUPD_OSCUPH2

#define PWM_OSCUPD_OSCUPH2 (0x1u << 2)

(PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2

Definition at line 339 of file component_pwm.h.

◆ PWM_OSCUPD_OSCUPH3

#define PWM_OSCUPD_OSCUPH3 (0x1u << 3)

(PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3

Definition at line 340 of file component_pwm.h.

◆ PWM_OSCUPD_OSCUPL0

#define PWM_OSCUPD_OSCUPL0 (0x1u << 16)

(PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0

Definition at line 341 of file component_pwm.h.

◆ PWM_OSCUPD_OSCUPL1

#define PWM_OSCUPD_OSCUPL1 (0x1u << 17)

(PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1

Definition at line 342 of file component_pwm.h.

◆ PWM_OSCUPD_OSCUPL2

#define PWM_OSCUPD_OSCUPL2 (0x1u << 18)

(PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2

Definition at line 343 of file component_pwm.h.

◆ PWM_OSCUPD_OSCUPL3

#define PWM_OSCUPD_OSCUPL3 (0x1u << 19)

(PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3

Definition at line 344 of file component_pwm.h.

◆ PWM_OSS_OSSH0

#define PWM_OSS_OSSH0 (0x1u << 0)

(PWM_OSS) Output Selection Set for PWMH output of the channel 0

Definition at line 310 of file component_pwm.h.

◆ PWM_OSS_OSSH1

#define PWM_OSS_OSSH1 (0x1u << 1)

(PWM_OSS) Output Selection Set for PWMH output of the channel 1

Definition at line 311 of file component_pwm.h.

◆ PWM_OSS_OSSH2

#define PWM_OSS_OSSH2 (0x1u << 2)

(PWM_OSS) Output Selection Set for PWMH output of the channel 2

Definition at line 312 of file component_pwm.h.

◆ PWM_OSS_OSSH3

#define PWM_OSS_OSSH3 (0x1u << 3)

(PWM_OSS) Output Selection Set for PWMH output of the channel 3

Definition at line 313 of file component_pwm.h.

◆ PWM_OSS_OSSL0

#define PWM_OSS_OSSL0 (0x1u << 16)

(PWM_OSS) Output Selection Set for PWML output of the channel 0

Definition at line 314 of file component_pwm.h.

◆ PWM_OSS_OSSL1

#define PWM_OSS_OSSL1 (0x1u << 17)

(PWM_OSS) Output Selection Set for PWML output of the channel 1

Definition at line 315 of file component_pwm.h.

◆ PWM_OSS_OSSL2

#define PWM_OSS_OSSL2 (0x1u << 18)

(PWM_OSS) Output Selection Set for PWML output of the channel 2

Definition at line 316 of file component_pwm.h.

◆ PWM_OSS_OSSL3

#define PWM_OSS_OSSL3 (0x1u << 19)

(PWM_OSS) Output Selection Set for PWML output of the channel 3

Definition at line 317 of file component_pwm.h.

◆ PWM_OSSUPD_OSSUPH0

#define PWM_OSSUPD_OSSUPH0 (0x1u << 0)

(PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0

Definition at line 328 of file component_pwm.h.

◆ PWM_OSSUPD_OSSUPH1

#define PWM_OSSUPD_OSSUPH1 (0x1u << 1)

(PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1

Definition at line 329 of file component_pwm.h.

◆ PWM_OSSUPD_OSSUPH2

#define PWM_OSSUPD_OSSUPH2 (0x1u << 2)

(PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2

Definition at line 330 of file component_pwm.h.

◆ PWM_OSSUPD_OSSUPH3

#define PWM_OSSUPD_OSSUPH3 (0x1u << 3)

(PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3

Definition at line 331 of file component_pwm.h.

◆ PWM_OSSUPD_OSSUPL0

#define PWM_OSSUPD_OSSUPL0 (0x1u << 16)

(PWM_OSSUPD) Output Selection Set for PWML output of the channel 0

Definition at line 332 of file component_pwm.h.

◆ PWM_OSSUPD_OSSUPL1

#define PWM_OSSUPD_OSSUPL1 (0x1u << 17)

(PWM_OSSUPD) Output Selection Set for PWML output of the channel 1

Definition at line 333 of file component_pwm.h.

◆ PWM_OSSUPD_OSSUPL2

#define PWM_OSSUPD_OSSUPL2 (0x1u << 18)

(PWM_OSSUPD) Output Selection Set for PWML output of the channel 2

Definition at line 334 of file component_pwm.h.

◆ PWM_OSSUPD_OSSUPL3

#define PWM_OSSUPD_OSSUPL3 (0x1u << 19)

(PWM_OSSUPD) Output Selection Set for PWML output of the channel 3

Definition at line 335 of file component_pwm.h.

◆ PWM_PTCR_RXTDIS

#define PWM_PTCR_RXTDIS (0x1u << 1)

(PWM_PTCR) Receiver Transfer Disable

Definition at line 449 of file component_pwm.h.

◆ PWM_PTCR_RXTEN

#define PWM_PTCR_RXTEN (0x1u << 0)

(PWM_PTCR) Receiver Transfer Enable

Definition at line 448 of file component_pwm.h.

◆ PWM_PTCR_TXTDIS

#define PWM_PTCR_TXTDIS (0x1u << 9)

(PWM_PTCR) Transmitter Transfer Disable

Definition at line 451 of file component_pwm.h.

◆ PWM_PTCR_TXTEN

#define PWM_PTCR_TXTEN (0x1u << 8)

(PWM_PTCR) Transmitter Transfer Enable

Definition at line 450 of file component_pwm.h.

◆ PWM_PTSR_RXTEN

#define PWM_PTSR_RXTEN (0x1u << 0)

(PWM_PTSR) Receiver Transfer Enable

Definition at line 453 of file component_pwm.h.

◆ PWM_PTSR_TXTEN

#define PWM_PTSR_TXTEN (0x1u << 8)

(PWM_PTSR) Transmitter Transfer Enable

Definition at line 454 of file component_pwm.h.

◆ PWM_SCM_PTRCS

#define PWM_SCM_PTRCS ( value )

Value:

((PWM_SCM_PTRCS_Msk & ((value) << PWM_SCM_PTRCS_Pos)))

PWM_SCM_PTRCS_Pos

#define PWM_SCM_PTRCS_Pos

Definition component_pwm.h:191

PWM_SCM_PTRCS_Msk

#define PWM_SCM_PTRCS_Msk

(PWM_SCM) PDC Transfer Request Comparison Selection

Definition component_pwm.h:192

Definition at line 193 of file component_pwm.h.

Referenced by pwm_pdc_set_request_mode().

◆ PWM_SCM_PTRCS_Msk

#define PWM_SCM_PTRCS_Msk (0x7u << PWM_SCM_PTRCS_Pos)

(PWM_SCM) PDC Transfer Request Comparison Selection

Definition at line 192 of file component_pwm.h.

Referenced by pwm_pdc_set_request_mode().

◆ PWM_SCM_PTRCS_Pos

#define PWM_SCM_PTRCS_Pos 21

Definition at line 191 of file component_pwm.h.

◆ PWM_SCM_PTRM

#define PWM_SCM_PTRM (0x1u << 20)

(PWM_SCM) PDC Transfer Request Mode

Definition at line 190 of file component_pwm.h.

Referenced by pwm_pdc_set_request_mode().

◆ PWM_SCM_SYNC0

#define PWM_SCM_SYNC0 (0x1u << 0)

(PWM_SCM) Synchronous Channel 0

Definition at line 181 of file component_pwm.h.

◆ PWM_SCM_SYNC1

#define PWM_SCM_SYNC1 (0x1u << 1)

(PWM_SCM) Synchronous Channel 1

Definition at line 182 of file component_pwm.h.

◆ PWM_SCM_SYNC2

#define PWM_SCM_SYNC2 (0x1u << 2)

(PWM_SCM) Synchronous Channel 2

Definition at line 183 of file component_pwm.h.

◆ PWM_SCM_SYNC3

#define PWM_SCM_SYNC3 (0x1u << 3)

(PWM_SCM) Synchronous Channel 3

Definition at line 184 of file component_pwm.h.

◆ PWM_SCM_UPDM_MODE0

#define PWM_SCM_UPDM_MODE0 (0x0u << 16)

(PWM_SCM) Manual write of double buffer registers and manual update of synchronous channels

Definition at line 187 of file component_pwm.h.

◆ PWM_SCM_UPDM_MODE1

#define PWM_SCM_UPDM_MODE1 (0x1u << 16)

(PWM_SCM) Manual write of double buffer registers and automatic update of synchronous channels

Definition at line 188 of file component_pwm.h.

◆ PWM_SCM_UPDM_MODE2

#define PWM_SCM_UPDM_MODE2 (0x2u << 16)

(PWM_SCM) Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous channels

Definition at line 189 of file component_pwm.h.

◆ PWM_SCM_UPDM_Msk

#define PWM_SCM_UPDM_Msk (0x3u << PWM_SCM_UPDM_Pos)

(PWM_SCM) Synchronous Channels Update Mode

Definition at line 186 of file component_pwm.h.

Referenced by pwm_sync_init().

◆ PWM_SCM_UPDM_Pos

#define PWM_SCM_UPDM_Pos 16

Definition at line 185 of file component_pwm.h.

◆ PWM_SCUC_UPDULOCK

#define PWM_SCUC_UPDULOCK (0x1u << 0)

(PWM_SCUC) Synchronous Channels Update Unlock

Definition at line 195 of file component_pwm.h.

Referenced by pwm_sync_unlock_update().

◆ PWM_SCUP_UPR

#define PWM_SCUP_UPR ( value )

Value:

((PWM_SCUP_UPR_Msk & ((value) << PWM_SCUP_UPR_Pos)))

PWM_SCUP_UPR_Msk

#define PWM_SCUP_UPR_Msk

(PWM_SCUP) Update Period

Definition component_pwm.h:198

PWM_SCUP_UPR_Pos

#define PWM_SCUP_UPR_Pos

Definition component_pwm.h:197

Definition at line 199 of file component_pwm.h.

Referenced by pwm_sync_init().

◆ PWM_SCUP_UPR_Msk

#define PWM_SCUP_UPR_Msk (0xfu << PWM_SCUP_UPR_Pos)

(PWM_SCUP) Update Period

Definition at line 198 of file component_pwm.h.

◆ PWM_SCUP_UPR_Pos

#define PWM_SCUP_UPR_Pos 0

Definition at line 197 of file component_pwm.h.

◆ PWM_SCUP_UPRCNT

#define PWM_SCUP_UPRCNT ( value )

Value:

((PWM_SCUP_UPRCNT_Msk & ((value) << PWM_SCUP_UPRCNT_Pos)))

PWM_SCUP_UPRCNT_Pos

#define PWM_SCUP_UPRCNT_Pos

Definition component_pwm.h:200

PWM_SCUP_UPRCNT_Msk

#define PWM_SCUP_UPRCNT_Msk

(PWM_SCUP) Update Period Counter

Definition component_pwm.h:201

Definition at line 202 of file component_pwm.h.

Referenced by pwm_sync_get_period_counter().

◆ PWM_SCUP_UPRCNT_Msk

#define PWM_SCUP_UPRCNT_Msk (0xfu << PWM_SCUP_UPRCNT_Pos)

(PWM_SCUP) Update Period Counter

Definition at line 201 of file component_pwm.h.

◆ PWM_SCUP_UPRCNT_Pos

#define PWM_SCUP_UPRCNT_Pos 4

Definition at line 200 of file component_pwm.h.

◆ PWM_SCUPUPD_UPRUPD

#define PWM_SCUPUPD_UPRUPD ( value )

Value:

((PWM_SCUPUPD_UPRUPD_Msk & ((value) << PWM_SCUPUPD_UPRUPD_Pos)))

PWM_SCUPUPD_UPRUPD_Pos

#define PWM_SCUPUPD_UPRUPD_Pos

Definition component_pwm.h:204

PWM_SCUPUPD_UPRUPD_Msk

#define PWM_SCUPUPD_UPRUPD_Msk

(PWM_SCUPUPD) Update Period Update

Definition component_pwm.h:205

Definition at line 206 of file component_pwm.h.

Referenced by pwm_sync_change_period().

◆ PWM_SCUPUPD_UPRUPD_Msk

#define PWM_SCUPUPD_UPRUPD_Msk (0xfu << PWM_SCUPUPD_UPRUPD_Pos)

(PWM_SCUPUPD) Update Period Update

Definition at line 205 of file component_pwm.h.

◆ PWM_SCUPUPD_UPRUPD_Pos

#define PWM_SCUPUPD_UPRUPD_Pos 0

Definition at line 204 of file component_pwm.h.

◆ PWM_SMMR_DOWN0

#define PWM_SMMR_DOWN0 (0x1u << 16)

(PWM_SMMR) DOWN Count

Definition at line 398 of file component_pwm.h.

Referenced by pwm_stepper_motor_init().

◆ PWM_SMMR_DOWN1

#define PWM_SMMR_DOWN1 (0x1u << 17)

(PWM_SMMR) DOWN Count

Definition at line 399 of file component_pwm.h.

◆ PWM_SMMR_GCEN0

#define PWM_SMMR_GCEN0 (0x1u << 0)

(PWM_SMMR) Gray Count ENable

Definition at line 396 of file component_pwm.h.

Referenced by pwm_stepper_motor_init().

◆ PWM_SMMR_GCEN1

#define PWM_SMMR_GCEN1 (0x1u << 1)

(PWM_SMMR) Gray Count ENable

Definition at line 397 of file component_pwm.h.

◆ PWM_SR_CHID0

#define PWM_SR_CHID0 (0x1u << 0)

(PWM_SR) Channel ID

Definition at line 140 of file component_pwm.h.

◆ PWM_SR_CHID1

#define PWM_SR_CHID1 (0x1u << 1)

(PWM_SR) Channel ID

Definition at line 141 of file component_pwm.h.

◆ PWM_SR_CHID2

#define PWM_SR_CHID2 (0x1u << 2)

(PWM_SR) Channel ID

Definition at line 142 of file component_pwm.h.

◆ PWM_SR_CHID3

#define PWM_SR_CHID3 (0x1u << 3)

(PWM_SR) Channel ID

Definition at line 143 of file component_pwm.h.

◆ PWM_TCR_TXCTR

#define PWM_TCR_TXCTR ( value )

Value:

((PWM_TCR_TXCTR_Msk & ((value) << PWM_TCR_TXCTR_Pos)))

PWM_TCR_TXCTR_Pos

#define PWM_TCR_TXCTR_Pos

Definition component_pwm.h:436

PWM_TCR_TXCTR_Msk

#define PWM_TCR_TXCTR_Msk

(PWM_TCR) Transmit Counter Register

Definition component_pwm.h:437

Definition at line 438 of file component_pwm.h.

◆ PWM_TCR_TXCTR_Msk

#define PWM_TCR_TXCTR_Msk (0xffffu << PWM_TCR_TXCTR_Pos)

(PWM_TCR) Transmit Counter Register

Definition at line 437 of file component_pwm.h.

◆ PWM_TCR_TXCTR_Pos

#define PWM_TCR_TXCTR_Pos 0

Definition at line 436 of file component_pwm.h.

◆ PWM_TNCR_TXNCTR

#define PWM_TNCR_TXNCTR ( value )

Value:

((PWM_TNCR_TXNCTR_Msk & ((value) << PWM_TNCR_TXNCTR_Pos)))

PWM_TNCR_TXNCTR_Pos

#define PWM_TNCR_TXNCTR_Pos

Definition component_pwm.h:444

PWM_TNCR_TXNCTR_Msk

#define PWM_TNCR_TXNCTR_Msk

(PWM_TNCR) Transmit Counter Next

Definition component_pwm.h:445

Definition at line 446 of file component_pwm.h.

◆ PWM_TNCR_TXNCTR_Msk

#define PWM_TNCR_TXNCTR_Msk (0xffffu << PWM_TNCR_TXNCTR_Pos)

(PWM_TNCR) Transmit Counter Next

Definition at line 445 of file component_pwm.h.

◆ PWM_TNCR_TXNCTR_Pos

#define PWM_TNCR_TXNCTR_Pos 0

Definition at line 444 of file component_pwm.h.

◆ PWM_TNPR_TXNPTR

#define PWM_TNPR_TXNPTR ( value )

Value:

((PWM_TNPR_TXNPTR_Msk & ((value) << PWM_TNPR_TXNPTR_Pos)))

PWM_TNPR_TXNPTR_Pos

#define PWM_TNPR_TXNPTR_Pos

Definition component_pwm.h:440

PWM_TNPR_TXNPTR_Msk

#define PWM_TNPR_TXNPTR_Msk

(PWM_TNPR) Transmit Next Pointer

Definition component_pwm.h:441

Definition at line 442 of file component_pwm.h.

◆ PWM_TNPR_TXNPTR_Msk

#define PWM_TNPR_TXNPTR_Msk (0xffffffffu << PWM_TNPR_TXNPTR_Pos)

(PWM_TNPR) Transmit Next Pointer

Definition at line 441 of file component_pwm.h.

◆ PWM_TNPR_TXNPTR_Pos

#define PWM_TNPR_TXNPTR_Pos 0

Definition at line 440 of file component_pwm.h.

◆ PWM_TPR_TXPTR

#define PWM_TPR_TXPTR ( value )

Value:

((PWM_TPR_TXPTR_Msk & ((value) << PWM_TPR_TXPTR_Pos)))

PWM_TPR_TXPTR_Msk

#define PWM_TPR_TXPTR_Msk

(PWM_TPR) Transmit Counter Register

Definition component_pwm.h:433

PWM_TPR_TXPTR_Pos

#define PWM_TPR_TXPTR_Pos

Definition component_pwm.h:432

Definition at line 434 of file component_pwm.h.

◆ PWM_TPR_TXPTR_Msk

#define PWM_TPR_TXPTR_Msk (0xffffffffu << PWM_TPR_TXPTR_Pos)

(PWM_TPR) Transmit Counter Register

Definition at line 433 of file component_pwm.h.

◆ PWM_TPR_TXPTR_Pos

#define PWM_TPR_TXPTR_Pos 0

Definition at line 432 of file component_pwm.h.

◆ PWM_WPCR_WPCMD_DISABLE_SW_PROT

#define PWM_WPCR_WPCMD_DISABLE_SW_PROT (0x0u << 0)

(PWM_WPCR) Disable the Software Write Protect of the register groups of which the bit WPRGx is at '1'.

Definition at line 403 of file component_pwm.h.

◆ PWM_WPCR_WPCMD_ENABLE_HW_PROT

#define PWM_WPCR_WPCMD_ENABLE_HW_PROT (0x2u << 0)

(PWM_WPCR) Enable the Hardware Write Protect of the register groups of which the bit WPRGx is at '1'.

Only a hardware reset of the PWM controller can disable the hardware write protect. Moreover, to meet security requirements, the PIO lines associated with PWM can not be configured through the PIO interface.

Definition at line 405 of file component_pwm.h.

◆ PWM_WPCR_WPCMD_ENABLE_SW_PROT

#define PWM_WPCR_WPCMD_ENABLE_SW_PROT (0x1u << 0)

(PWM_WPCR) Enable the Software Write Protect of the register groups of which the bit WPRGx is at '1'.

Definition at line 404 of file component_pwm.h.

◆ PWM_WPCR_WPCMD_Msk

#define PWM_WPCR_WPCMD_Msk (0x3u << PWM_WPCR_WPCMD_Pos)

(PWM_WPCR) Write Protect Command

Definition at line 402 of file component_pwm.h.

◆ PWM_WPCR_WPCMD_Pos

#define PWM_WPCR_WPCMD_Pos 0

Definition at line 401 of file component_pwm.h.

◆ PWM_WPCR_WPKEY_Msk

#define PWM_WPCR_WPKEY_Msk (0xffffffu << PWM_WPCR_WPKEY_Pos)

(PWM_WPCR) Write Protect Key

Definition at line 413 of file component_pwm.h.

◆ PWM_WPCR_WPKEY_PASSWD

#define PWM_WPCR_WPKEY_PASSWD (0x50574Du << 8)

(PWM_WPCR) Writing any other value in this field aborts the write operation of the WPCMD field.Always reads as 0

Definition at line 414 of file component_pwm.h.

◆ PWM_WPCR_WPKEY_Pos

#define PWM_WPCR_WPKEY_Pos 8

Definition at line 412 of file component_pwm.h.

◆ PWM_WPCR_WPRG0

#define PWM_WPCR_WPRG0 (0x1u << 2)

(PWM_WPCR) Write Protect Register Group 0

Definition at line 406 of file component_pwm.h.

◆ PWM_WPCR_WPRG1

#define PWM_WPCR_WPRG1 (0x1u << 3)

(PWM_WPCR) Write Protect Register Group 1

Definition at line 407 of file component_pwm.h.

◆ PWM_WPCR_WPRG2

#define PWM_WPCR_WPRG2 (0x1u << 4)

(PWM_WPCR) Write Protect Register Group 2

Definition at line 408 of file component_pwm.h.

◆ PWM_WPCR_WPRG3

#define PWM_WPCR_WPRG3 (0x1u << 5)

(PWM_WPCR) Write Protect Register Group 3

Definition at line 409 of file component_pwm.h.

◆ PWM_WPCR_WPRG4

#define PWM_WPCR_WPRG4 (0x1u << 6)

(PWM_WPCR) Write Protect Register Group 4

Definition at line 410 of file component_pwm.h.

◆ PWM_WPCR_WPRG5

#define PWM_WPCR_WPRG5 (0x1u << 7)

(PWM_WPCR) Write Protect Register Group 5

Definition at line 411 of file component_pwm.h.

◆ PWM_WPSR_WPHWS0

#define PWM_WPSR_WPHWS0 (0x1u << 8)

(PWM_WPSR) Write Protect HW Status

Definition at line 423 of file component_pwm.h.

◆ PWM_WPSR_WPHWS1

#define PWM_WPSR_WPHWS1 (0x1u << 9)

(PWM_WPSR) Write Protect HW Status

Definition at line 424 of file component_pwm.h.

◆ PWM_WPSR_WPHWS2

#define PWM_WPSR_WPHWS2 (0x1u << 10)

(PWM_WPSR) Write Protect HW Status

Definition at line 425 of file component_pwm.h.

◆ PWM_WPSR_WPHWS3

#define PWM_WPSR_WPHWS3 (0x1u << 11)

(PWM_WPSR) Write Protect HW Status

Definition at line 426 of file component_pwm.h.

◆ PWM_WPSR_WPHWS4

#define PWM_WPSR_WPHWS4 (0x1u << 12)

(PWM_WPSR) Write Protect HW Status

Definition at line 427 of file component_pwm.h.

◆ PWM_WPSR_WPHWS5

#define PWM_WPSR_WPHWS5 (0x1u << 13)

(PWM_WPSR) Write Protect HW Status

Definition at line 428 of file component_pwm.h.