twi.h

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/*
 * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
 */
 
#ifndef TWI_H_INCLUDED
#define TWI_H_INCLUDED
 
#include "compiler.h"


#ifdef __cplusplus
extern "C" {
#endif

#define TWI_TIMEOUT              30000

#define TWI_SUCCESS              0
#define TWI_INVALID_ARGUMENT     1
#define TWI_ARBITRATION_LOST     2
#define TWI_NO_CHIP_FOUND        3
#define TWI_RECEIVE_OVERRUN      4
#define TWI_RECEIVE_NACK         5
#define TWI_SEND_OVERRUN         6
#define TWI_SEND_NACK            7
#define TWI_BUSY                 8
#define TWI_ERROR_TIMEOUT        9
 
typedef struct twi_options {
    uint32_t master_clk;
    uint32_t speed;
    uint8_t chip;
    uint8_t smbus;
} twi_options_t;

typedef struct twi_packet {
    uint8_t addr[3];
    uint32_t addr_length;
    void *buffer;
    uint32_t length;
    uint8_t chip;
} twi_packet_t;
 
#if SAMG55
enum twi_source_clock {
    TWI_SOURCE_PERIPH_CLK = TWI_CWGR_BRSRCCLK_PERIPH_CLK,
    TWI_SOURCE_PCK_CLK = TWI_CWGR_BRSRCCLK_PMC_PCK, 
};
#endif
 
void twi_enable_master_mode(Twi *p_twi);
void twi_disable_master_mode(Twi *p_twi);
uint32_t twi_master_init(Twi *p_twi, const twi_options_t *p_opt);
uint32_t twi_set_speed(Twi *p_twi, uint32_t ul_speed, uint32_t ul_mck);
uint32_t twi_probe(Twi *p_twi, uint8_t uc_slave_addr);
uint32_t twi_master_read(Twi *p_twi, twi_packet_t *p_packet);
uint32_t twi_master_write(Twi *p_twi, twi_packet_t *p_packet);
void twi_enable_interrupt(Twi *p_twi, uint32_t ul_sources);
void twi_disable_interrupt(Twi *p_twi, uint32_t ul_sources);
uint32_t twi_get_interrupt_status(Twi *p_twi);
uint32_t twi_get_interrupt_mask(Twi *p_twi);
uint8_t twi_read_byte(Twi *p_twi);
void twi_write_byte(Twi *p_twi, uint8_t uc_byte);
void twi_enable_slave_mode(Twi *p_twi);
void twi_disable_slave_mode(Twi *p_twi);
void twi_slave_init(Twi *p_twi, uint32_t ul_device_addr);
void twi_set_slave_addr(Twi *p_twi, uint32_t ul_device_addr);
uint32_t twi_slave_read(Twi *p_twi, uint8_t *p_data);
uint32_t twi_slave_write(Twi *p_twi, uint8_t *p_data);
void twi_reset(Twi *p_twi);
uint32_t twi_mk_addr(const uint8_t *addr, int len);
Pdc *twi_get_pdc_base(Twi *p_twi);
#if (SAM4E || SAM4C || SAMG || SAM4CP || SAM4CM)
void twi_set_write_protection(Twi *p_twi, bool flag);
void twi_read_write_protection_status(Twi *p_twi, uint32_t *p_status);
#endif
 
#if SAMG55
void twi_smbus_set_timing(Twi *p_twi, uint32_t ul_timing);
void twi_set_alternative_command(Twi *p_twi, uint32_t ul_alt_cmd);
void twi_set_filter(Twi *p_twi, uint32_t ul_filter);
void twi_mask_slave_addr(Twi *p_twi, uint32_t ul_mask);
void twi_set_sleepwalking(Twi *p_twi,
        uint32_t ul_matching_addr1, bool flag1,
        uint32_t ul_matching_addr2, bool flag2,
        uint32_t ul_matching_addr3, bool flag3,
        uint32_t ul_matching_data, bool flag);

static inline void twi_enable_highspeed(Twi *p_twi)
{
    p_twi->TWI_CR = TWI_CR_HSEN;
}

static inline void twi_disable_highspeed(Twi *p_twi)
{
    p_twi->TWI_CR = TWI_CR_HSDIS;
}

static inline void twi_enable_smbus(Twi *p_twi)
{
    p_twi->TWI_CR = TWI_CR_SMBEN;
}

static inline void twi_disable_smbus(Twi *p_twi)
{
    p_twi->TWI_CR = TWI_CR_SMBDIS;
}

static inline void twi_enable_pec(Twi *p_twi)
{
    p_twi->TWI_CR = TWI_CR_PECEN;
}

static inline void twi_disable_pec(Twi *p_twi)
{
    p_twi->TWI_CR = TWI_CR_PECDIS;
}

static inline void twi_request_pec(Twi *p_twi)
{
    p_twi->TWI_CR = TWI_CR_PECRQ;
}

static inline void twi_send_clear(Twi *p_twi)
{
    p_twi->TWI_CR = TWI_CR_CLEAR;
}

static inline void twi_enable_alternative_command(Twi *p_twi)
{
    p_twi->TWI_CR = TWI_CR_ACMEN;
}

static inline void twi_disable_alternative_command(Twi *p_twi)
{
    p_twi->TWI_CR = TWI_CR_ACMDIS;
}

static inline void twi_thr_clear(Twi *p_twi)
{
    p_twi->TWI_CR = TWI_CR_THRCLR;
}

static inline void twi_lock_clear(Twi *p_twi)
{
    p_twi->TWI_CR = TWI_CR_LOCKCLR;
}

static inline void twi_disable_slave_nack(Twi *p_twi)
{
    p_twi->TWI_SMR &= ~TWI_SMR_NACKEN;
}

static inline void twi_enable_slave_nack(Twi *p_twi)
{
    p_twi->TWI_SMR |= TWI_SMR_NACKEN;
}

static inline void twi_disable_slave_default_addr(Twi *p_twi)
{
    p_twi->TWI_SMR &= ~TWI_SMR_SMDA;
}

static inline void twi_enable_slave_default_addr(Twi *p_twi)
{
    p_twi->TWI_SMR |= TWI_SMR_SMDA;
}

static inline void twi_disable_smbus_host_header(Twi *p_twi)
{
    p_twi->TWI_SMR &= ~TWI_SMR_SMHH;
}

static inline void twi_enable_smbus_host_header(Twi *p_twi)
{
    p_twi->TWI_SMR |= TWI_SMR_SMHH;
}

static inline void twi_disable_clock_wait_state(Twi *p_twi)
{
    p_twi->TWI_SMR |= TWI_SMR_SCLWSDIS;
}

static inline void twi_clear_disable_clock_wait_state(Twi *p_twi)
{
    p_twi->TWI_SMR &= ~TWI_SMR_SCLWSDIS;
}

static inline void twi_disable_slave_addr1_matching(Twi *p_twi)
{
    p_twi->TWI_SMR &= ~TWI_SMR_SADR1EN;
}

static inline void twi_enable_slave_addr1_matching(Twi *p_twi)
{
    p_twi->TWI_SMR |= TWI_SMR_SADR1EN;
}

static inline void twi_disable_slave_addr2_matching(Twi *p_twi)
{
    p_twi->TWI_SMR &= ~TWI_SMR_SADR2EN;
}

static inline void twi_enable_slave_addr2_matching(Twi *p_twi)
{
    p_twi->TWI_SMR |= TWI_SMR_SADR2EN;
}

static inline void twi_disable_slave_addr3_matching(Twi *p_twi)
{
    p_twi->TWI_SMR &= ~TWI_SMR_SADR3EN;
}

static inline void twi_enable_slave_addr3_matching(Twi *p_twi)
{
    p_twi->TWI_SMR |= TWI_SMR_SADR3EN;
}

static inline void twi_disable_slave_data_matching(Twi *p_twi)
{
    p_twi->TWI_SMR &= ~TWI_SMR_DATAMEN;
}

static inline void twi_select_source_clock(Twi *p_twi, enum twi_source_clock src_clk)
{
    p_twi->TWI_CWGR &= ~TWI_CWGR_BRSRCCLK;
    p_twi->TWI_CWGR |= src_clk;
}
#endif


#ifdef __cplusplus
}
#endif
 
#endif /* TWI_H_INCLUDED */