SAM4SD32 (SAM4S-EK2)
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Pulse Width Modulation (PWM)

See Quickstart guide for SAM PWM module. More...

Macros

#define PWM_CLOCK_DIV_MAX   256
#define PWM_CLOCK_PRE_MAX   11
#define PWM_WPCR_WPCMD_DISABLE_SW_PROT   (PWM_WPCR_WPCMD(0))
#define PWM_WPCR_WPCMD_ENABLE_HW_PROT   (PWM_WPCR_WPCMD(2))
#define PWM_WPCR_WPCMD_ENABLE_SW_PROT   (PWM_WPCR_WPCMD(1))
#define PWM_WPCR_WPKEY_PASSWD   0x50574D00

Functions

void pwm_channel_disable (Pwm *p_pwm, uint32_t ul_channel)
 Disable the PWM channel.
void pwm_channel_disable_interrupt (Pwm *p_pwm, uint32_t ul_event, uint32_t ul_fault)
 Disable the interrupt of a channel counter event and fault protection.
void pwm_channel_enable (Pwm *p_pwm, uint32_t ul_channel)
 Enable the PWM channel.
void pwm_channel_enable_interrupt (Pwm *p_pwm, uint32_t ul_event, uint32_t ul_fault)
 Enable the interrupt of a channel counter event and fault protection.
uint32_t pwm_channel_get_counter (Pwm *p_pwm, pwm_channel_t *p_channel)
 Return channel counter value.
uint32_t pwm_channel_get_interrupt_mask (Pwm *p_pwm)
 Get channel counter event and fault protection trigger interrupt mask.
uint32_t pwm_channel_get_interrupt_status (Pwm *p_pwm)
 Get channel counter event and fault protection trigger interrupt status.
uint32_t pwm_channel_get_status (Pwm *p_pwm)
 Check which PWM channel is enabled.
uint32_t pwm_channel_init (Pwm *p_pwm, pwm_channel_t *p_channel)
 Initialize one PWM channel.
void pwm_channel_update_dead_time (Pwm *p_pwm, pwm_channel_t *p_channel, uint16_t us_deadtime_pwmh, uint16_t us_deadtime_pwml)
 Change dead-time value for PWM outputs.
uint32_t pwm_channel_update_duty (Pwm *p_pwm, pwm_channel_t *p_channel, uint32_t ul_duty)
 Change the duty cycle of the PWM channel.
void pwm_channel_update_output (Pwm *p_pwm, pwm_channel_t *p_channel, pwm_output_t *p_output, bool b_sync)
 Change output selection of the PWM channel.
uint32_t pwm_channel_update_period (Pwm *p_pwm, pwm_channel_t *p_channel, uint32_t ul_period)
 Change the period of the PWM channel.
static uint32_t pwm_clocks_generate (uint32_t ul_frequency, uint32_t ul_mck)
 Find a prescaler/divisor couple to generate the desired ul_frequency from ul_mck.
uint32_t pwm_cmp_change_setting (Pwm *p_pwm, pwm_cmp_t *p_cmp)
 Change the setting of PWM comparison.
void pwm_cmp_disable_interrupt (Pwm *p_pwm, uint32_t ul_sources, pwm_cmp_interrupt_t type)
 Disable the interrupt of comparison.
void pwm_cmp_enable_interrupt (Pwm *p_pwm, uint32_t ul_sources, pwm_cmp_interrupt_t type)
 Enable the interrupt of comparison.
uint32_t pwm_cmp_get_period_counter (Pwm *p_pwm, uint32_t ul_cmp_unit)
 Report the value of the comparison period counter.
uint32_t pwm_cmp_get_update_counter (Pwm *p_pwm, uint32_t ul_cmp_unit)
 Report the value of the comparison update period counter.
uint32_t pwm_cmp_init (Pwm *p_pwm, pwm_cmp_t *p_cmp)
 Initialize PWM comparison unit.
void pwm_disable_protect (Pwm *p_pwm, uint32_t ul_group)
 Disable PWM write protect.
void pwm_enable_protect (Pwm *p_pwm, uint32_t ul_group, bool b_sw)
 Enable PWM write protect.
void pwm_fault_clear_status (Pwm *p_pwm, pwm_fault_id_t id)
 Clear a fault input.
pwm_level_t pwm_fault_get_input_level (Pwm *p_pwm, pwm_fault_id_t id)
 Get the level of a fault input.
uint32_t pwm_fault_get_status (Pwm *p_pwm)
 Get fault status.
uint32_t pwm_fault_init (Pwm *p_pwm, pwm_fault_t *p_fault)
 Initialize the behavior of a fault input.
uint32_t pwm_get_interrupt_mask (Pwm *p_pwm)
 Get interrupt mask of PDC transfer, synchronous channels and comparison.
uint32_t pwm_get_interrupt_status (Pwm *p_pwm)
 Get interrupt status of PDC transfer, synchronous channels and comparison.
bool pwm_get_protect_status (Pwm *p_pwm, pwm_protect_t *p_protect)
 Get PWM write protect status.
uint32_t pwm_init (Pwm *p_pwm, pwm_clock_t *clock_config)
 Initialize the PWM source clock (clock A and clock B).
void pwm_pdc_disable_interrupt (Pwm *p_pwm, uint32_t ul_sources)
 Disable the interrupt of PDC transfer.
void pwm_pdc_enable_interrupt (Pwm *p_pwm, uint32_t ul_sources)
 Enable the interrupt of PDC transfer.
void pwm_pdc_set_request_mode (Pwm *p_pwm, pwm_pdc_request_mode_t request_mode, uint32_t ul_cmp_unit)
 Set PDC transfer request mode.
void pwm_stepper_motor_init (Pwm *p_pwm, pwm_stepper_motor_pair_t pair, bool b_enable_gray, bool b_down)
 Initialize PWM stepper motor mode.
void pwm_sync_change_period (Pwm *p_pwm, uint32_t ul_update_period)
 Change the wanted time between each update of the synchronous channels.
void pwm_sync_disable_interrupt (Pwm *p_pwm, uint32_t ul_sources)
 Disable the interrupt of synchronous channels.
void pwm_sync_enable_interrupt (Pwm *p_pwm, uint32_t ul_sources)
 Enable the interrupt of synchronous channel.
uint32_t pwm_sync_get_period_counter (Pwm *p_pwm)
 Get the value of the synchronization update period counter.
uint32_t pwm_sync_init (Pwm *p_pwm, pwm_sync_update_mode_t mode, uint32_t ul_update_period)
 Initialize synchronous channels update mode and period.
void pwm_sync_unlock_update (Pwm *p_pwm)
 Unlock the update of synchronous channels.

Detailed Description

See Quickstart guide for SAM PWM module.

Driver for the PWM (Pulse Width Modulation). This driver provides access to the main features of the PWM controller.

Macro Definition Documentation

◆ PWM_CLOCK_DIV_MAX

#define PWM_CLOCK_DIV_MAX   256

Definition at line 74 of file pwm.c.

Referenced by pwm_clocks_generate().

◆ PWM_CLOCK_PRE_MAX

#define PWM_CLOCK_PRE_MAX   11

Definition at line 75 of file pwm.c.

Referenced by pwm_clocks_generate().

◆ PWM_WPCR_WPCMD_DISABLE_SW_PROT

#define PWM_WPCR_WPCMD_DISABLE_SW_PROT   (PWM_WPCR_WPCMD(0))

Definition at line 63 of file pwm.c.

Referenced by pwm_disable_protect().

◆ PWM_WPCR_WPCMD_ENABLE_HW_PROT

#define PWM_WPCR_WPCMD_ENABLE_HW_PROT   (PWM_WPCR_WPCMD(2))

Definition at line 71 of file pwm.c.

Referenced by pwm_enable_protect().

◆ PWM_WPCR_WPCMD_ENABLE_SW_PROT

#define PWM_WPCR_WPCMD_ENABLE_SW_PROT   (PWM_WPCR_WPCMD(1))

Definition at line 67 of file pwm.c.

Referenced by pwm_enable_protect().

◆ PWM_WPCR_WPKEY_PASSWD

#define PWM_WPCR_WPKEY_PASSWD   0x50574D00

Definition at line 59 of file pwm.c.

Referenced by pwm_disable_protect(), and pwm_enable_protect().

Function Documentation

◆ pwm_channel_disable()

void pwm_channel_disable ( Pwm * p_pwm,
uint32_t ul_channel )

Disable the PWM channel.

Note
A disabled PWM channel can be re-initialized using pwm_channel_init().
Parameters
p_pwmPointer to a PWM instance.
ul_channelPWM channel number to disable.

Definition at line 410 of file pwm.c.

411{
412 p_pwm->PWM_DIS = (1 << ul_channel);
413}
__O uint32_t PWM_DIS
(Pwm Offset: 0x08) PWM Disable Register

References Pwm::PWM_DIS.

◆ pwm_channel_disable_interrupt()

void pwm_channel_disable_interrupt ( Pwm * p_pwm,
uint32_t ul_event,
uint32_t ul_fault )

Disable the interrupt of a channel counter event and fault protection.

Parameters
p_pwmPointer to a PWM instance.
ul_eventBitmask of channel number to disable counter event interrupt.
ul_faultBitmask of channel number to disable fault protection interrupt(ignored by SAM3N/SAM4N/SAM4C/SAM4CP/SAM4CM).

Definition at line 488 of file pwm.c.

490{
491#if (SAM3N || SAM4N || SAM4C || SAM4CP || SAM4CM)
492 p_pwm->PWM_IDR = (1 << ul_event);
493 /* avoid Cppcheck Warning */
494 UNUSED(ul_fault);
495#else
496 p_pwm->PWM_IDR1 = (1 << ul_event) | (1 << (ul_fault + 16));
497#endif
498}
__O uint32_t PWM_IDR1
(Pwm Offset: 0x14) PWM Interrupt Disable Register 1

References Pwm::PWM_IDR1.

◆ pwm_channel_enable()

void pwm_channel_enable ( Pwm * p_pwm,
uint32_t ul_channel )

Enable the PWM channel.

Note
The PWM channel should be initialized by pwm_channel_init() before it is enabled.
Parameters
p_pwmPointer to a PWM instance.
ul_channelPWM channel number to enable.

Definition at line 397 of file pwm.c.

398{
399 p_pwm->PWM_ENA = (1 << ul_channel);
400}
__O uint32_t PWM_ENA
(Pwm Offset: 0x04) PWM Enable Register

References Pwm::PWM_ENA.

◆ pwm_channel_enable_interrupt()

void pwm_channel_enable_interrupt ( Pwm * p_pwm,
uint32_t ul_event,
uint32_t ul_fault )

Enable the interrupt of a channel counter event and fault protection.

Parameters
p_pwmPointer to a PWM instance.
ul_eventChannel number to enable counter event interrupt.
ul_faultChannel number to enable fault protection interrupt(ignored by SAM3N/SAM4N/SAM4C/SAM4CP/SAM4CM).

Definition at line 467 of file pwm.c.

469{
470#if (SAM3N || SAM4N || SAM4C || SAM4CP || SAM4CM)
471 p_pwm->PWM_IER = (1 << ul_event);
472 /* avoid Cppcheck Warning */
473 UNUSED(ul_fault);
474#else
475 p_pwm->PWM_IER1 = (1 << ul_event) | (1 << (ul_fault + 16));
476#endif
477}
__O uint32_t PWM_IER1
(Pwm Offset: 0x10) PWM Interrupt Enable Register 1

References Pwm::PWM_IER1.

◆ pwm_channel_get_counter()

uint32_t pwm_channel_get_counter ( Pwm * p_pwm,
pwm_channel_t * p_channel )

Return channel counter value.

Parameters
p_pwmPointer to a PWM instance.
p_channelConfigurations of the specified PWM channel.
Returns
channel Counter value.

Definition at line 383 of file pwm.c.

384{
385 return p_pwm->PWM_CH_NUM[p_channel->channel].PWM_CCNT;
386}
__I uint32_t PWM_CCNT
(PwmCh_num Offset: 0x14) PWM Channel Counter Register
PwmCh_num PWM_CH_NUM[PWMCH_NUM_NUMBER]
(Pwm Offset: 0x200) ch_num = 0 .
uint32_t channel
Channel number.
Definition pwm.h:286

References pwm_channel_t::channel, PwmCh_num::PWM_CCNT, and Pwm::PWM_CH_NUM.

◆ pwm_channel_get_interrupt_mask()

uint32_t pwm_channel_get_interrupt_mask ( Pwm * p_pwm)

Get channel counter event and fault protection trigger interrupt mask.

Parameters
p_pwmPointer to a PWM instance.
Returns
Channel counter event and fault protection trigger interrupt mask.

Definition at line 450 of file pwm.c.

451{
452#if (SAM3N || SAM4N || SAM4C || SAM4CP || SAM4CM)
453 return p_pwm->PWM_IMR;
454#else
455 return p_pwm->PWM_IMR1;
456#endif
457}
__I uint32_t PWM_IMR1
(Pwm Offset: 0x18) PWM Interrupt Mask Register 1

References Pwm::PWM_IMR1.

◆ pwm_channel_get_interrupt_status()

uint32_t pwm_channel_get_interrupt_status ( Pwm * p_pwm)

Get channel counter event and fault protection trigger interrupt status.

Parameters
p_pwmPointer to a PWM instance.
Returns
Channel counter event and fault protection trigger interrupt status.

Definition at line 434 of file pwm.c.

435{
436#if (SAM3N || SAM4N || SAM4C || SAM4CP || SAM4CM)
437 return p_pwm->PWM_ISR;
438#else
439 return p_pwm->PWM_ISR1;
440#endif
441}
__I uint32_t PWM_ISR1
(Pwm Offset: 0x1C) PWM Interrupt Status Register 1

References Pwm::PWM_ISR1.

◆ pwm_channel_get_status()

uint32_t pwm_channel_get_status ( Pwm * p_pwm)

Check which PWM channel is enabled.

Parameters
p_pwmPointer to a PWM instance.
Returns
Bitmask of enabled PWM channel(s).

Definition at line 422 of file pwm.c.

423{
424 return p_pwm->PWM_SR;
425}
__I uint32_t PWM_SR
(Pwm Offset: 0x0C) PWM Status Register

References Pwm::PWM_SR.

◆ pwm_channel_init()

uint32_t pwm_channel_init ( Pwm * p_pwm,
pwm_channel_t * p_channel )

Initialize one PWM channel.

Parameters
p_pwmPointer to a PWM instance.
p_channelConfigurations of the specified PWM channel.
Return values
0if initialization succeeds, otherwise fails.

Definition at line 160 of file pwm.c.

161{
162 uint32_t tmp_reg = 0;
163 uint32_t ch_num = p_channel->channel;
164
165 /* Channel Mode/Clock Register */
166 tmp_reg = (p_channel->ul_prescaler & 0xF) |
167 (p_channel->polarity << 9) |
168#if (SAM3U || SAM3S || SAM3XA || SAM4S || SAM4E || SAMV70 || SAMV71 || SAME70 || SAMS70)
169 (p_channel->counter_event) |
170 (p_channel->b_deadtime_generator << 16) |
171 (p_channel->b_pwmh_output_inverted << 17) |
172 (p_channel->b_pwml_output_inverted << 18) |
173#endif
174 (p_channel->alignment);
175 p_pwm->PWM_CH_NUM[ch_num].PWM_CMR = tmp_reg;
176
177 /* Channel Duty Cycle Register */
178 p_pwm->PWM_CH_NUM[ch_num].PWM_CDTY = p_channel->ul_duty;
179
180 /* Channel Period Register */
181 p_pwm->PWM_CH_NUM[ch_num].PWM_CPRD = p_channel->ul_period;
182
183#if (SAM3U || SAM3S || SAM3XA || SAM4S || SAM4E || SAMV70 || SAMV71 || SAME70 || SAMS70)
184 /* Channel Dead Time Register */
185 if (p_channel->b_deadtime_generator) {
186 p_pwm->PWM_CH_NUM[ch_num].PWM_DT =
187 PWM_DT_DTL(p_channel->
188 us_deadtime_pwml) | PWM_DT_DTH(p_channel->
189 us_deadtime_pwmh);
190 }
191
192 /* Output Selection Register */
193 tmp_reg = p_pwm->PWM_OS & (~((PWM_OS_OSH0 | PWM_OS_OSL0) << ch_num));
194 tmp_reg |= ((p_channel->output_selection.b_override_pwmh) << ch_num) |
195 (((p_channel->output_selection.b_override_pwml) << ch_num)
196 << 16);
197 p_pwm->PWM_OS = tmp_reg;
198
199 /* Output Override Value Register */
200 tmp_reg = p_pwm->PWM_OOV & (~((PWM_OOV_OOVH0 | PWM_OOV_OOVL0) << ch_num));
201 tmp_reg |= ((p_channel->output_selection.override_level_pwmh) << ch_num) |
202 (((p_channel->output_selection.override_level_pwml) << ch_num)
203 << 16);
204 p_pwm->PWM_OOV = tmp_reg;
205
206 /* Sync Channels Mode Register */
207 uint32_t channel = (1 << ch_num);
208 if (p_channel->b_sync_ch) {
209 p_pwm->PWM_SCM |= channel;
210 } else {
211 p_pwm->PWM_SCM &= ~((uint32_t) channel);
212 }
213
214 /* Fault Protection Value Register */
215#if (SAM4E || SAMV70 || SAMV71 || SAME70 || SAMS70)
216 if (p_channel->ul_fault_output_pwmh == PWM_HIGHZ) {
217 p_pwm->PWM_FPV2 |= (0x01 << ch_num);
218 } else {
219 p_pwm->PWM_FPV2 &= ~(0x01 << ch_num);
220 if (p_channel->ul_fault_output_pwmh == PWM_HIGH) {
221 p_pwm->PWM_FPV1 |= (0x01 << ch_num);
222 } else {
223 p_pwm->PWM_FPV1 &= (~(0x01 << ch_num));
224 }
225 }
226 if (p_channel->ul_fault_output_pwml == PWM_HIGHZ) {
227 p_pwm->PWM_FPV2 |= ((0x01 << ch_num) << 16);
228 } else {
229 p_pwm->PWM_FPV2 &= ~((0x01 << ch_num) << 16);
230 if (p_channel->ul_fault_output_pwml == PWM_HIGH) {
231 p_pwm->PWM_FPV1 |= ((0x01 << ch_num) << 16);
232 } else {
233 p_pwm->PWM_FPV1 &= (~((0x01 << ch_num) << 16));
234 }
235 }
236#else
237 if (p_channel->ul_fault_output_pwmh == PWM_HIGH) {
238 p_pwm->PWM_FPV |= (0x01 << ch_num);
239 } else {
240 p_pwm->PWM_FPV &= (~(0x01 << ch_num));
241 }
242 if (p_channel->ul_fault_output_pwml == PWM_HIGH) {
243 p_pwm->PWM_FPV |= ((0x01 << ch_num) << 16);
244 } else {
245 p_pwm->PWM_FPV &= (~((0x01 << ch_num) << 16));
246 }
247#endif
248 /* Fault Protection Enable Register */
249 uint32_t fault_enable_reg = 0;
250#if (SAM3XA)
251 if (ch_num < 4) {
252 ch_num *= 8;
253 fault_enable_reg = p_pwm->PWM_FPE1;
254 fault_enable_reg &= ~(0xFF << ch_num);
255 fault_enable_reg |= ((p_channel->fault_id) << ch_num);
256 p_pwm->PWM_FPE1 = fault_enable_reg;
257 } else {
258 ch_num -= 4;
259 ch_num *= 8;
260 fault_enable_reg = p_pwm->PWM_FPE2;
261 fault_enable_reg &= ~(0xFF << ch_num);
262 fault_enable_reg |= ((p_channel->fault_id) << ch_num);
263 p_pwm->PWM_FPE2 = fault_enable_reg;
264 }
265#endif
266
267#if (SAM3U || SAM3S || SAM4S || SAM4E || SAMV70 || SAMV71 || SAME70 || SAMS70)
268 ch_num *= 8;
269 fault_enable_reg = p_pwm->PWM_FPE;
270 fault_enable_reg &= ~(0xFF << ch_num);
271 fault_enable_reg |= ((p_channel->fault_id) << ch_num);
272 p_pwm->PWM_FPE = fault_enable_reg;
273#endif
274#endif
275
276 ch_num = p_channel->channel;
277
278#if SAM4E
279 if (!ch_num) {
280 if (p_channel->spread_spectrum_mode ==
281 PWM_SPREAD_SPECTRUM_MODE_RANDOM) {
282 p_pwm->PWM_SSPR = PWM_SSPR_SPRD(p_channel->ul_spread) |
283 PWM_SSPR_SPRDM;
284 } else {
285 p_pwm->PWM_SSPR = PWM_SSPR_SPRD(p_channel->ul_spread);
286 }
287 }
288#elif (SAMV70 || SAMV71 || SAME70 || SAMS70)
289 if (!ch_num) {
290 if (p_channel->spread_spectrum_mode ==
291 PWM_SPREAD_SPECTRUM_MODE_RANDOM) {
292 p_pwm->PWM_SSPR = PWM_SSPR_SPRD(p_channel->ul_spread) |
293 PWM_SSPR_SPRDM;
294 } else {
295 p_pwm->PWM_SSPR = PWM_SSPR_SPRD(p_channel->ul_spread);
296 }
297 }
298 p_pwm->PWM_CH_NUM[ch_num].PWM_CMR &= (~PWM_CMR_PPM);
299 p_pwm->PWM_CH_NUM[ch_num].PWM_CMR |= (p_channel->ul_ppm_mode & PWM_CMR_PPM);
300#endif
301
302 return 0;
303}
#define PWM_DT_DTL(value)
#define PWM_OS_OSH0
(PWM_OS) Output Selection for PWMH output of the channel 0
#define PWM_DT_DTH(value)
#define PWM_OOV_OOVL0
(PWM_OOV) Output Override Value for PWML output of the channel 0
#define PWM_OS_OSL0
(PWM_OS) Output Selection for PWML output of the channel 0
#define PWM_OOV_OOVH0
(PWM_OOV) Output Override Value for PWMH output of the channel 0
@ PWM_HIGH
Definition pwm.h:75
__IO uint32_t PWM_CMR
(PwmCh_num Offset: 0x0) PWM Channel Mode Register
__IO uint32_t PWM_CPRD
(PwmCh_num Offset: 0xC) PWM Channel Period Register
__IO uint32_t PWM_CDTY
(PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register
__IO uint32_t PWM_DT
(PwmCh_num Offset: 0x18) PWM Channel Dead Time Register
__IO uint32_t PWM_SCM
(Pwm Offset: 0x20) PWM Sync Channels Mode Register
__IO uint32_t PWM_FPE
(Pwm Offset: 0x6C) PWM Fault Protection Enable Register
__IO uint32_t PWM_OOV
(Pwm Offset: 0x44) PWM Output Override Value Register
__IO uint32_t PWM_OS
(Pwm Offset: 0x48) PWM Output Selection Register
__IO uint32_t PWM_FPV
(Pwm Offset: 0x68) PWM Fault Protection Value Register
pwm_align_t alignment
Channel alignment.
Definition pwm.h:290
pwm_fault_id_t fault_id
Fault ID of the channel.
Definition pwm.h:316
bool b_pwml_output_inverted
Boolean of channel dead-time PWML output inverted.
Definition pwm.h:306
bool b_pwmh_output_inverted
Boolean of channel dead-time PWMH output inverted.
Definition pwm.h:304
bool b_deadtime_generator
Boolean of channel dead-time generator.
Definition pwm.h:302
pwm_level_t ul_fault_output_pwml
Channel PWML output level in fault protection.
Definition pwm.h:320
bool b_sync_ch
Boolean of Synchronous Channel.
Definition pwm.h:314
pwm_level_t polarity
Channel initial polarity.
Definition pwm.h:292
uint32_t ul_period
Period Cycle Value.
Definition pwm.h:296
uint32_t ul_prescaler
Channel prescaler.
Definition pwm.h:288
pwm_output_t output_selection
Channel output.
Definition pwm.h:312
pwm_counter_event_t counter_event
Channel counter event.
Definition pwm.h:300
pwm_level_t ul_fault_output_pwmh
Channel PWMH output level in fault protection.
Definition pwm.h:318
uint32_t ul_duty
Duty Cycle Value.
Definition pwm.h:294
bool b_override_pwml
Boolean of using override output as PWML.
Definition pwm.h:231
pwm_level_t override_level_pwml
Level of override output for PWML.
Definition pwm.h:235
pwm_level_t override_level_pwmh
Level of override output for PWMH.
Definition pwm.h:233
bool b_override_pwmh
Boolean of using override output as PWMH.
Definition pwm.h:229

References pwm_channel_t::alignment, pwm_channel_t::b_deadtime_generator, pwm_output_t::b_override_pwmh, pwm_output_t::b_override_pwml, pwm_channel_t::b_pwmh_output_inverted, pwm_channel_t::b_pwml_output_inverted, pwm_channel_t::b_sync_ch, pwm_channel_t::channel, pwm_channel_t::counter_event, pwm_channel_t::fault_id, pwm_channel_t::output_selection, pwm_output_t::override_level_pwmh, pwm_output_t::override_level_pwml, pwm_channel_t::polarity, PwmCh_num::PWM_CDTY, Pwm::PWM_CH_NUM, PwmCh_num::PWM_CMR, PwmCh_num::PWM_CPRD, PwmCh_num::PWM_DT, PWM_DT_DTH, PWM_DT_DTL, Pwm::PWM_FPE, Pwm::PWM_FPV, PWM_HIGH, Pwm::PWM_OOV, PWM_OOV_OOVH0, PWM_OOV_OOVL0, Pwm::PWM_OS, PWM_OS_OSH0, PWM_OS_OSL0, Pwm::PWM_SCM, pwm_channel_t::ul_duty, pwm_channel_t::ul_fault_output_pwmh, pwm_channel_t::ul_fault_output_pwml, pwm_channel_t::ul_period, and pwm_channel_t::ul_prescaler.

◆ pwm_channel_update_dead_time()

void pwm_channel_update_dead_time ( Pwm * p_pwm,
pwm_channel_t * p_channel,
uint16_t us_deadtime_pwmh,
uint16_t us_deadtime_pwml )

Change dead-time value for PWM outputs.

Parameters
p_pwmPointer to a PWM instance.
p_channelConfigurations of the specified PWM channel.
us_deadtime_pwmhNew dead-time value for PWMH output.
us_deadtime_pwmlNew dead-time value for PWML output.

Definition at line 554 of file pwm.c.

556{
557 /* Save new dead time value */
558 p_channel->us_deadtime_pwmh = us_deadtime_pwmh;
559 p_channel->us_deadtime_pwml = us_deadtime_pwml;
560
561 /* Write channel dead time update register */
562 p_pwm->PWM_CH_NUM[p_channel->channel].PWM_DTUPD =
563 PWM_DTUPD_DTLUPD(us_deadtime_pwml) |
564 PWM_DTUPD_DTHUPD(us_deadtime_pwmh);
565}
#define PWM_DTUPD_DTLUPD(value)
#define PWM_DTUPD_DTHUPD(value)
__O uint32_t PWM_DTUPD
(PwmCh_num Offset: 0x1C) PWM Channel Dead Time Update Register
uint16_t us_deadtime_pwml
Dead-time Value for PWML Output.
Definition pwm.h:310
uint16_t us_deadtime_pwmh
Dead-time Value for PWMH Output.
Definition pwm.h:308

References pwm_channel_t::channel, Pwm::PWM_CH_NUM, PwmCh_num::PWM_DTUPD, PWM_DTUPD_DTHUPD, PWM_DTUPD_DTLUPD, pwm_channel_t::us_deadtime_pwmh, and pwm_channel_t::us_deadtime_pwml.

◆ pwm_channel_update_duty()

uint32_t pwm_channel_update_duty ( Pwm * p_pwm,
pwm_channel_t * p_channel,
uint32_t ul_duty )

Change the duty cycle of the PWM channel.

Parameters
p_pwmPointer to a PWM instance.
p_channelConfigurations of the specified PWM channel.
ul_dutyNew duty cycle value.
Return values
0if changing succeeds, otherwise fails.

Check parameter

Definition at line 348 of file pwm.c.

350{
351 uint32_t ch_num = p_channel->channel;
352
354 if (p_channel->ul_period < ul_duty) {
356 } else {
357 /* Save new duty cycle value */
358 p_channel->ul_duty = ul_duty;
359
360#if (SAM3N || SAM4N || SAM4C || SAM4CP || SAM4CM)
361 /* Clear CPD bit to change duty cycle value */
362 uint32_t mode = p_pwm->PWM_CH_NUM[ch_num].PWM_CMR;
363 mode &= ~PWM_CMR_CPD;
364 p_pwm->PWM_CH_NUM[ch_num].PWM_CMR = mode;
365
366 p_pwm->PWM_CH_NUM[ch_num].PWM_CUPD = ul_duty;
367#else
368 p_pwm->PWM_CH_NUM[ch_num].PWM_CDTYUPD = ul_duty;
369#endif
370 }
371
372 return 0;
373}
#define PWM_INVALID_ARGUMENT
Definition pwm.h:50
__O uint32_t PWM_CDTYUPD
(PwmCh_num Offset: 0x8) PWM Channel Duty Cycle Update Register

References pwm_channel_t::channel, PwmCh_num::PWM_CDTYUPD, Pwm::PWM_CH_NUM, PwmCh_num::PWM_CMR, PWM_INVALID_ARGUMENT, pwm_channel_t::ul_duty, and pwm_channel_t::ul_period.

◆ pwm_channel_update_output()

void pwm_channel_update_output ( Pwm * p_pwm,
pwm_channel_t * p_channel,
pwm_output_t * p_output,
bool b_sync )

Change output selection of the PWM channel.

Parameters
p_pwmPointer to a PWM instance.
p_channelConfigurations of the specified PWM channel.
p_outputNew PWM channel output selection.
b_syncBoolean of changing of output selection. Set true to change the output synchronously (at the beginning of the next PWM period). Set false to change the output asynchronously (at the end of the execution of the function).

Definition at line 510 of file pwm.c.

512{
513 uint32_t ch_num = p_channel->channel;
514
515 bool override_pwmh = p_output->b_override_pwmh;
516 bool override_pwml = p_output->b_override_pwml;
517 uint32_t pwmh = p_output->override_level_pwmh;
518 uint32_t pwml = p_output->override_level_pwml;
519
520 /* Save new output configuration */
521 p_channel->output_selection.b_override_pwmh = override_pwmh;
522 p_channel->output_selection.b_override_pwml = override_pwml;
525
526 /* Change override output level */
527 uint32_t override_value = p_pwm->PWM_OOV;
528 override_value &= ~((PWM_OOV_OOVH0 | PWM_OOV_OOVL0) << ch_num);
529 override_value |= (((pwml << 16) | pwmh) << ch_num);
530 p_pwm->PWM_OOV = override_value;
531
532 /* Apply new output selection */
533 if (b_sync) {
534 p_pwm->PWM_OSSUPD = ((override_pwml << ch_num) << 16) |
535 (override_pwmh << ch_num);
536 p_pwm->PWM_OSCUPD = ((!override_pwml << ch_num) << 16) |
537 (!override_pwmh << ch_num);
538 } else {
539 p_pwm->PWM_OSS = ((override_pwml << ch_num) << 16) |
540 (override_pwmh << ch_num);
541 p_pwm->PWM_OSC = ((!override_pwml << ch_num) << 16) |
542 (!override_pwmh << ch_num);
543 }
544}
pwm_level_t
Definitions for PWM level.
Definition pwm.h:73
__O uint32_t PWM_OSCUPD
(Pwm Offset: 0x58) PWM Output Selection Clear Update Register
__O uint32_t PWM_OSSUPD
(Pwm Offset: 0x54) PWM Output Selection Set Update Register
__O uint32_t PWM_OSS
(Pwm Offset: 0x4C) PWM Output Selection Set Register
__O uint32_t PWM_OSC
(Pwm Offset: 0x50) PWM Output Selection Clear Register

References pwm_output_t::b_override_pwmh, pwm_output_t::b_override_pwml, pwm_channel_t::channel, pwm_channel_t::output_selection, pwm_output_t::override_level_pwmh, pwm_output_t::override_level_pwml, Pwm::PWM_OOV, PWM_OOV_OOVH0, PWM_OOV_OOVL0, Pwm::PWM_OSC, Pwm::PWM_OSCUPD, Pwm::PWM_OSS, and Pwm::PWM_OSSUPD.

◆ pwm_channel_update_period()

uint32_t pwm_channel_update_period ( Pwm * p_pwm,
pwm_channel_t * p_channel,
uint32_t ul_period )

Change the period of the PWM channel.

Parameters
p_pwmPointer to a PWM instance.
p_channelConfigurations of the specified PWM channel.
ul_periodNew period value.
Return values
0if changing succeeds, otherwise fails.

Check parameter

Definition at line 314 of file pwm.c.

316{
317 uint32_t ch_num = p_channel->channel;
318
320 if (p_channel->ul_duty > ul_period) {
322 } else {
323 /* Save new period value */
324 p_channel->ul_period = ul_period;
325
326#if (SAM3N || SAM4N || SAM4C || SAM4CP || SAM4CM)
327 /* Set CPD bit to change period value */
328 p_pwm->PWM_CH_NUM[ch_num].PWM_CMR |= PWM_CMR_CPD;
329
330 p_pwm->PWM_CH_NUM[ch_num].PWM_CUPD = ul_period;
331#else
332 p_pwm->PWM_CH_NUM[ch_num].PWM_CPRDUPD = ul_period;
333#endif
334 }
335
336 return 0;
337}
__O uint32_t PWM_CPRDUPD
(PwmCh_num Offset: 0x10) PWM Channel Period Update Register

References pwm_channel_t::channel, Pwm::PWM_CH_NUM, PwmCh_num::PWM_CMR, PwmCh_num::PWM_CPRDUPD, PWM_INVALID_ARGUMENT, pwm_channel_t::ul_duty, and pwm_channel_t::ul_period.

◆ pwm_clocks_generate()

uint32_t pwm_clocks_generate ( uint32_t ul_frequency,
uint32_t ul_mck )
static

Find a prescaler/divisor couple to generate the desired ul_frequency from ul_mck.

Parameters
ul_frequencyDesired frequency in Hz.
ul_mckMaster clock frequency in Hz.
Return values
Returnthe value to be set in the PWM Clock Register (PWM Mode Register for SAM3N/SAM4N/SAM4C/SAM4CP/SAM4CM) or PWM_INVALID_ARGUMENT if the configuration cannot be met.

Definition at line 87 of file pwm.c.

88{
89 uint32_t ul_divisors[PWM_CLOCK_PRE_MAX] =
90 {1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024 };
91 uint32_t ul_pre = 0;
92 uint32_t ul_div;
93
94 /* Find prescaler and divisor values */
95 do {
96 ul_div = (ul_mck / ul_divisors[ul_pre]) / ul_frequency;
97 if (ul_div <= PWM_CLOCK_DIV_MAX) {
98 break;
99 }
100 ul_pre++;
101 } while (ul_pre < PWM_CLOCK_PRE_MAX);
102
103 /* Return result */
104 if (ul_pre < PWM_CLOCK_PRE_MAX) {
105 return ul_div | (ul_pre << 8);
106 } else {
108 }
109}
#define PWM_CLOCK_DIV_MAX
Definition pwm.c:74
#define PWM_CLOCK_PRE_MAX
Definition pwm.c:75

References PWM_CLOCK_DIV_MAX, PWM_CLOCK_PRE_MAX, and PWM_INVALID_ARGUMENT.

Referenced by pwm_init().

◆ pwm_cmp_change_setting()

uint32_t pwm_cmp_change_setting ( Pwm * p_pwm,
pwm_cmp_t * p_cmp )

Change the setting of PWM comparison.

Parameters
p_pwmPointer to a PWM instance.
p_cmpConfigurations of PWM comparison tagged by unit.
Return values
0if changing succeeds, otherwise fails.

Boolean of generating a match pulse

Boolean of generating a match pulse

Boolean of comparison enable

Definition at line 696 of file pwm.c.

697{
698 uint32_t unit = p_cmp->unit;
699
700 p_pwm->PWM_CMP[unit].PWM_CMPVUPD = PWM_CMPV_CV(p_cmp->ul_value) |
701 (p_cmp->b_is_decrementing << 24);
702
703 p_pwm->PWM_CMP[unit].PWM_CMPMUPD = PWM_CMPM_CTR(p_cmp->ul_trigger) |
704 PWM_CMPM_CPR(p_cmp->ul_period) |
706
708 if (p_cmp->b_pulse_on_line_0) {
709 p_pwm->PWM_ELMR[0] |= (1 << unit);
710 } else {
711 p_pwm->PWM_ELMR[0] &= ~((uint32_t) (1 << unit));
712 }
714 if (p_cmp->b_pulse_on_line_1) {
715 p_pwm->PWM_ELMR[1] |= (1 << unit);
716 } else {
717 p_pwm->PWM_ELMR[1] &= ~((uint32_t) (1 << unit));
718 }
719
721 if (p_cmp->b_enable) {
722 p_pwm->PWM_CMP[unit].PWM_CMPMUPD |= PWM_CMPM_CEN;
723 } else {
724 p_pwm->PWM_CMP[unit].PWM_CMPMUPD &= ~PWM_CMPM_CEN;
725 }
726
727 return 0;
728}
#define PWM_CMPM_CUPR(value)
#define PWM_CMPM_CPR(value)
#define PWM_CMPV_CV(value)
#define PWM_CMPM_CTR(value)
#define PWM_CMPM_CEN
(PWM_CMPM) Comparison x Enable
__O uint32_t PWM_CMPMUPD
(PwmCmp Offset: 0xC) PWM Comparison 0 Mode Update Register
__O uint32_t PWM_CMPVUPD
(PwmCmp Offset: 0x4) PWM Comparison 0 Value Update Register
__IO uint32_t PWM_ELMR[2]
(Pwm Offset: 0x7C) PWM Event Line 0 Mode Register
PwmCmp PWM_CMP[PWMCMP_NUMBER]
(Pwm Offset: 0x130) 0 .
bool b_enable
Boolean of comparison enable.
Definition pwm.h:243
uint32_t ul_value
Comparison value.
Definition pwm.h:245
uint32_t ul_period
Comparison period value.
Definition pwm.h:251
uint32_t ul_trigger
Comparison trigger value.
Definition pwm.h:249
bool b_is_decrementing
Comparison mode.
Definition pwm.h:247
uint32_t ul_update_period
Comparison update period value.
Definition pwm.h:253
uint32_t unit
Comparison unit number.
Definition pwm.h:241
bool b_pulse_on_line_0
Boolean of generating a match pulse on PWM event line 0.
Definition pwm.h:255
bool b_pulse_on_line_1
Boolean of generating a match pulse on PWM event line 1.
Definition pwm.h:257

References pwm_cmp_t::b_enable, pwm_cmp_t::b_is_decrementing, pwm_cmp_t::b_pulse_on_line_0, pwm_cmp_t::b_pulse_on_line_1, Pwm::PWM_CMP, PWM_CMPM_CEN, PWM_CMPM_CPR, PWM_CMPM_CTR, PWM_CMPM_CUPR, PwmCmp::PWM_CMPMUPD, PWM_CMPV_CV, PwmCmp::PWM_CMPVUPD, Pwm::PWM_ELMR, pwm_cmp_t::ul_period, pwm_cmp_t::ul_trigger, pwm_cmp_t::ul_update_period, pwm_cmp_t::ul_value, and pwm_cmp_t::unit.

◆ pwm_cmp_disable_interrupt()

void pwm_cmp_disable_interrupt ( Pwm * p_pwm,
uint32_t ul_sources,
pwm_cmp_interrupt_t type )

Disable the interrupt of comparison.

Parameters
p_pwmPointer to a PWM instance.
ul_sourcesBitmask of comparison unit.
typePWM_CMP_MATCH disables the match interrupt of the unit. PWM_CMP_UPDATE disables the update interrupt of the comparison unit.

Definition at line 787 of file pwm.c.

789{
790 if (type == PWM_CMP_MATCH) {
791 p_pwm->PWM_IDR2 = ((1 << ul_sources) << 8);
792 } else if (type == PWM_CMP_UPDATE) {
793 p_pwm->PWM_IDR2 = ((1 << ul_sources) << 16);
794 } else {
795 /* Do Nothing */
796 }
797}
@ PWM_CMP_UPDATE
Definition pwm.h:174
@ PWM_CMP_MATCH
Definition pwm.h:173
__O uint32_t PWM_IDR2
(Pwm Offset: 0x38) PWM Interrupt Disable Register 2

References PWM_CMP_MATCH, PWM_CMP_UPDATE, and Pwm::PWM_IDR2.

◆ pwm_cmp_enable_interrupt()

void pwm_cmp_enable_interrupt ( Pwm * p_pwm,
uint32_t ul_sources,
pwm_cmp_interrupt_t type )

Enable the interrupt of comparison.

Parameters
p_pwmPointer to a PWM instance.
ul_sourcesBitmask of comparison unit.
typePWM_CMP_MATCH enables the match interrupt of the unit. PWM_CMP_UPDATE enables the update interrupt of the comparison unit.

Definition at line 767 of file pwm.c.

769{
770 if (type == PWM_CMP_MATCH) {
771 p_pwm->PWM_IER2 = ((1 << ul_sources) << 8);
772 } else if (type == PWM_CMP_UPDATE) {
773 p_pwm->PWM_IER2 = ((1 << ul_sources) << 16);
774 } else {
775 /* Do Nothing */
776 }
777}
__O uint32_t PWM_IER2
(Pwm Offset: 0x34) PWM Interrupt Enable Register 2

References PWM_CMP_MATCH, PWM_CMP_UPDATE, and Pwm::PWM_IER2.

◆ pwm_cmp_get_period_counter()

uint32_t pwm_cmp_get_period_counter ( Pwm * p_pwm,
uint32_t ul_cmp_unit )

Report the value of the comparison period counter.

Parameters
p_pwmPointer to a PWM instance.
ul_cmp_unitPWM comparison unit number.
Returns
Value of the comparison period counter.

Definition at line 739 of file pwm.c.

740{
741 return (PWM_CMPM_CPRCNT(p_pwm->PWM_CMP[ul_cmp_unit].PWM_CMPM)
743}
#define PWM_CMPM_CPRCNT_Pos
#define PWM_CMPM_CPRCNT(value)
__IO uint32_t PWM_CMPM
(PwmCmp Offset: 0x8) PWM Comparison 0 Mode Register

References Pwm::PWM_CMP, PwmCmp::PWM_CMPM, PWM_CMPM_CPRCNT, and PWM_CMPM_CPRCNT_Pos.

◆ pwm_cmp_get_update_counter()

uint32_t pwm_cmp_get_update_counter ( Pwm * p_pwm,
uint32_t ul_cmp_unit )

Report the value of the comparison update period counter.

Parameters
p_pwmPointer to a PWM instance.
ul_cmp_unitPWM comparison unit number.
Returns
Value of the comparison update period counter.

Definition at line 753 of file pwm.c.

754{
755 return (PWM_CMPM_CUPRCNT(p_pwm->PWM_CMP[ul_cmp_unit].PWM_CMPM)
757}
#define PWM_CMPM_CUPRCNT_Pos
#define PWM_CMPM_CUPRCNT(value)

References Pwm::PWM_CMP, PwmCmp::PWM_CMPM, PWM_CMPM_CUPRCNT, and PWM_CMPM_CUPRCNT_Pos.

◆ pwm_cmp_init()

uint32_t pwm_cmp_init ( Pwm * p_pwm,
pwm_cmp_t * p_cmp )

Initialize PWM comparison unit.

Parameters
p_pwmPointer to a PWM instance.
p_cmpConfigurations of PWM comparison tagged by unit.
Return values
0if initialization succeeds, otherwise fails.

Boolean of generating a match pulse

Boolean of generating a match pulse

Boolean of comparison enable

Definition at line 653 of file pwm.c.

654{
655 uint32_t unit = p_cmp->unit;
656
657 p_pwm->PWM_CMP[unit].PWM_CMPV = PWM_CMPV_CV(p_cmp->ul_value) |
658 (p_cmp->b_is_decrementing << 24);
659
660 p_pwm->PWM_CMP[unit].PWM_CMPM = PWM_CMPM_CTR(p_cmp->ul_trigger) |
661 PWM_CMPM_CPR(p_cmp->ul_period) |
663
665 if (p_cmp->b_pulse_on_line_0) {
666 p_pwm->PWM_ELMR[0] |= (1 << unit);
667 } else {
668 p_pwm->PWM_ELMR[0] &= ~((uint32_t) (1 << unit));
669 }
671 if (p_cmp->b_pulse_on_line_1) {
672 p_pwm->PWM_ELMR[1] |= (1 << unit);
673 } else {
674 p_pwm->PWM_ELMR[1] &= ~((uint32_t) (1 << unit));
675 }
676
678 if (p_cmp->b_enable) {
679 p_pwm->PWM_CMP[unit].PWM_CMPM |= PWM_CMPM_CEN;
680 } else {
681 p_pwm->PWM_CMP[unit].PWM_CMPM &= ~PWM_CMPM_CEN;
682 }
683
684 return 0;
685}
__IO uint32_t PWM_CMPV
(PwmCmp Offset: 0x0) PWM Comparison 0 Value Register

References pwm_cmp_t::b_enable, pwm_cmp_t::b_is_decrementing, pwm_cmp_t::b_pulse_on_line_0, pwm_cmp_t::b_pulse_on_line_1, Pwm::PWM_CMP, PwmCmp::PWM_CMPM, PWM_CMPM_CEN, PWM_CMPM_CPR, PWM_CMPM_CTR, PWM_CMPM_CUPR, PwmCmp::PWM_CMPV, PWM_CMPV_CV, Pwm::PWM_ELMR, pwm_cmp_t::ul_period, pwm_cmp_t::ul_trigger, pwm_cmp_t::ul_update_period, pwm_cmp_t::ul_value, and pwm_cmp_t::unit.

◆ pwm_disable_protect()

void pwm_disable_protect ( Pwm * p_pwm,
uint32_t ul_group )

Disable PWM write protect.

Note
Only a hardware reset of PWM controller (handled by PMC) can disable hardware write protect.
Parameters
p_pwmPointer to a PWM instance.
ul_groupBitmask of PWM register group.

Definition at line 956 of file pwm.c.

957{
959 | (ul_group << 2) | PWM_WPCR_WPCMD_DISABLE_SW_PROT;
960}
#define PWM_WPCR_WPKEY_PASSWD
Definition pwm.c:59
#define PWM_WPCR_WPCMD_DISABLE_SW_PROT
Definition pwm.c:63
__O uint32_t PWM_WPCR
(Pwm Offset: 0xE4) PWM Write Protection Control Register

References Pwm::PWM_WPCR, PWM_WPCR_WPCMD_DISABLE_SW_PROT, and PWM_WPCR_WPKEY_PASSWD.

◆ pwm_enable_protect()

void pwm_enable_protect ( Pwm * p_pwm,
uint32_t ul_group,
bool b_sw )

Enable PWM write protect.

Parameters
p_pwmPointer to a PWM instance.
ul_groupBitmask of PWM register group.
b_swBoolean of software protect. True for software protect and false for hardware protect.

Definition at line 933 of file pwm.c.

934{
935 uint32_t wp = 0;
936
937 if (b_sw) {
938 wp = PWM_WPCR_WPKEY_PASSWD | (ul_group << 2) |
940 } else {
941 wp = PWM_WPCR_WPKEY_PASSWD | (ul_group << 2) |
943 }
944
945 p_pwm->PWM_WPCR = wp;
946}
#define PWM_WPCR_WPCMD_ENABLE_HW_PROT
Definition pwm.c:71
#define PWM_WPCR_WPCMD_ENABLE_SW_PROT
Definition pwm.c:67

References Pwm::PWM_WPCR, PWM_WPCR_WPCMD_ENABLE_HW_PROT, PWM_WPCR_WPCMD_ENABLE_SW_PROT, and PWM_WPCR_WPKEY_PASSWD.

◆ pwm_fault_clear_status()

void pwm_fault_clear_status ( Pwm * p_pwm,
pwm_fault_id_t id )

Clear a fault input.

Parameters
p_pwmPointer to a PWM instance.
idFaulty ID.

Definition at line 640 of file pwm.c.

641{
642 p_pwm->PWM_FCR = id;
643}
__O uint32_t PWM_FCR
(Pwm Offset: 0x64) PWM Fault Clear Register

References Pwm::PWM_FCR.

◆ pwm_fault_get_input_level()

pwm_level_t pwm_fault_get_input_level ( Pwm * p_pwm,
pwm_fault_id_t id )

Get the level of a fault input.

Parameters
p_pwmPointer to a PWM instance.
idFaulty ID.
Returns
Level of the fault input.

Definition at line 626 of file pwm.c.

627{
628 uint32_t fault_status_reg = p_pwm->PWM_FSR;
629 fault_status_reg >>= id;
630
631 return ((fault_status_reg & 1) ? PWM_HIGH : PWM_LOW);
632}
@ PWM_LOW
Definition pwm.h:74
__I uint32_t PWM_FSR
(Pwm Offset: 0x60) PWM Fault Status Register

References Pwm::PWM_FSR, PWM_HIGH, and PWM_LOW.

◆ pwm_fault_get_status()

uint32_t pwm_fault_get_status ( Pwm * p_pwm)

Get fault status.

Parameters
p_pwmPointer to a PWM instance.
Returns
Bitmask of IDs of all active faulty.

Definition at line 613 of file pwm.c.

614{
615 return ((p_pwm->PWM_FSR >> 8) & 0xFF);
616}

References Pwm::PWM_FSR.

◆ pwm_fault_init()

uint32_t pwm_fault_init ( Pwm * p_pwm,
pwm_fault_t * p_fault )

Initialize the behavior of a fault input.

Parameters
p_pwmPointer to a PWM instance.
p_faultConfigurations of a fault input.
Return values
0if configuration succeeds, otherwise fails.

Polarity of fault input

Boolean of clearing fault flag

Boolean of fault filtering

Definition at line 577 of file pwm.c.

578{
579 uint32_t fault_id = p_fault->fault_id;
580 uint32_t fault_reg = p_pwm->PWM_FMR;
581
583 if (p_fault->polarity == PWM_HIGH) {
584 fault_reg |= fault_id;
585 } else {
586 fault_reg &= ~fault_id;
587 }
589 if (p_fault->b_clear) {
590 fault_reg |= (fault_id << 8);
591 } else {
592 fault_reg &= ~(fault_id << 8);
593 }
595 if (p_fault->b_filtered) {
596 fault_reg |= (fault_id << 16);
597 } else {
598 fault_reg &= ~(fault_id << 16);
599 }
600
601 p_pwm->PWM_FMR = fault_reg;
602
603 return 0;
604}
__IO uint32_t PWM_FMR
(Pwm Offset: 0x5C) PWM Fault Mode Register
bool b_filtered
Boolean of fault filtering.
Definition pwm.h:269
pwm_fault_id_t fault_id
Fault ID.
Definition pwm.h:263
pwm_level_t polarity
Polarity of fault input.
Definition pwm.h:265
bool b_clear
Boolean of clearing fault flag.
Definition pwm.h:267

References pwm_fault_t::b_clear, pwm_fault_t::b_filtered, pwm_fault_t::fault_id, pwm_fault_t::polarity, Pwm::PWM_FMR, and PWM_HIGH.

◆ pwm_get_interrupt_mask()

uint32_t pwm_get_interrupt_mask ( Pwm * p_pwm)

Get interrupt mask of PDC transfer, synchronous channels and comparison.

Parameters
p_pwmPointer to a PWM instance.
Returns
Interrupt mask of PDC transfer, synchronous channels and comparison.

Definition at line 1008 of file pwm.c.

1009{
1010 return p_pwm->PWM_IMR2;
1011}
__I uint32_t PWM_IMR2
(Pwm Offset: 0x3C) PWM Interrupt Mask Register 2

References Pwm::PWM_IMR2.

◆ pwm_get_interrupt_status()

uint32_t pwm_get_interrupt_status ( Pwm * p_pwm)

Get interrupt status of PDC transfer, synchronous channels and comparison.

Parameters
p_pwmPointer to a PWM instance.
Returns
Interrupt status of PDC transfer, synchronous channels and comparison.

Definition at line 996 of file pwm.c.

997{
998 return p_pwm->PWM_ISR2;
999}
__I uint32_t PWM_ISR2
(Pwm Offset: 0x40) PWM Interrupt Status Register 2

References Pwm::PWM_ISR2.

◆ pwm_get_protect_status()

bool pwm_get_protect_status ( Pwm * p_pwm,
pwm_protect_t * p_protect )

Get PWM write protect status.

Parameters
p_pwmPointer to a PWM instance.
p_protectPointer to a structure stored PWM protect status.
Return values
0Protection disabled.
1Protection enabled.

Bitmask of PWM register group for write protect software status

Definition at line 971 of file pwm.c.

972{
973 uint32_t wpsr = p_pwm->PWM_WPSR;
974
975 p_protect->ul_hw_status = (wpsr >> 8) & 0x3F;
977 p_protect->ul_sw_status = (wpsr & 0x3F);
978
979 if ((PWM_WPSR_WPVS & wpsr) == PWM_WPSR_WPVS) {
980 p_protect->ul_offset =
981 (wpsr & PWM_WPSR_WPVSRC_Msk) >>
983 return true;
984 } else {
985 return false;
986 }
987}
#define PWM_WPSR_WPVSRC_Pos
#define PWM_WPSR_WPVS
(PWM_WPSR) Write Protect Violation Status
#define PWM_WPSR_WPVSRC_Msk
(PWM_WPSR) Write Protect Violation Source
__I uint32_t PWM_WPSR
(Pwm Offset: 0xE8) PWM Write Protection Status Register
uint32_t ul_sw_status
Bitmask of PWM register group for write protect software status.
Definition pwm.h:277
uint32_t ul_offset
Offset address of PWM register in which a write access has been attempted.
Definition pwm.h:279
uint32_t ul_hw_status
Bitmask of PWM register group for write protect hardware status.
Definition pwm.h:275

References Pwm::PWM_WPSR, PWM_WPSR_WPVS, PWM_WPSR_WPVSRC_Msk, PWM_WPSR_WPVSRC_Pos, pwm_protect_t::ul_hw_status, pwm_protect_t::ul_offset, and pwm_protect_t::ul_sw_status.

◆ pwm_init()

uint32_t pwm_init ( Pwm * p_pwm,
pwm_clock_t * clock_config )

Initialize the PWM source clock (clock A and clock B).

Parameters
p_pwmPointer to a PWM instance.
clock_configPWM clock configuration.
Return values
0if initialization succeeds, otherwise fails.

Definition at line 119 of file pwm.c.

120{
121 uint32_t clock = 0;
122 uint32_t result;
123
124 /* Clock A */
125 if (clock_config->ul_clka != 0) {
126 result = pwm_clocks_generate(clock_config->ul_clka, clock_config->ul_mck);
127 if (result == PWM_INVALID_ARGUMENT) {
128 return result;
129 }
130
131 clock = result;
132 }
133
134 /* Clock B */
135 if (clock_config->ul_clkb != 0) {
136 result = pwm_clocks_generate(clock_config->ul_clkb, clock_config->ul_mck);
137
138 if (result == PWM_INVALID_ARGUMENT) {
139 return result;
140 }
141
142 clock |= (result << 16);
143 }
144#if (SAM3N || SAM4N || SAM4C || SAM4CP || SAM4CM)
145 p_pwm->PWM_MR = clock;
146#else
147 p_pwm->PWM_CLK = clock;
148#endif
149 return 0;
150}
static uint32_t pwm_clocks_generate(uint32_t ul_frequency, uint32_t ul_mck)
Find a prescaler/divisor couple to generate the desired ul_frequency from ul_mck.
Definition pwm.c:87
__IO uint32_t PWM_CLK
(Pwm Offset: 0x00) PWM Clock Register
uint32_t ul_clkb
Frequency of clock B in Hz (set 0 to turn it off).
Definition pwm.h:86
uint32_t ul_mck
Frequency of master clock in Hz.
Definition pwm.h:88
uint32_t ul_clka
Frequency of clock A in Hz (set 0 to turn it off).
Definition pwm.h:84

References Pwm::PWM_CLK, pwm_clocks_generate(), PWM_INVALID_ARGUMENT, pwm_clock_t::ul_clka, pwm_clock_t::ul_clkb, and pwm_clock_t::ul_mck.

◆ pwm_pdc_disable_interrupt()

void pwm_pdc_disable_interrupt ( Pwm * p_pwm,
uint32_t ul_sources )

Disable the interrupt of PDC transfer.

Parameters
p_pwmPointer to a PWM instance.
ul_sourcesBitmask of PWM PDC transfer interrupt sources.

Definition at line 839 of file pwm.c.

840{
841 p_pwm->PWM_IDR2 = ul_sources;
842}

References Pwm::PWM_IDR2.

◆ pwm_pdc_enable_interrupt()

void pwm_pdc_enable_interrupt ( Pwm * p_pwm,
uint32_t ul_sources )

Enable the interrupt of PDC transfer.

Parameters
p_pwmPointer to a PWM instance.
ul_sourcesBitmask of PWM PDC transfer interrupt sources.

Definition at line 828 of file pwm.c.

829{
830 p_pwm->PWM_IER2 = ul_sources;
831}

References Pwm::PWM_IER2.

◆ pwm_pdc_set_request_mode()

void pwm_pdc_set_request_mode ( Pwm * p_pwm,
pwm_pdc_request_mode_t request_mode,
uint32_t ul_cmp_unit )

Set PDC transfer request mode.

Note
If configure Synchronous channels update mode as 'PWM_SYNC_UPDATE_MODE_0' or 'PWM_SYNC_UPDATE_MODE_1' via pwm_sync_init(), ul_pdc_request will be ignored and PDC transfer request will never occur.
Parameters
p_pwmPointer to a PWM instance.
request_modePDC transfer request mode.
ul_cmp_unitPWM comparison unit number for PDC transfer request.

Definition at line 809 of file pwm.c.

811{
812 uint32_t sync_mode = p_pwm->PWM_SCM;
813
814 sync_mode &= ~(PWM_SCM_PTRCS_Msk | PWM_SCM_PTRM);
815 sync_mode |= (PWM_SCM_PTRCS(ul_cmp_unit) | request_mode);
816
817 p_pwm->PWM_SCM = sync_mode;
818}
#define PWM_SCM_PTRCS(value)
#define PWM_SCM_PTRM
(PWM_SCM) PDC Transfer Request Mode
#define PWM_SCM_PTRCS_Msk
(PWM_SCM) PDC Transfer Request Comparison Selection

References Pwm::PWM_SCM, PWM_SCM_PTRCS, PWM_SCM_PTRCS_Msk, and PWM_SCM_PTRM.

◆ pwm_stepper_motor_init()

void pwm_stepper_motor_init ( Pwm * p_pwm,
pwm_stepper_motor_pair_t pair,
bool b_enable_gray,
bool b_down )

Initialize PWM stepper motor mode.

Parameters
p_pwmPointer to a PWM instance.
pairPWM channels used by stepper motor.
b_enable_graySet true to enable gray count generation. Set false to disable it.
b_downSet true to use down counter. Set false to use up counter.

Definition at line 1023 of file pwm.c.

1025{
1026 uint32_t motor = p_pwm->PWM_SMMR;
1027
1028 motor &= ~((PWM_SMMR_GCEN0 | PWM_SMMR_DOWN0) << pair);
1029 motor |= ((b_enable_gray | (b_down << 16)) << pair);
1030
1031 p_pwm->PWM_SMMR = motor;
1032}
#define PWM_SMMR_DOWN0
(PWM_SMMR) DOWN Count
#define PWM_SMMR_GCEN0
(PWM_SMMR) Gray Count ENable
__IO uint32_t PWM_SMMR
(Pwm Offset: 0xB0) PWM Stepper Motor Mode Register

References Pwm::PWM_SMMR, PWM_SMMR_DOWN0, and PWM_SMMR_GCEN0.

◆ pwm_sync_change_period()

void pwm_sync_change_period ( Pwm * p_pwm,
uint32_t ul_update_period )

Change the wanted time between each update of the synchronous channels.

Parameters
p_pwmPointer to a PWM instance.
ul_update_periodTime between each update of the synchronous channels.

Definition at line 887 of file pwm.c.

888{
889 p_pwm->PWM_SCUPUPD = PWM_SCUPUPD_UPRUPD(ul_update_period);
890}
#define PWM_SCUPUPD_UPRUPD(value)
__O uint32_t PWM_SCUPUPD
(Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register

References Pwm::PWM_SCUPUPD, and PWM_SCUPUPD_UPRUPD.

◆ pwm_sync_disable_interrupt()

void pwm_sync_disable_interrupt ( Pwm * p_pwm,
uint32_t ul_sources )

Disable the interrupt of synchronous channels.

Parameters
p_pwmPointer to a PWM instance.
ul_sourcesBitmask of PWM synchronous channels interrupt sources.

Definition at line 921 of file pwm.c.

922{
923 p_pwm->PWM_IDR2 = ul_sources;
924}

References Pwm::PWM_IDR2.

◆ pwm_sync_enable_interrupt()

void pwm_sync_enable_interrupt ( Pwm * p_pwm,
uint32_t ul_sources )

Enable the interrupt of synchronous channel.

Parameters
p_pwmPointer to a PWM instance.
ul_sourcesBitmask of PWM synchronous channels interrupt sources.

Definition at line 910 of file pwm.c.

911{
912 p_pwm->PWM_IER2 = ul_sources;
913}

References Pwm::PWM_IER2.

◆ pwm_sync_get_period_counter()

uint32_t pwm_sync_get_period_counter ( Pwm * p_pwm)

Get the value of the synchronization update period counter.

Parameters
p_pwmPointer to a PWM instance.
Returns
Value of the synchronization update Period Counter.

Definition at line 899 of file pwm.c.

900{
901 return PWM_SCUP_UPRCNT(p_pwm->PWM_SCUP);
902}
#define PWM_SCUP_UPRCNT(value)
__IO uint32_t PWM_SCUP
(Pwm Offset: 0x2C) PWM Sync Channels Update Period Register

References Pwm::PWM_SCUP, and PWM_SCUP_UPRCNT.

◆ pwm_sync_init()

uint32_t pwm_sync_init ( Pwm * p_pwm,
pwm_sync_update_mode_t mode,
uint32_t ul_update_period )

Initialize synchronous channels update mode and period.

Parameters
p_pwmPointer to a PWM instance.
modeSynchronous channels update mode.
ul_update_periodTime between each update of the synchronous channels.
Return values
0if initialization succeeds, otherwise fails.

Definition at line 854 of file pwm.c.

856{
857 uint32_t sync_mode = p_pwm->PWM_SCM;
858
859 sync_mode &= ~PWM_SCM_UPDM_Msk;
860 sync_mode |= mode;
861
862 p_pwm->PWM_SCM = sync_mode;
863
864 p_pwm->PWM_SCUP = PWM_SCUP_UPR(ul_update_period);
865
866 return 0;
867}
#define PWM_SCUP_UPR(value)
#define PWM_SCM_UPDM_Msk
(PWM_SCM) Synchronous Channels Update Mode

References Pwm::PWM_SCM, PWM_SCM_UPDM_Msk, Pwm::PWM_SCUP, and PWM_SCUP_UPR.

◆ pwm_sync_unlock_update()

void pwm_sync_unlock_update ( Pwm * p_pwm)

Unlock the update of synchronous channels.

Note
After unlock, synchronous channels will be updated at the next PWM period.
Parameters
p_pwmPointer to a PWM instance.

Definition at line 876 of file pwm.c.

877{
879}
#define PWM_SCUC_UPDULOCK
(PWM_SCUC) Synchronous Channels Update Unlock
__IO uint32_t PWM_SCUC
(Pwm Offset: 0x28) PWM Sync Channels Update Control Register

References Pwm::PWM_SCUC, and PWM_SCUC_UPDULOCK.