48#ifndef TC_WPMR_WPKEY_PASSWD
49#define TC_WPMR_WPKEY_PASSWD TC_WPMR_WPKEY((uint32_t)0x54494D)
87 tc_channel->
TC_IDR = 0xFFFFFFFF;
93 tc_channel->
TC_CMR = ul_mode;
125 uint32_t ul_blockmode)
130 p_tc->
TC_BMR = ul_blockmode;
133#if (!SAM3U) || defined(__DOXYGEN__)
150 uint32_t ul_steppermode)
374 tc_channel->
TC_IER = ul_sources;
412 tc_channel->
TC_IDR = ul_sources;
434 return tc_channel->
TC_IMR;
457 return tc_channel->
TC_SR;
461#define TC_DIV_FACTOR 65536
463#if (!SAM4L) && !defined(__DOXYGEN__)
465#ifndef FREQ_SLOW_CLOCK_EXT
466#define FREQ_SLOW_CLOCK_EXT 32768
491 uint32_t *p_ultcclks,
492 uint32_t ul_boardmck)
494 const uint32_t divisors[5] = { 2, 8, 32, 128,
497 uint32_t ul_high, ul_low;
501 ul_index < (
sizeof(divisors) /
sizeof(divisors[0]));
503 ul_high = ul_mck / divisors[ul_index];
505 if (ul_freq > ul_high) {
507 }
else if (ul_freq >= ul_low) {
511 if (ul_index >= (
sizeof(divisors) /
sizeof(divisors[0]))) {
517 *p_uldiv = divisors[ul_index];
521 *p_ultcclks = ul_index;
529#if (SAM4L) || defined(__DOXYGEN__)
557 uint32_t *p_ultcclks,
558 uint32_t ul_boardmck)
560 const uint32_t divisors[5] = { 0, 2, 8, 32, 128};
562 uint32_t ul_high, ul_low;
568 ul_index < (
sizeof(divisors) /
sizeof(divisors[0]));
570 ul_high = ul_mck / divisors[ul_index];
572 if (ul_freq > ul_high) {
574 }
else if (ul_freq >= ul_low) {
578 if (ul_index >= (
sizeof(divisors) /
sizeof(divisors[0]))) {
584 *p_uldiv = divisors[ul_index];
588 *p_ultcclks = ul_index;
596#if (!SAM4L && !SAMG) || defined(__DOXYGEN__)
694#if (!SAM3U) || defined(__DOXYGEN__)
720#if SAM4L || defined(__DOXYGEN__)
737 return p_tc->TC_FEATURES;
755 return p_tc->TC_VERSION;
#define TC_BCR_SYNC
(TC_BCR) Synchro Command
#define TC_CCR_SWTRG
(TC_CCR) Software Trigger Command
#define TC_WPMR_WPEN
(TC_WPMR) Write Protect Enable
#define TC_CCR_CLKEN
(TC_CCR) Counter Clock Enable Command
#define TC_CCR_CLKDIS
(TC_CCR) Counter Clock Disable Command
uint32_t tc_get_qdec_interrupt_status(Tc *p_tc)
Get current TC QDEC interrupt status.
uint32_t tc_get_interrupt_mask(Tc *p_tc, uint32_t ul_channel)
Read the TC interrupt mask for the specified channel.
void tc_enable_interrupt(Tc *p_tc, uint32_t ul_channel, uint32_t ul_sources)
Enable the TC interrupts on the specified channel.
uint32_t tc_read_rb(Tc *p_tc, uint32_t ul_channel)
Read TC Register B (RB) on the specified channel.
void tc_write_rb(Tc *p_tc, uint32_t ul_channel, uint32_t ul_value)
Write to TC Register B (RB) on the specified channel.
uint32_t tc_read_rc(Tc *p_tc, uint32_t ul_channel)
Read TC Register C (RC) on the specified channel.
void tc_init(Tc *p_tc, uint32_t ul_channel, uint32_t ul_mode)
Configure TC for timer, waveform generation, or capture.
void tc_set_block_mode(Tc *p_tc, uint32_t ul_blockmode)
Configure the TC Block mode.
void tc_write_rc(Tc *p_tc, uint32_t ul_channel, uint32_t ul_value)
Write to TC Register C (RC) on the selected channel.
uint32_t tc_find_mck_divisor(uint32_t ul_freq, uint32_t ul_mck, uint32_t *p_uldiv, uint32_t *p_ultcclks, uint32_t ul_boardmck)
Find the best PBA/MCK divisor.
uint32_t tc_get_qdec_interrupt_mask(Tc *p_tc)
Read TC QDEC interrupt mask.
void tc_start(Tc *p_tc, uint32_t ul_channel)
Start the TC clock on the specified channel.
void tc_disable_interrupt(Tc *p_tc, uint32_t ul_channel, uint32_t ul_sources)
Disable TC interrupts on the specified channel.
void tc_disable_qdec_interrupt(Tc *p_tc, uint32_t ul_sources)
Disable TC QDEC interrupts.
void tc_write_ra(Tc *p_tc, uint32_t ul_channel, uint32_t ul_value)
Write to TC Register A (RA) on the specified channel.
void tc_enable_qdec_interrupt(Tc *p_tc, uint32_t ul_sources)
Enable TC QDEC interrupts.
void tc_sync_trigger(Tc *p_tc)
Asserts a SYNC signal to generate a software trigger on all channels.
uint32_t tc_get_feature(Tc *p_tc)
Indicate TC features.
void tc_set_writeprotect(Tc *p_tc, uint32_t ul_enable)
Enable or disable write protection of TC registers.
void tc_stop(Tc *p_tc, uint32_t ul_channel)
Stop the TC clock on the specified channel.
uint32_t tc_get_version(Tc *p_tc)
Indicate TC version.
uint32_t tc_init_2bit_gray(Tc *p_tc, uint32_t ul_channel, uint32_t ul_steppermode)
Configure TC for 2-bit Gray Counter for Stepper Motor.
uint32_t tc_get_status(Tc *p_tc, uint32_t ul_channel)
Get the current status for the specified TC channel.
uint32_t tc_read_ra(Tc *p_tc, uint32_t ul_channel)
Read TC Register A (RA) on the specified channel.
uint32_t tc_read_cv(Tc *p_tc, uint32_t ul_channel)
Read the counter value on the specified channel.
#define FREQ_SLOW_CLOCK_EXT
TcChannel hardware registers.
__O uint32_t TC_IER
(TcChannel Offset: 0x24) Interrupt Enable Register
__IO uint32_t TC_RA
(TcChannel Offset: 0x14) Register A
__IO uint32_t TC_RB
(TcChannel Offset: 0x18) Register B
__IO uint32_t TC_SMMR
(TcChannel Offset: 0x8) Stepper Motor Mode Register
__I uint32_t TC_SR
(TcChannel Offset: 0x20) Status Register
__IO uint32_t TC_RC
(TcChannel Offset: 0x1C) Register C
__O uint32_t TC_IDR
(TcChannel Offset: 0x28) Interrupt Disable Register
__O uint32_t TC_CCR
(TcChannel Offset: 0x0) Channel Control Register
__I uint32_t TC_IMR
(TcChannel Offset: 0x2C) Interrupt Mask Register
__IO uint32_t TC_CMR
(TcChannel Offset: 0x4) Channel Mode Register
__I uint32_t TC_CV
(TcChannel Offset: 0x10) Counter Value
__O uint32_t TC_QIDR
(Tc Offset: 0xCC) QDEC Interrupt Disable Register
__IO uint32_t TC_BMR
(Tc Offset: 0xC4) Block Mode Register
__I uint32_t TC_QIMR
(Tc Offset: 0xD0) QDEC Interrupt Mask Register
TcChannel TC_CHANNEL[TCCHANNEL_NUMBER]
(Tc Offset: 0x0) channel = 0 .
__IO uint32_t TC_WPMR
(Tc Offset: 0xE4) Write Protect Mode Register
__O uint32_t TC_BCR
(Tc Offset: 0xC0) Block Control Register
__O uint32_t TC_QIER
(Tc Offset: 0xC8) QDEC Interrupt Enable Register
__I uint32_t TC_QISR
(Tc Offset: 0xD4) QDEC Interrupt Status Register
#define TC_WPMR_WPKEY_PASSWD
SAM Timer Counter (TC) driver.