Tc Struct Reference

#include <component_tc.h>

Data Fields
__I uint32_t	Reserved1 [2]
__O uint32_t	TC_BCR
	(Tc Offset: 0xC0) Block Control Register
__IO uint32_t	TC_BMR
	(Tc Offset: 0xC4) Block Mode Register
TcChannel	TC_CHANNEL [TCCHANNEL_NUMBER]
	(Tc Offset: 0x0) channel = 0 .
__IO uint32_t	TC_FMR
	(Tc Offset: 0xD8) Fault Mode Register
__O uint32_t	TC_QIDR
	(Tc Offset: 0xCC) QDEC Interrupt Disable Register
__O uint32_t	TC_QIER
	(Tc Offset: 0xC8) QDEC Interrupt Enable Register
__I uint32_t	TC_QIMR
	(Tc Offset: 0xD0) QDEC Interrupt Mask Register
__I uint32_t	TC_QISR
	(Tc Offset: 0xD4) QDEC Interrupt Status Register
__IO uint32_t	TC_WPMR
	(Tc Offset: 0xE4) Write Protect Mode Register

Detailed Description

Definition at line 63 of file component_tc.h.

Field Documentation

Reserved1

__I uint32_t Tc::Reserved1[2]

Definition at line 72 of file component_tc.h.

TC_BCR

__O uint32_t Tc::TC_BCR

(Tc Offset: 0xC0) Block Control Register

Definition at line 65 of file component_tc.h.

Referenced by tc_sync_trigger().

TC_BMR

__IO uint32_t Tc::TC_BMR

(Tc Offset: 0xC4) Block Mode Register

Definition at line 66 of file component_tc.h.

Referenced by tc_set_block_mode().

TC_CHANNEL

TcChannel Tc::TC_CHANNEL[TCCHANNEL_NUMBER]

(Tc Offset: 0x0) channel = 0 .

. 2

Definition at line 64 of file component_tc.h.

Referenced by tc_disable_interrupt(), tc_enable_interrupt(), tc_get_interrupt_mask(), tc_get_status(), tc_init(), tc_init_2bit_gray(), tc_read_cv(), tc_read_ra(), tc_read_rb(), tc_read_rc(), tc_start(), tc_stop(), tc_write_ra(), tc_write_rb(), and tc_write_rc().

TC_FMR

__IO uint32_t Tc::TC_FMR

(Tc Offset: 0xD8) Fault Mode Register

Definition at line 71 of file component_tc.h.

TC_QIDR

__O uint32_t Tc::TC_QIDR

(Tc Offset: 0xCC) QDEC Interrupt Disable Register

Definition at line 68 of file component_tc.h.

Referenced by tc_disable_qdec_interrupt().

TC_QIER

__O uint32_t Tc::TC_QIER

(Tc Offset: 0xC8) QDEC Interrupt Enable Register

Definition at line 67 of file component_tc.h.

Referenced by tc_enable_qdec_interrupt().

TC_QIMR

__I uint32_t Tc::TC_QIMR

(Tc Offset: 0xD0) QDEC Interrupt Mask Register

Definition at line 69 of file component_tc.h.

Referenced by tc_get_qdec_interrupt_mask().

TC_QISR

__I uint32_t Tc::TC_QISR

(Tc Offset: 0xD4) QDEC Interrupt Status Register

Definition at line 70 of file component_tc.h.

Referenced by tc_get_qdec_interrupt_status().

TC_WPMR

__IO uint32_t Tc::TC_WPMR

(Tc Offset: 0xE4) Write Protect Mode Register

Definition at line 73 of file component_tc.h.

Referenced by tc_set_writeprotect().