50 p_opt->
master_clk = sysclk_get_peripheral_hz();
54 sysclk_enable_peripheral_clock(ID_FLEXCOM0);
55 }
else if (p_twi ==
TWI1) {
56 sysclk_enable_peripheral_clock(ID_FLEXCOM1);
57 }
else if (p_twi == TWI2) {
58 sysclk_enable_peripheral_clock(ID_FLEXCOM2);
59 }
else if (p_twi == TWI3) {
60 sysclk_enable_peripheral_clock(ID_FLEXCOM3);
61 }
else if (p_twi == TWI4) {
62 sysclk_enable_peripheral_clock(ID_FLEXCOM4);
63 }
else if (p_twi == TWI5) {
64 sysclk_enable_peripheral_clock(ID_FLEXCOM5);
65 }
else if (p_twi == TWI6) {
66 sysclk_enable_peripheral_clock(ID_FLEXCOM6);
67#ifdef _SAMG55_FLEXCOM7_INSTANCE_
68 }
else if (p_twi == TWI7) {
69 sysclk_enable_peripheral_clock(ID_FLEXCOM7);
75#if (!(SAMG51 || SAMG53 || SAMG54))
77 sysclk_enable_peripheral_clock(
ID_TWI0);
81 sysclk_enable_peripheral_clock(
ID_TWI1);
83 }
else if (p_twi == TWI2) {
84 sysclk_enable_peripheral_clock(ID_TWI2);
94#define twi_master_enable(p_twi) twi_enable_master_mode(p_twi)
95#define twi_master_disable(p_twi) twi_disable_master_mode(p_twi)
uint32_t twi_master_init(Twi *p_twi, const twi_options_t *p_opt)
Initialize TWI master mode.
Twi * twi_master_t
This type can be used independently to refer to TWI master module for the architecture used.
#define TWI0
(TWI0 ) Base Address
#define ID_TWI1
Two Wire Interface 1 (TWI1).
#define TWI1
(TWI1 ) Base Address
#define ID_TWI0
Two Wire Interface 0 (TWI0).
twi_options_t twi_master_options_t
static uint32_t twi_master_setup(twi_master_t p_twi, twi_master_options_t *p_opt)
twi_packet_t twi_package_t
uint8_t smbus
SMBUS mode (set 1 to use SMBUS quick command, otherwise don't).
uint32_t master_clk
MCK for TWI.
Two-Wire Interface (TWI) driver for SAM.
struct twi_packet twi_packet_t
Information concerning the data transmission.
struct twi_options twi_options_t
Input parameters when initializing the TWI module mode.