#include <stdint.h>
#include <core_cm4.h>
#include "system_sam4s.h"
#include "component/component_acc.h"
#include "component/component_adc.h"
#include "component/component_chipid.h"
#include "component/component_cmcc.h"
#include "component/component_crccu.h"
#include "component/component_dacc.h"
#include "component/component_efc.h"
#include "component/component_gpbr.h"
#include "component/component_hsmci.h"
#include "component/component_matrix.h"
#include "component/component_pdc.h"
#include "component/component_pio.h"
#include "component/component_pmc.h"
#include "component/component_pwm.h"
#include "component/component_rstc.h"
#include "component/component_rtc.h"
#include "component/component_rtt.h"
#include "component/component_smc.h"
#include "component/component_spi.h"
#include "component/component_ssc.h"
#include "component/component_supc.h"
#include "component/component_tc.h"
#include "component/component_twi.h"
#include "component/component_uart.h"
#include "component/component_udp.h"
#include "component/component_usart.h"
#include "component/component_wdt.h"
#include "instance/instance_hsmci.h"
#include "instance/instance_ssc.h"
#include "instance/instance_spi.h"
#include "instance/instance_tc0.h"
#include "instance/instance_tc1.h"
#include "instance/instance_twi0.h"
#include "instance/instance_twi1.h"
#include "instance/instance_pwm.h"
#include "instance/instance_usart0.h"
#include "instance/instance_usart1.h"
#include "instance/instance_udp.h"
#include "instance/instance_adc.h"
#include "instance/instance_dacc.h"
#include "instance/instance_acc.h"
#include "instance/instance_crccu.h"
#include "instance/instance_cmcc.h"
#include "instance/instance_smc.h"
#include "instance/instance_matrix.h"
#include "instance/instance_pmc.h"
#include "instance/instance_uart0.h"
#include "instance/instance_chipid.h"
#include "instance/instance_uart1.h"
#include "instance/instance_efc0.h"
#include "instance/instance_efc1.h"
#include "instance/instance_pioa.h"
#include "instance/instance_piob.h"
#include "instance/instance_pioc.h"
#include "instance/instance_rstc.h"
#include "instance/instance_supc.h"
#include "instance/instance_rtt.h"
#include "instance/instance_wdt.h"
#include "instance/instance_rtc.h"
#include "instance/instance_gpbr.h"
#include "pio/pio_sam4sd32c.h"

Data Structures
struct	_DeviceVectors

Macros
#define	__CM4_REV 0x0001
	Configuration of the Cortex-M4 Processor and Core Peripherals.
#define	__FPU_PRESENT 0
	SAM4SD32C does not provide a FPU.
#define	__MPU_PRESENT 1
	SAM4SD32C does provide a MPU.
#define	__NVIC_PRIO_BITS 4
	SAM4SD32C uses 4 Bits for the Priority Levels.
#define	__Vendor_SysTickConfig 0
	Set to 1 if different SysTick Config is used.
#define	ACC ((Acc *)0x40040000U)
	(ACC ) Base Address
#define	ACC_ACR_HYST_50MV_MAX (0x01UL)
#define	ACC_ACR_HYST_90MV_MAX (0x11UL)
#define	ADC ((Adc *)0x40038000U)
	(ADC ) Base Address
#define	CHIP_CIDR (0x29A70EE0UL)
#define	CHIP_FLASH_WRITE_WAIT_STATE (6U)
#define	CHIP_FREQ_CPU_MAX (120000000UL)
#define	CHIP_FREQ_FWS_0 (20000000UL)
	Maximum operating frequency when FWS is 0.
#define	CHIP_FREQ_FWS_1 (40000000UL)
	Maximum operating frequency when FWS is 1.
#define	CHIP_FREQ_FWS_2 (60000000UL)
	Maximum operating frequency when FWS is 2.
#define	CHIP_FREQ_FWS_3 (80000000UL)
	Maximum operating frequency when FWS is 3.
#define	CHIP_FREQ_FWS_4 (100000000UL)
	Maximum operating frequency when FWS is 4.
#define	CHIP_FREQ_FWS_5 (123000000UL)
	Maximum operating frequency when FWS is 5.
#define	CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)
#define	CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)
#define	CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)
#define	CHIP_FREQ_SLCK_RC (32000UL)
#define	CHIP_FREQ_SLCK_RC_MAX (44000UL)
#define	CHIP_FREQ_SLCK_RC_MIN (20000UL)
#define	CHIP_FREQ_XTAL_32K (32768UL)
#define	CHIP_JTAGID (0x05B3203FUL)
#define	CHIPID ((Chipid *)0x400E0740U)
	(CHIPID ) Base Address
#define	CMCC ((Cmcc *)0x4007C000U)
	(CMCC ) Base Address
#define	CRCCU ((Crccu *)0x40044000U)
	(CRCCU ) Base Address
#define	DACC ((Dacc *)0x4003C000U)
	(DACC ) Base Address
#define	EBI_CS0_ADDR (0x60000000u)
	EBI Chip Select 0 base address.
#define	EBI_CS1_ADDR (0x61000000u)
	EBI Chip Select 1 base address.
#define	EBI_CS2_ADDR (0x62000000u)
	EBI Chip Select 2 base address.
#define	EBI_CS3_ADDR (0x63000000u)
	EBI Chip Select 3 base address.
#define	EFC0 ((Efc *)0x400E0A00U)
	(EFC0 ) Base Address
#define	EFC1 ((Efc *)0x400E0C00U)
	(EFC1 ) Base Address
#define	GPBR ((Gpbr *)0x400E1490U)
	(GPBR ) Base Address
#define	HSMCI ((Hsmci *)0x40000000U)
	(HSMCI ) Base Address
#define	ID_ACC (33)
	Analog Comparator (ACC).
#define	ID_ADC (29)
	Analog To Digital Converter (ADC).
#define	ID_CRCCU (32)
	CRC Calculation Unit (CRCCU).
#define	ID_DACC (30)
	Digital To Analog Converter (DACC).
#define	ID_EFC0 ( 6)
	Enhanced Embedded Flash Controller 0 (EFC0).
#define	ID_EFC1 ( 7)
	Enhanced Embedded Flash Controller 1 (EFC1).
#define	ID_HSMCI (18)
	Multimedia Card Interface (HSMCI).
#define	ID_PERIPH_COUNT (35)
	Number of peripheral IDs.
#define	ID_PIOA (11)
	Parallel I/O Controller A (PIOA).
#define	ID_PIOB (12)
	Parallel I/O Controller B (PIOB).
#define	ID_PIOC (13)
	Parallel I/O Controller C (PIOC).
#define	ID_PMC ( 5)
	Power Management Controller (PMC).
#define	ID_PWM (31)
	Pulse Width Modulation (PWM).
#define	ID_RSTC ( 1)
	Reset Controller (RSTC).
#define	ID_RTC ( 2)
	Real Time Clock (RTC).
#define	ID_RTT ( 3)
	Real Time Timer (RTT).
#define	ID_SMC (10)
	Static Memory Controller (SMC).
#define	ID_SPI (21)
	Serial Peripheral Interface (SPI).
#define	ID_SSC (22)
	Synchronous Serial Controller (SSC).
#define	ID_SUPC ( 0)
	Supply Controller (SUPC).
#define	ID_TC0 (23)
	Timer/Counter 0 (TC0).
#define	ID_TC1 (24)
	Timer/Counter 1 (TC1).
#define	ID_TC2 (25)
	Timer/Counter 2 (TC2).
#define	ID_TC3 (26)
	Timer/Counter 3 (TC3).
#define	ID_TC4 (27)
	Timer/Counter 4 (TC4).
#define	ID_TC5 (28)
	Timer/Counter 5 (TC5).
#define	ID_TWI0 (19)
	Two Wire Interface 0 (TWI0).
#define	ID_TWI1 (20)
	Two Wire Interface 1 (TWI1).
#define	ID_UART0 ( 8)
	UART 0 (UART0).
#define	ID_UART1 ( 9)
	UART 1 (UART1).
#define	ID_UDP (34)
	USB Device Port (UDP).
#define	ID_USART0 (14)
	USART 0 (USART0).
#define	ID_USART1 (15)
	USART 1 (USART1).
#define	ID_WDT ( 4)
	Watchdog Timer (WDT).
#define	IFLASH0_ADDR (0x00400000u)
	Internal Flash 0 base address.
#define	IFLASH0_LOCK_REGION_SIZE (8192u)
#define	IFLASH0_NB_OF_LOCK_BITS (128u)
#define	IFLASH0_NB_OF_PAGES (2048u)
#define	IFLASH0_PAGE_SIZE (512u)
#define	IFLASH0_SIZE (0x100000u)
#define	IFLASH1_ADDR (IFLASH0_ADDR+IFLASH0_SIZE)
	Internal Flash 1 base address.
#define	IFLASH1_LOCK_REGION_SIZE (8192u)
#define	IFLASH1_NB_OF_LOCK_BITS (128u)
#define	IFLASH1_NB_OF_PAGES (2048u)
#define	IFLASH1_PAGE_SIZE (512u)
#define	IFLASH1_SIZE (0x100000u)
#define	IFLASH_SIZE (IFLASH0_SIZE+IFLASH1_SIZE)
#define	IRAM_ADDR (0x20000000u)
	Internal RAM base address.
#define	IRAM_SIZE (0x28000u)
#define	IROM_ADDR (0x00800000u)
	Internal ROM base address.
#define	MATRIX ((Matrix *)0x400E0200U)
	(MATRIX ) Base Address
#define	NB_CH_ADC (15UL)
#define	NB_CH_DAC (2UL)
#define	PDC_ADC ((Pdc *)0x40038100U)
	(PDC_ADC ) Base Address
#define	PDC_DACC ((Pdc *)0x4003C100U)
	(PDC_DACC ) Base Address
#define	PDC_HSMCI ((Pdc *)0x40000100U)
	(PDC_HSMCI ) Base Address
#define	PDC_PIOA ((Pdc *)0x400E0F68U)
	(PDC_PIOA ) Base Address
#define	PDC_PWM ((Pdc *)0x40020100U)
	(PDC_PWM ) Base Address
#define	PDC_SPI ((Pdc *)0x40008100U)
	(PDC_SPI ) Base Address
#define	PDC_SSC ((Pdc *)0x40004100U)
	(PDC_SSC ) Base Address
#define	PDC_TWI0 ((Pdc *)0x40018100U)
	(PDC_TWI0 ) Base Address
#define	PDC_TWI1 ((Pdc *)0x4001C100U)
	(PDC_TWI1 ) Base Address
#define	PDC_UART0 ((Pdc *)0x400E0700U)
	(PDC_UART0 ) Base Address
#define	PDC_UART1 ((Pdc *)0x400E0900U)
	(PDC_UART1 ) Base Address
#define	PDC_USART0 ((Pdc *)0x40024100U)
	(PDC_USART0) Base Address
#define	PDC_USART1 ((Pdc *)0x40028100U)
	(PDC_USART1) Base Address
#define	PIOA ((Pio *)0x400E0E00U)
	(PIOA ) Base Address
#define	PIOB ((Pio *)0x400E1000U)
	(PIOB ) Base Address
#define	PIOC ((Pio *)0x400E1200U)
	(PIOC ) Base Address
#define	PMC ((Pmc *)0x400E0400U)
	(PMC ) Base Address
#define	PWM ((Pwm *)0x40020000U)
	(PWM ) Base Address
#define	RSTC ((Rstc *)0x400E1400U)
	(RSTC ) Base Address
#define	RTC ((Rtc *)0x400E1460U)
	(RTC ) Base Address
#define	RTT ((Rtt *)0x400E1430U)
	(RTT ) Base Address
#define	SMC ((Smc *)0x400E0000U)
	(SMC ) Base Address
#define	SPI ((Spi *)0x40008000U)
	(SPI ) Base Address
#define	SSC ((Ssc *)0x40004000U)
	(SSC ) Base Address
#define	SUPC ((Supc *)0x400E1410U)
	(SUPC ) Base Address
#define	TC0 ((Tc *)0x40010000U)
	(TC0 ) Base Address
#define	TC1 ((Tc *)0x40014000U)
	(TC1 ) Base Address
#define	TWI0 ((Twi *)0x40018000U)
	(TWI0 ) Base Address
#define	TWI1 ((Twi *)0x4001C000U)
	(TWI1 ) Base Address
#define	UART0 ((Uart *)0x400E0600U)
	(UART0 ) Base Address
#define	UART1 ((Uart *)0x400E0800U)
	(UART1 ) Base Address
#define	UDP ((Udp *)0x40034000U)
	(UDP ) Base Address
#define	USART0 ((Usart *)0x40024000U)
	(USART0 ) Base Address
#define	USART1 ((Usart *)0x40028000U)
	(USART1 ) Base Address
#define	USB_DEVICE_MAX_EP (8UL)
#define	WDT ((Wdt *)0x400E1450U)
	(WDT ) Base Address

Typedefs
typedef struct _DeviceVectors	DeviceVectors
typedef enum IRQn	IRQn_Type
	< Interrupt Number Definition

Enumerations
enum	IRQn { NonMaskableInt_IRQn = -14 , MemoryManagement_IRQn = -12 , BusFault_IRQn = -11 , UsageFault_IRQn = -10 , SVCall_IRQn = -5 , DebugMonitor_IRQn = -4 , PendSV_IRQn = -2 , SysTick_IRQn = -1 , SUPC_IRQn = 0 , RSTC_IRQn = 1 , RTC_IRQn = 2 , RTT_IRQn = 3 , WDT_IRQn = 4 , PMC_IRQn = 5 , EFC0_IRQn = 6 , EFC1_IRQn = 7 , UART0_IRQn = 8 , UART1_IRQn = 9 , PIOA_IRQn = 11 , PIOB_IRQn = 12 , PIOC_IRQn = 13 , USART0_IRQn = 14 , USART1_IRQn = 15 , HSMCI_IRQn = 18 , TWI0_IRQn = 19 , TWI1_IRQn = 20 , SPI_IRQn = 21 , SSC_IRQn = 22 , TC0_IRQn = 23 , TC1_IRQn = 24 , TC2_IRQn = 25 , TC3_IRQn = 26 , TC4_IRQn = 27 , TC5_IRQn = 28 , ADC_IRQn = 29 , DACC_IRQn = 30 , PWM_IRQn = 31 , CRCCU_IRQn = 32 , ACC_IRQn = 33 , UDP_IRQn = 34 , PERIPH_COUNT_IRQn = 35 }
	< Interrupt Number Definition More...

Functions
void	ACC_Handler (void)
void	ADC_Handler (void)
void	BusFault_Handler (void)
void	CRCCU_Handler (void)
void	DACC_Handler (void)
void	DebugMon_Handler (void)
void	EFC0_Handler (void)
void	EFC1_Handler (void)
void	HardFault_Handler (void)
void	HSMCI_Handler (void)
void	MemManage_Handler (void)
void	NMI_Handler (void)
void	PendSV_Handler (void)
void	PIOA_Handler (void)
void	PIOB_Handler (void)
void	PIOC_Handler (void)
void	PMC_Handler (void)
void	PWM_Handler (void)
void	Reset_Handler (void)
void	RSTC_Handler (void)
void	RTC_Handler (void)
void	RTT_Handler (void)
void	SPI_Handler (void)
void	SSC_Handler (void)
void	SUPC_Handler (void)
void	SVC_Handler (void)
void	SysTick_Handler (void)
void	TC0_Handler (void)
void	TC1_Handler (void)
void	TC2_Handler (void)
void	TC3_Handler (void)
void	TC4_Handler (void)
void	TC5_Handler (void)
void	TWI0_Handler (void)
void	TWI1_Handler (void)
void	UART0_Handler (void)
void	UART1_Handler (void)
void	UDP_Handler (void)
void	UsageFault_Handler (void)
void	USART0_Handler (void)
void	USART1_Handler (void)
void	WDT_Handler (void)

Detailed Description

and its subsidiaries.

\cond ASF_LICENSE

Definition in file sam4sd32c.h.

Macro Definition Documentation

◆ __CM4_REV

#define __CM4_REV 0x0001

Configuration of the Cortex-M4 Processor and Core Peripherals.

SAM4SD32C core revision number ([15:8] revision number, [7:0] patch number)

Definition at line 221 of file sam4sd32c.h.

◆ __FPU_PRESENT

#define __FPU_PRESENT 0

SAM4SD32C does not provide a FPU.

Definition at line 223 of file sam4sd32c.h.

◆ __MPU_PRESENT

#define __MPU_PRESENT 1

SAM4SD32C does provide a MPU.

Definition at line 222 of file sam4sd32c.h.

◆ __NVIC_PRIO_BITS

#define __NVIC_PRIO_BITS 4

SAM4SD32C uses 4 Bits for the Priority Levels.

Definition at line 224 of file sam4sd32c.h.

◆ __Vendor_SysTickConfig

#define __Vendor_SysTickConfig 0

Set to 1 if different SysTick Config is used.

Definition at line 225 of file sam4sd32c.h.

◆ ACC

#define ACC ((Acc *)0x40040000U)

(ACC ) Base Address

Definition at line 434 of file sam4sd32c.h.

◆ ACC_ACR_HYST_50MV_MAX

#define ACC_ACR_HYST_50MV_MAX (0x01UL)

Definition at line 533 of file sam4sd32c.h.

◆ ACC_ACR_HYST_90MV_MAX

#define ACC_ACR_HYST_90MV_MAX (0x11UL)

Definition at line 534 of file sam4sd32c.h.

◆ ADC

#define ADC ((Adc *)0x40038000U)

(ADC ) Base Address

Definition at line 430 of file sam4sd32c.h.

◆ CHIP_CIDR

#define CHIP_CIDR (0x29A70EE0UL)

Definition at line 502 of file sam4sd32c.h.

◆ CHIP_FLASH_WRITE_WAIT_STATE

#define CHIP_FLASH_WRITE_WAIT_STATE (6U)

Definition at line 522 of file sam4sd32c.h.

◆ CHIP_FREQ_CPU_MAX

#define CHIP_FREQ_CPU_MAX (120000000UL)

Definition at line 518 of file sam4sd32c.h.

◆ CHIP_FREQ_FWS_0

#define CHIP_FREQ_FWS_0 (20000000UL)

Maximum operating frequency when FWS is 0.

Definition at line 525 of file sam4sd32c.h.

◆ CHIP_FREQ_FWS_1

#define CHIP_FREQ_FWS_1 (40000000UL)

Maximum operating frequency when FWS is 1.

Definition at line 526 of file sam4sd32c.h.

◆ CHIP_FREQ_FWS_2

#define CHIP_FREQ_FWS_2 (60000000UL)

Maximum operating frequency when FWS is 2.

Definition at line 527 of file sam4sd32c.h.

◆ CHIP_FREQ_FWS_3

#define CHIP_FREQ_FWS_3 (80000000UL)

Maximum operating frequency when FWS is 3.

Definition at line 528 of file sam4sd32c.h.

◆ CHIP_FREQ_FWS_4

#define CHIP_FREQ_FWS_4 (100000000UL)

Maximum operating frequency when FWS is 4.

Definition at line 529 of file sam4sd32c.h.

◆ CHIP_FREQ_FWS_5

#define CHIP_FREQ_FWS_5 (123000000UL)

Maximum operating frequency when FWS is 5.

Definition at line 530 of file sam4sd32c.h.

◆ CHIP_FREQ_MAINCK_RC_12MHZ

#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)

Definition at line 517 of file sam4sd32c.h.

◆ CHIP_FREQ_MAINCK_RC_4MHZ

#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)

Definition at line 515 of file sam4sd32c.h.

◆ CHIP_FREQ_MAINCK_RC_8MHZ

#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)

Definition at line 516 of file sam4sd32c.h.

◆ CHIP_FREQ_SLCK_RC

#define CHIP_FREQ_SLCK_RC (32000UL)

Definition at line 513 of file sam4sd32c.h.

◆ CHIP_FREQ_SLCK_RC_MAX

#define CHIP_FREQ_SLCK_RC_MAX (44000UL)

Definition at line 514 of file sam4sd32c.h.

◆ CHIP_FREQ_SLCK_RC_MIN

#define CHIP_FREQ_SLCK_RC_MIN (20000UL)

Definition at line 512 of file sam4sd32c.h.

◆ CHIP_FREQ_XTAL_32K

#define CHIP_FREQ_XTAL_32K (32768UL)

Definition at line 519 of file sam4sd32c.h.

◆ CHIP_JTAGID

#define CHIP_JTAGID (0x05B3203FUL)

Definition at line 501 of file sam4sd32c.h.

◆ CHIPID

#define CHIPID ((Chipid *)0x400E0740U)

(CHIPID ) Base Address

Definition at line 442 of file sam4sd32c.h.

◆ CMCC

#define CMCC ((Cmcc *)0x4007C000U)

(CMCC ) Base Address

Definition at line 436 of file sam4sd32c.h.

◆ CRCCU

#define CRCCU ((Crccu *)0x40044000U)

(CRCCU ) Base Address

Definition at line 435 of file sam4sd32c.h.

◆ DACC

#define DACC ((Dacc *)0x4003C000U)

(DACC ) Base Address

Definition at line 432 of file sam4sd32c.h.

◆ EBI_CS0_ADDR

#define EBI_CS0_ADDR (0x60000000u)

EBI Chip Select 0 base address.

Definition at line 492 of file sam4sd32c.h.

◆ EBI_CS1_ADDR

#define EBI_CS1_ADDR (0x61000000u)

EBI Chip Select 1 base address.

Definition at line 493 of file sam4sd32c.h.

◆ EBI_CS2_ADDR

#define EBI_CS2_ADDR (0x62000000u)

EBI Chip Select 2 base address.

Definition at line 494 of file sam4sd32c.h.

◆ EBI_CS3_ADDR

#define EBI_CS3_ADDR (0x63000000u)

EBI Chip Select 3 base address.

Definition at line 495 of file sam4sd32c.h.

◆ EFC0

#define EFC0 ((Efc *)0x400E0A00U)

(EFC0 ) Base Address

Definition at line 445 of file sam4sd32c.h.

◆ EFC1

#define EFC1 ((Efc *)0x400E0C00U)

(EFC1 ) Base Address

Definition at line 446 of file sam4sd32c.h.

◆ GPBR

#define GPBR ((Gpbr *)0x400E1490U)

(GPBR ) Base Address

Definition at line 456 of file sam4sd32c.h.

◆ HSMCI

#define HSMCI ((Hsmci *)0x40000000U)

(HSMCI ) Base Address

Definition at line 411 of file sam4sd32c.h.

◆ ID_ACC

#define ID_ACC (33)

Analog Comparator (ACC).

Definition at line 351 of file sam4sd32c.h.

◆ ID_ADC

#define ID_ADC (29)

Analog To Digital Converter (ADC).

Definition at line 347 of file sam4sd32c.h.

◆ ID_CRCCU

#define ID_CRCCU (32)

CRC Calculation Unit (CRCCU).

Definition at line 350 of file sam4sd32c.h.

◆ ID_DACC

#define ID_DACC (30)

Digital To Analog Converter (DACC).

Definition at line 348 of file sam4sd32c.h.

◆ ID_EFC0

#define ID_EFC0 ( 6)

Enhanced Embedded Flash Controller 0 (EFC0).

Definition at line 326 of file sam4sd32c.h.

◆ ID_EFC1

#define ID_EFC1 ( 7)

Enhanced Embedded Flash Controller 1 (EFC1).

Definition at line 327 of file sam4sd32c.h.

◆ ID_HSMCI

#define ID_HSMCI (18)

Multimedia Card Interface (HSMCI).

Definition at line 336 of file sam4sd32c.h.

◆ ID_PERIPH_COUNT

#define ID_PERIPH_COUNT (35)

Number of peripheral IDs.

Definition at line 354 of file sam4sd32c.h.

◆ ID_PIOA

#define ID_PIOA (11)

Parallel I/O Controller A (PIOA).

Definition at line 331 of file sam4sd32c.h.

Referenced by arch_ioport_init(), and pio_get_pin_group_id().

◆ ID_PIOB

#define ID_PIOB (12)

Parallel I/O Controller B (PIOB).

Definition at line 332 of file sam4sd32c.h.

Referenced by arch_ioport_init().

◆ ID_PIOC

#define ID_PIOC (13)

Parallel I/O Controller C (PIOC).

Definition at line 333 of file sam4sd32c.h.

Referenced by arch_ioport_init(), and pio_get_pin_group_id().

◆ ID_PMC

#define ID_PMC ( 5)

Power Management Controller (PMC).

Definition at line 325 of file sam4sd32c.h.

◆ ID_PWM

#define ID_PWM (31)

Pulse Width Modulation (PWM).

Definition at line 349 of file sam4sd32c.h.

◆ ID_RSTC

#define ID_RSTC ( 1)

Reset Controller (RSTC).

Definition at line 321 of file sam4sd32c.h.

◆ ID_RTC

#define ID_RTC ( 2)

Real Time Clock (RTC).

Definition at line 322 of file sam4sd32c.h.

◆ ID_RTT

#define ID_RTT ( 3)

Real Time Timer (RTT).

Definition at line 323 of file sam4sd32c.h.

◆ ID_SMC

#define ID_SMC (10)

Static Memory Controller (SMC).

Definition at line 330 of file sam4sd32c.h.

◆ ID_SPI

#define ID_SPI (21)

Serial Peripheral Interface (SPI).

Definition at line 339 of file sam4sd32c.h.

Referenced by spi_disable_clock(), and spi_enable_clock().

◆ ID_SSC

#define ID_SSC (22)

Synchronous Serial Controller (SSC).

Definition at line 340 of file sam4sd32c.h.

◆ ID_SUPC

#define ID_SUPC ( 0)

Supply Controller (SUPC).

Definition at line 320 of file sam4sd32c.h.

◆ ID_TC0

#define ID_TC0 (23)

Timer/Counter 0 (TC0).

Definition at line 341 of file sam4sd32c.h.

◆ ID_TC1

#define ID_TC1 (24)

Timer/Counter 1 (TC1).

Definition at line 342 of file sam4sd32c.h.

◆ ID_TC2

#define ID_TC2 (25)

Timer/Counter 2 (TC2).

Definition at line 343 of file sam4sd32c.h.

◆ ID_TC3

#define ID_TC3 (26)

Timer/Counter 3 (TC3).

Definition at line 344 of file sam4sd32c.h.

◆ ID_TC4

#define ID_TC4 (27)

Timer/Counter 4 (TC4).

Definition at line 345 of file sam4sd32c.h.

◆ ID_TC5

#define ID_TC5 (28)

Timer/Counter 5 (TC5).

Definition at line 346 of file sam4sd32c.h.

◆ ID_TWI0

#define ID_TWI0 (19)

Two Wire Interface 0 (TWI0).

Definition at line 337 of file sam4sd32c.h.

Referenced by twi_master_setup(), and twi_slave_setup().

◆ ID_TWI1

#define ID_TWI1 (20)

Two Wire Interface 1 (TWI1).

Definition at line 338 of file sam4sd32c.h.

Referenced by twi_master_setup(), and twi_slave_setup().

◆ ID_UART0

#define ID_UART0 ( 8)

UART 0 (UART0).

Definition at line 328 of file sam4sd32c.h.

Referenced by usart_serial_init().

◆ ID_UART1

#define ID_UART1 ( 9)

UART 1 (UART1).

Definition at line 329 of file sam4sd32c.h.

Referenced by usart_serial_init().

◆ ID_UDP

#define ID_UDP (34)

USB Device Port (UDP).

Definition at line 352 of file sam4sd32c.h.

◆ ID_USART0

#define ID_USART0 (14)

USART 0 (USART0).

Definition at line 334 of file sam4sd32c.h.

Referenced by usart_serial_init().

◆ ID_USART1

#define ID_USART1 (15)

USART 1 (USART1).

Definition at line 335 of file sam4sd32c.h.

Referenced by usart_serial_init().

◆ ID_WDT

#define ID_WDT ( 4)

Watchdog Timer (WDT).

Definition at line 324 of file sam4sd32c.h.

◆ IFLASH0_ADDR

#define IFLASH0_ADDR (0x00400000u)

Internal Flash 0 base address.

Definition at line 486 of file sam4sd32c.h.

◆ IFLASH0_LOCK_REGION_SIZE

#define IFLASH0_LOCK_REGION_SIZE (8192u)

Definition at line 475 of file sam4sd32c.h.

◆ IFLASH0_NB_OF_LOCK_BITS

#define IFLASH0_NB_OF_LOCK_BITS (128u)

Definition at line 477 of file sam4sd32c.h.

◆ IFLASH0_NB_OF_PAGES

#define IFLASH0_NB_OF_PAGES (2048u)

Definition at line 476 of file sam4sd32c.h.

◆ IFLASH0_PAGE_SIZE

#define IFLASH0_PAGE_SIZE (512u)

Definition at line 474 of file sam4sd32c.h.

◆ IFLASH0_SIZE

#define IFLASH0_SIZE (0x100000u)

Definition at line 473 of file sam4sd32c.h.

◆ IFLASH1_ADDR

#define IFLASH1_ADDR (IFLASH0_ADDR+IFLASH0_SIZE)

Internal Flash 1 base address.

Definition at line 488 of file sam4sd32c.h.

◆ IFLASH1_LOCK_REGION_SIZE

#define IFLASH1_LOCK_REGION_SIZE (8192u)

Definition at line 480 of file sam4sd32c.h.

◆ IFLASH1_NB_OF_LOCK_BITS

#define IFLASH1_NB_OF_LOCK_BITS (128u)

Definition at line 482 of file sam4sd32c.h.

◆ IFLASH1_NB_OF_PAGES

#define IFLASH1_NB_OF_PAGES (2048u)

Definition at line 481 of file sam4sd32c.h.

◆ IFLASH1_PAGE_SIZE

#define IFLASH1_PAGE_SIZE (512u)

Definition at line 479 of file sam4sd32c.h.

◆ IFLASH1_SIZE

#define IFLASH1_SIZE (0x100000u)

Definition at line 478 of file sam4sd32c.h.

◆ IFLASH_SIZE

#define IFLASH_SIZE (IFLASH0_SIZE+IFLASH1_SIZE)

Definition at line 484 of file sam4sd32c.h.

◆ IRAM_ADDR

#define IRAM_ADDR (0x20000000u)

Internal RAM base address.

Definition at line 491 of file sam4sd32c.h.

◆ IRAM_SIZE

#define IRAM_SIZE (0x28000u)

Definition at line 483 of file sam4sd32c.h.

◆ IROM_ADDR

#define IROM_ADDR (0x00800000u)

Internal ROM base address.

Definition at line 490 of file sam4sd32c.h.

◆ MATRIX

#define MATRIX ((Matrix *)0x400E0200U)

(MATRIX ) Base Address

Definition at line 438 of file sam4sd32c.h.

◆ NB_CH_ADC

#define NB_CH_ADC (15UL)

Definition at line 503 of file sam4sd32c.h.

◆ NB_CH_DAC

#define NB_CH_DAC (2UL)

Definition at line 504 of file sam4sd32c.h.

◆ PDC_ADC

#define PDC_ADC ((Pdc *)0x40038100U)

(PDC_ADC ) Base Address

Definition at line 431 of file sam4sd32c.h.

Referenced by adc_get_pdc_base().

◆ PDC_DACC

#define PDC_DACC ((Pdc *)0x4003C100U)

(PDC_DACC ) Base Address

Definition at line 433 of file sam4sd32c.h.

◆ PDC_HSMCI

#define PDC_HSMCI ((Pdc *)0x40000100U)

(PDC_HSMCI ) Base Address

Definition at line 412 of file sam4sd32c.h.

◆ PDC_PIOA

#define PDC_PIOA ((Pdc *)0x400E0F68U)

(PDC_PIOA ) Base Address

Definition at line 448 of file sam4sd32c.h.

Referenced by pio_capture_get_pdc_base().

◆ PDC_PWM

#define PDC_PWM ((Pdc *)0x40020100U)

(PDC_PWM ) Base Address

Definition at line 424 of file sam4sd32c.h.

◆ PDC_SPI

#define PDC_SPI ((Pdc *)0x40008100U)

(PDC_SPI ) Base Address

Definition at line 416 of file sam4sd32c.h.

◆ PDC_SSC

#define PDC_SSC ((Pdc *)0x40004100U)

(PDC_SSC ) Base Address

Definition at line 414 of file sam4sd32c.h.

◆ PDC_TWI0

#define PDC_TWI0 ((Pdc *)0x40018100U)

(PDC_TWI0 ) Base Address

Definition at line 420 of file sam4sd32c.h.

Referenced by twi_get_pdc_base().

◆ PDC_TWI1

#define PDC_TWI1 ((Pdc *)0x4001C100U)

(PDC_TWI1 ) Base Address

Definition at line 422 of file sam4sd32c.h.

Referenced by twi_get_pdc_base().

◆ PDC_UART0

#define PDC_UART0 ((Pdc *)0x400E0700U)

(PDC_UART0 ) Base Address

Definition at line 441 of file sam4sd32c.h.

◆ PDC_UART1

#define PDC_UART1 ((Pdc *)0x400E0900U)

(PDC_UART1 ) Base Address

Definition at line 444 of file sam4sd32c.h.

◆ PDC_USART0

#define PDC_USART0 ((Pdc *)0x40024100U)

(PDC_USART0) Base Address

Definition at line 426 of file sam4sd32c.h.

Referenced by usart_get_pdc_base().

◆ PDC_USART1

#define PDC_USART1 ((Pdc *)0x40028100U)

(PDC_USART1) Base Address

Definition at line 428 of file sam4sd32c.h.

Referenced by usart_get_pdc_base().

◆ PIOA

#define PIOA ((Pio *)0x400E0E00U)

(PIOA ) Base Address

Definition at line 447 of file sam4sd32c.h.

Referenced by pio_get_pin_group().

◆ PIOB

#define PIOB ((Pio *)0x400E1000U)

(PIOB ) Base Address

Definition at line 449 of file sam4sd32c.h.

◆ PIOC

#define PIOC ((Pio *)0x400E1200U)

(PIOC ) Base Address

Definition at line 450 of file sam4sd32c.h.

Referenced by arch_ioport_port_to_base(), and pio_get_pin_group().

◆ PMC

#define PMC ((Pmc *)0x400E0400U)

(PMC ) Base Address

Definition at line 439 of file sam4sd32c.h.

◆ PWM

#define PWM ((Pwm *)0x40020000U)

(PWM ) Base Address

Definition at line 423 of file sam4sd32c.h.

◆ RSTC

#define RSTC ((Rstc *)0x400E1400U)

(RSTC ) Base Address

Definition at line 451 of file sam4sd32c.h.

◆ RTC

#define RTC ((Rtc *)0x400E1460U)

(RTC ) Base Address

Definition at line 455 of file sam4sd32c.h.

◆ RTT

#define RTT ((Rtt *)0x400E1430U)

(RTT ) Base Address

Definition at line 453 of file sam4sd32c.h.

◆ SMC

#define SMC ((Smc *)0x400E0000U)

(SMC ) Base Address

Definition at line 437 of file sam4sd32c.h.

◆ SPI

#define SPI ((Spi *)0x40008000U)

(SPI ) Base Address

Definition at line 415 of file sam4sd32c.h.

◆ SSC

#define SSC ((Ssc *)0x40004000U)

(SSC ) Base Address

Definition at line 413 of file sam4sd32c.h.

◆ SUPC

#define SUPC ((Supc *)0x400E1410U)

(SUPC ) Base Address

Definition at line 452 of file sam4sd32c.h.

◆ TC0

#define TC0 ((Tc *)0x40010000U)

(TC0 ) Base Address

Definition at line 417 of file sam4sd32c.h.

◆ TC1

#define TC1 ((Tc *)0x40014000U)

(TC1 ) Base Address

Definition at line 418 of file sam4sd32c.h.

◆ TWI0

#define TWI0 ((Twi *)0x40018000U)

(TWI0 ) Base Address

Definition at line 419 of file sam4sd32c.h.

Referenced by twi_get_pdc_base(), twi_master_setup(), and twi_slave_setup().

◆ TWI1

#define TWI1 ((Twi *)0x4001C000U)

(TWI1 ) Base Address

Definition at line 421 of file sam4sd32c.h.

Referenced by twi_get_pdc_base(), twi_master_setup(), and twi_slave_setup().

◆ UART0

#define UART0 ((Uart *)0x400E0600U)

(UART0 ) Base Address

Definition at line 440 of file sam4sd32c.h.

Referenced by usart_serial_getchar(), usart_serial_init(), usart_serial_is_rx_ready(), and usart_serial_putchar().

◆ UART1

#define UART1 ((Uart *)0x400E0800U)

(UART1 ) Base Address

Definition at line 443 of file sam4sd32c.h.

Referenced by usart_serial_getchar(), usart_serial_init(), usart_serial_is_rx_ready(), and usart_serial_putchar().

◆ UDP

#define UDP ((Udp *)0x40034000U)

(UDP ) Base Address

Definition at line 429 of file sam4sd32c.h.

◆ USART0

#define USART0 ((Usart *)0x40024000U)

(USART0 ) Base Address

Definition at line 425 of file sam4sd32c.h.

Referenced by usart_get_pdc_base(), usart_init_modem(), usart_serial_getchar(), usart_serial_init(), usart_serial_is_rx_ready(), and usart_serial_putchar().

◆ USART1

#define USART1 ((Usart *)0x40028000U)

(USART1 ) Base Address

Definition at line 427 of file sam4sd32c.h.

Referenced by usart_get_pdc_base(), usart_init_modem(), usart_serial_getchar(), usart_serial_init(), usart_serial_is_rx_ready(), and usart_serial_putchar().

◆ USB_DEVICE_MAX_EP

#define USB_DEVICE_MAX_EP (8UL)

Definition at line 505 of file sam4sd32c.h.

◆ WDT

#define WDT ((Wdt *)0x400E1450U)

(WDT ) Base Address

Definition at line 454 of file sam4sd32c.h.

Typedef Documentation

◆ DeviceVectors

typedef struct _DeviceVectors DeviceVectors

◆ IRQn_Type

typedef enum IRQn IRQn_Type

< Interrupt Number Definition

Enumeration Type Documentation

◆ IRQn

enum IRQn

< Interrupt Number Definition

Enumerator
NonMaskableInt_IRQn	2 Non Maskable Interrupt
MemoryManagement_IRQn	4 Cortex-M4 Memory Management Interrupt
BusFault_IRQn	5 Cortex-M4 Bus Fault Interrupt
UsageFault_IRQn	6 Cortex-M4 Usage Fault Interrupt
SVCall_IRQn	11 Cortex-M4 SV Call Interrupt
DebugMonitor_IRQn	12 Cortex-M4 Debug Monitor Interrupt
PendSV_IRQn	14 Cortex-M4 Pend SV Interrupt
SysTick_IRQn	15 Cortex-M4 System Tick Interrupt
SUPC_IRQn	0 SAM4SD32C Supply Controller (SUPC)
RSTC_IRQn	1 SAM4SD32C Reset Controller (RSTC)
RTC_IRQn	2 SAM4SD32C Real Time Clock (RTC)
RTT_IRQn	3 SAM4SD32C Real Time Timer (RTT)
WDT_IRQn	4 SAM4SD32C Watchdog Timer (WDT)
PMC_IRQn	5 SAM4SD32C Power Management Controller (PMC)
EFC0_IRQn	6 SAM4SD32C Enhanced Embedded Flash Controller 0 (EFC0)
EFC1_IRQn	7 SAM4SD32C Enhanced Embedded Flash Controller 1 (EFC1)
UART0_IRQn	8 SAM4SD32C UART 0 (UART0)
UART1_IRQn	9 SAM4SD32C UART 1 (UART1)
PIOA_IRQn	11 SAM4SD32C Parallel I/O Controller A (PIOA)
PIOB_IRQn	12 SAM4SD32C Parallel I/O Controller B (PIOB)
PIOC_IRQn	13 SAM4SD32C Parallel I/O Controller C (PIOC)
USART0_IRQn	14 SAM4SD32C USART 0 (USART0)
USART1_IRQn	15 SAM4SD32C USART 1 (USART1)
HSMCI_IRQn	18 SAM4SD32C Multimedia Card Interface (HSMCI)
TWI0_IRQn	19 SAM4SD32C Two Wire Interface 0 (TWI0)
TWI1_IRQn	20 SAM4SD32C Two Wire Interface 1 (TWI1)
SPI_IRQn	21 SAM4SD32C Serial Peripheral Interface (SPI)
SSC_IRQn	22 SAM4SD32C Synchronous Serial Controller (SSC)
TC0_IRQn	23 SAM4SD32C Timer/Counter 0 (TC0)
TC1_IRQn	24 SAM4SD32C Timer/Counter 1 (TC1)
TC2_IRQn	25 SAM4SD32C Timer/Counter 2 (TC2)
TC3_IRQn	26 SAM4SD32C Timer/Counter 3 (TC3)
TC4_IRQn	27 SAM4SD32C Timer/Counter 4 (TC4)
TC5_IRQn	28 SAM4SD32C Timer/Counter 5 (TC5)
ADC_IRQn	29 SAM4SD32C Analog To Digital Converter (ADC)
DACC_IRQn	30 SAM4SD32C Digital To Analog Converter (DACC)
PWM_IRQn	31 SAM4SD32C Pulse Width Modulation (PWM)
CRCCU_IRQn	32 SAM4SD32C CRC Calculation Unit (CRCCU)
ACC_IRQn	33 SAM4SD32C Analog Comparator (ACC)
UDP_IRQn	34 SAM4SD32C USB Device Port (UDP)
PERIPH_COUNT_IRQn	Number of peripheral IDs.

Definition at line 62 of file sam4sd32c.h.

{
/******  Cortex-M4 Processor Exceptions Numbers ******************************/
  NonMaskableInt_IRQn   = -14, 
  MemoryManagement_IRQn = -12, 
  BusFault_IRQn         = -11, 
  UsageFault_IRQn       = -10, 
  SVCall_IRQn           = -5,  
  DebugMonitor_IRQn     = -4,  
  PendSV_IRQn           = -2,  
  SysTick_IRQn          = -1,  
/******  SAM4SD32C specific Interrupt Numbers *********************************/
 
  SUPC_IRQn            =  0, 
  RSTC_IRQn            =  1, 
  RTC_IRQn             =  2, 
  RTT_IRQn             =  3, 
  WDT_IRQn             =  4, 
  PMC_IRQn             =  5, 
  EFC0_IRQn            =  6, 
  EFC1_IRQn            =  7, 
  UART0_IRQn           =  8, 
  UART1_IRQn           =  9, 
  PIOA_IRQn            = 11, 
  PIOB_IRQn            = 12, 
  PIOC_IRQn            = 13, 
  USART0_IRQn          = 14, 
  USART1_IRQn          = 15, 
  HSMCI_IRQn           = 18, 
  TWI0_IRQn            = 19, 
  TWI1_IRQn            = 20, 
  SPI_IRQn             = 21, 
  SSC_IRQn             = 22, 
  TC0_IRQn             = 23, 
  TC1_IRQn             = 24, 
  TC2_IRQn             = 25, 
  TC3_IRQn             = 26, 
  TC4_IRQn             = 27, 
  TC5_IRQn             = 28, 
  ADC_IRQn             = 29, 
  DACC_IRQn            = 30, 
  PWM_IRQn             = 31, 
  CRCCU_IRQn           = 32, 
  ACC_IRQn             = 33, 
  UDP_IRQn             = 34, 
 
  PERIPH_COUNT_IRQn    = 35  
} IRQn_Type;

Function Documentation

◆ ACC_Handler()

void ACC_Handler ( void )

◆ ADC_Handler()

void ADC_Handler ( void )

◆ BusFault_Handler()

void BusFault_Handler ( void )

◆ CRCCU_Handler()

void CRCCU_Handler ( void )

◆ DACC_Handler()

void DACC_Handler ( void )

◆ DebugMon_Handler()

void DebugMon_Handler ( void )

◆ EFC0_Handler()

void EFC0_Handler ( void )

◆ EFC1_Handler()

void EFC1_Handler ( void )

◆ HardFault_Handler()

void HardFault_Handler ( void )

◆ HSMCI_Handler()

void HSMCI_Handler ( void )

◆ MemManage_Handler()

void MemManage_Handler ( void )

◆ NMI_Handler()

void NMI_Handler ( void )

◆ PendSV_Handler()

void PendSV_Handler ( void )

◆ PIOA_Handler()

void PIOA_Handler ( void )

◆ PIOB_Handler()

void PIOB_Handler ( void )

◆ PIOC_Handler()

void PIOC_Handler ( void )

◆ PMC_Handler()

void PMC_Handler ( void )

◆ PWM_Handler()

void PWM_Handler ( void )

◆ Reset_Handler()

void Reset_Handler ( void )

◆ RSTC_Handler()

void RSTC_Handler ( void )

◆ RTC_Handler()

void RTC_Handler ( void )

◆ RTT_Handler()

void RTT_Handler ( void )

◆ SPI_Handler()

void SPI_Handler ( void )

◆ SSC_Handler()

void SSC_Handler ( void )

◆ SUPC_Handler()

void SUPC_Handler ( void )

◆ SVC_Handler()

void SVC_Handler ( void )

◆ SysTick_Handler()

void SysTick_Handler ( void )

◆ TC0_Handler()

void TC0_Handler ( void )

◆ TC1_Handler()

void TC1_Handler ( void )

◆ TC2_Handler()

void TC2_Handler ( void )

◆ TC3_Handler()

void TC3_Handler ( void )

◆ TC4_Handler()

void TC4_Handler ( void )

◆ TC5_Handler()

void TC5_Handler ( void )

◆ TWI0_Handler()

void TWI0_Handler ( void )

◆ TWI1_Handler()

void TWI1_Handler ( void )

◆ UART0_Handler()

void UART0_Handler ( void )

◆ UART1_Handler()

void UART1_Handler ( void )

◆ UDP_Handler()

void UDP_Handler ( void )

◆ UsageFault_Handler()

void UsageFault_Handler ( void )

◆ USART0_Handler()

void USART0_Handler ( void )

◆ USART1_Handler()

void USART1_Handler ( void )

◆ WDT_Handler()

void WDT_Handler ( void )

Data Structures

Macros

Typedefs

Enumerations

Functions

Detailed Description

Macro Definition Documentation

◆ __CM4_REV

◆ __FPU_PRESENT

◆ __MPU_PRESENT

◆ __NVIC_PRIO_BITS

◆ __Vendor_SysTickConfig

◆ ACC

◆ ACC_ACR_HYST_50MV_MAX

◆ ACC_ACR_HYST_90MV_MAX

◆ ADC

◆ CHIP_CIDR

◆ CHIP_FLASH_WRITE_WAIT_STATE

◆ CHIP_FREQ_CPU_MAX

◆ CHIP_FREQ_FWS_0

◆ CHIP_FREQ_FWS_1

◆ CHIP_FREQ_FWS_2

◆ CHIP_FREQ_FWS_3

◆ CHIP_FREQ_FWS_4

◆ CHIP_FREQ_FWS_5

◆ CHIP_FREQ_MAINCK_RC_12MHZ

◆ CHIP_FREQ_MAINCK_RC_4MHZ

◆ CHIP_FREQ_MAINCK_RC_8MHZ

◆ CHIP_FREQ_SLCK_RC

◆ CHIP_FREQ_SLCK_RC_MAX

◆ CHIP_FREQ_SLCK_RC_MIN

◆ CHIP_FREQ_XTAL_32K

◆ CHIP_JTAGID

◆ CHIPID

◆ CMCC

◆ CRCCU

◆ DACC

◆ EBI_CS0_ADDR

◆ EBI_CS1_ADDR

◆ EBI_CS2_ADDR

◆ EBI_CS3_ADDR

◆ EFC0

◆ EFC1

◆ GPBR

◆ HSMCI

◆ ID_ACC

◆ ID_ADC

◆ ID_CRCCU

◆ ID_DACC

◆ ID_EFC0

◆ ID_EFC1

◆ ID_HSMCI

◆ ID_PERIPH_COUNT

◆ ID_PIOA

◆ ID_PIOB

◆ ID_PIOC

◆ ID_PMC

◆ ID_PWM

◆ ID_RSTC

◆ ID_RTC

◆ ID_RTT

◆ ID_SMC

◆ ID_SPI

◆ ID_SSC

◆ ID_SUPC

◆ ID_TC0

◆ ID_TC1

◆ ID_TC2

◆ ID_TC3

◆ ID_TC4

◆ ID_TC5

◆ ID_TWI0

◆ ID_TWI1

◆ ID_UART0

◆ ID_UART1

◆ ID_UDP

◆ ID_USART0

◆ ID_USART1

◆ ID_WDT

◆ IFLASH0_ADDR